hak5
/
wifipineapple-openwrt
mirror of https://github.com/hak5/wifipineapple-openwrt.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

major cleanup of the ar531x code, improved hardware detection and support for multiple ethernet interfaces 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6307 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Felix Fietkau 2007-02-16 09:23:15 +00:00
parent c55df2a7ed
commit b7e5e78ae6
14 changed files with 360 additions and 429 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

155
target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c
View File

@ -29,56 +29,55 @@
#include <asm/io.h>
#include "ar531x.h"
#define NO_PHY 0x1f
static int is_5312 = 0;
static struct platform_device *ar5312_devs[5];
static struct resource ar5312_eth0_res[] = {
{
.name = "eth_membase",
.name = "eth0_membase",
.flags = IORESOURCE_MEM,
.start = KSEG1ADDR(AR531X_ENET0),
.end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
},
{
.name = "eth_irq",
.name = "eth0_irq",
.flags = IORESOURCE_IRQ,
.start = AR5312_IRQ_ENET0_INTRS,
.end = AR5312_IRQ_ENET0_INTRS,
},
};
static struct ar531x_eth ar5312_eth0_data = {
.phy = NO_PHY,
.mac = 0,
.reset_base = AR531X_RESET,
.reset_mac = AR531X_RESET_ENET0,
.reset_phy = AR531X_RESET_EPHY0,
.phy_base = KSEG1ADDR(AR531X_ENET0),
};
static struct resource ar5312_eth1_res[] = {
{
.name = "eth_membase",
.name = "eth1_membase",
.flags = IORESOURCE_MEM,
.start = KSEG1ADDR(AR531X_ENET1),
.end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
},
{
.name = "eth_irq",
.name = "eth1_irq",
.flags = IORESOURCE_IRQ,
.start = AR5312_IRQ_ENET1_INTRS,
.end = AR5312_IRQ_ENET1_INTRS,
},
};
static struct ar531x_eth ar5312_eth0_data = {
.phy = 0x1f,
.mac = 0,
.reset_base = AR531X_RESET,
.reset_mac = AR531X_RESET_ENET0,
.reset_phy = AR531X_RESET_EPHY0,
};
static struct ar531x_eth ar5312_eth1_data = {
.phy = 0,
.phy = NO_PHY,
.mac = 1,
.reset_base = AR531X_RESET,
.reset_mac = AR531X_RESET_ENET1,
.reset_phy = AR531X_RESET_EPHY1,
.phy_base = KSEG1ADDR(AR531X_ENET1),
};
static struct platform_device ar5312_eth[] = {
@ -98,6 +97,42 @@ static struct platform_device ar5312_eth[] = {
},
};
/*
* AR2312/3 ethernet uses the PHY of ENET0, but the MAC
* of ENET1. Atheros calls it 'twisted' for a reason :)
*/
static struct resource ar231x_eth0_res[] = {
{
.name = "eth0_membase",
.flags = IORESOURCE_MEM,
.start = KSEG1ADDR(AR531X_ENET1),
.end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
},
{
.name = "eth0_irq",
.flags = IORESOURCE_IRQ,
.start = AR5312_IRQ_ENET1_INTRS,
.end = AR5312_IRQ_ENET1_INTRS,
},
};
static struct ar531x_eth ar231x_eth0_data = {
.phy = 1,
.mac = 1,
.reset_base = AR531X_RESET,
.reset_mac = AR531X_RESET_ENET1,
.reset_phy = AR531X_RESET_EPHY1,
.phy_base = KSEG1ADDR(AR531X_ENET0),
};
static struct platform_device ar231x_eth0 = {
.id = 0,
.name = "ar531x-eth",
.dev.platform_data = &ar231x_eth0_data,
.resource = ar231x_eth0_res,
.num_resources = ARRAY_SIZE(ar231x_eth0_res)
};
static struct platform_device ar5312_wmac[] = {
{
.id = 0,
@ -109,7 +144,6 @@ static struct platform_device ar5312_wmac[] = {
},
};
static struct physmap_flash_data ar5312_flash_data = {
.width = 2,
};
@ -139,7 +173,10 @@ static struct platform_device ar5312_physmap_flash = {
static char __init *ar5312_flash_limit(void)
{
u32 ctl;
/* Configure flash bank 0 */
/*
* Configure flash bank 0.
* Assume 8M window size. Flash will be aliased if it's smaller
*/
ctl = FLASHCTL_E |
FLASHCTL_AC_8M |
FLASHCTL_RBLE |
@ -157,7 +194,7 @@ static char __init *ar5312_flash_limit(void)
sysRegWrite(AR531X_FLASHCTL2,
sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
return (char *) KSEG1ADDR(AR531X_FLASH + 0x400000);
return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
}
static struct ar531x_config __init *init_wmac(int unit)
@ -175,20 +212,72 @@ static struct ar531x_config __init *init_wmac(int unit)
int __init ar5312_init_devices(void)
{
char *radio;
struct ar531x_boarddata *bcfg;
char *radio, *c;
int dev = 0;
if (mips_machtype != MACH_ATHEROS_AR5312)
if (!is_5312)
return 0;
/* Locate board/radio config data */
ar531x_find_config(ar5312_flash_limit());
bcfg = (struct ar531x_boarddata *) board_config;
/*
* Chip IDs and hardware detection for some Atheros
* models are really broken!
*
* Atheros uses a disabled WMAC0 and Silicon ID of AR5312
* as indication for AR2312, which is otherwise
* indistinguishable from the real AR5312.
*/
if (radio_config) {
radio = radio_config + AR531X_RADIO_MASK_OFF;
if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
bcfg->config |= BD_ISCASPER;
} else
radio = NULL;
/* AR2313 has CPU minor rev. 10 */
if ((current_cpu_data.processor_id & 0xff) == 0x0a)
mips_machtype = MACH_ATHEROS_AR2313;
/* AR2312 shares the same Silicon ID as AR5312 */
else if (bcfg->config & BD_ISCASPER)
mips_machtype = MACH_ATHEROS_AR2312;
/* Everything else is probably AR5312 or compatible */
else
mips_machtype = MACH_ATHEROS_AR5312;
ar5312_eth0_data.board_config = board_config;
ar5312_eth1_data.board_config = board_config;
ar5312_devs[dev++] = &ar5312_physmap_flash;
ar5312_eth0_data.macaddr = bcfg->enet0Mac;
ar5312_eth1_data.macaddr = bcfg->enet1Mac;
if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
/* ENET0 and ENET1 have the same mac.
* Increment the one from ENET1 */
c = bcfg->enet1Mac + 5;
while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
c--;
}
switch(mips_machtype) {
case MACH_ATHEROS_AR5312:
ar5312_devs[dev++] = &ar5312_eth[0];
ar5312_devs[dev++] = &ar5312_eth[1];
break;
case MACH_ATHEROS_AR2312:
case MACH_ATHEROS_AR2313:
ar5312_devs[dev++] = &ar231x_eth0;
ar5312_flash_data.width = 1;
break;
}
radio = radio_config + AR531X_RADIO_MASK_OFF;
if (radio) {
if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
ar5312_wmac[0].dev.platform_data = init_wmac(0);
ar5312_devs[dev++] = &ar5312_wmac[0];
@ -197,6 +286,7 @@ int __init ar5312_init_devices(void)
ar5312_wmac[1].dev.platform_data = init_wmac(1);
ar5312_devs[dev++] = &ar5312_wmac[1];
}
}
return platform_add_devices(ar5312_devs, dev);
}
@ -445,6 +535,25 @@ void __init ar5312_misc_intr_init(int irq_base)
setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
}
void __init ar5312_prom_init(void)
{
u32 memsize, memcfg, bank0AC, bank1AC;
is_5312 = 1;
/* Detect memory size */
memcfg = sysRegRead(AR531X_MEM_CFG1);
bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
+ (bank1AC ? (1 << (bank1AC+1)) : 0);
memsize <<= 20;
add_memory_region(0, memsize, BOOT_MEM_RAM);
/* Initialize it to AR5312 for now. Real detection will be done
* in ar5312_init_devices() */
mips_machtype = MACH_ATHEROS_AR5312;
}
void __init ar5312_plat_setup(void)
{

2
target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h
View File

@ -164,7 +164,7 @@
#define AR531X_REV_MAJ_S 4
#define AR531X_REV_MIN 0x000f
#define AR531X_REV_MIN_S 0
#define AR531X_REV_CHIP (REV_MAJ|REV_MIN)
#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
/* Major revision numbers, bits 7..4 of Revision ID register */
#define AR531X_REV_MAJ_AR5312 0x4

49
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c
View File

@ -28,15 +28,16 @@
#include <asm/io.h>
#include "ar531x.h"
static int is_5315 = 0;
static struct resource ar5315_eth_res[] = {
{
.name = "eth_membase",
.name = "eth0_membase",
.flags = IORESOURCE_MEM,
.start = AR5315_ENET0,
.end = AR5315_ENET0 + 0x2000,
},
{
.name = "eth_irq",
.name = "eth0_irq",
.flags = IORESOURCE_IRQ,
.start = AR5315_IRQ_ENET0_INTRS,
.end = AR5315_IRQ_ENET0_INTRS,
@ -49,6 +50,7 @@ static struct ar531x_eth ar5315_eth_data = {
.reset_base = AR5315_RESET,
.reset_mac = AR5315_RESET_ENET0,
.reset_phy = AR5315_RESET_EPHY0,
.phy_base = AR5315_ENET0
};
static struct platform_device ar5315_eth = {
@ -175,20 +177,40 @@ static char __init *ar5315_flash_limit(void)
int __init ar5315_init_devices(void)
{
struct ar531x_config *config;
struct ar531x_boarddata *bcfg;
u32 devid;
int dev = 0;
if (mips_machtype != MACH_ATHEROS_AR5315)
if (!is_5315)
return 0;
/* Find board configuration */
ar531x_find_config(ar5315_flash_limit());
bcfg = (struct ar531x_boarddata *) board_config;
#if 0
/* Detect the hardware based on the device ID */
devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
switch(devid) {
case 0x9:
mips_machtype = MACH_ATHEROS_AR2317;
break;
/* FIXME: how can we detect AR2316? */
case 0x8:
default:
mips_machtype = MACH_ATHEROS_AR2315;
break;
}
#endif
config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
config->board = board_config;
config->radio = radio_config;
config->unit = 0;
config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & REV_CHIP);
config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
ar5315_eth_data.board_config = board_config;
ar5315_eth_data.macaddr = bcfg->enet0Mac;
ar5315_wmac.dev.platform_data = config;
ar5315_devs[dev++] = &ar5315_eth;
@ -379,8 +401,6 @@ ar5315_misc_intr_enable(unsigned int irq)
}
sysRegWrite(AR5315_IMR, imr);
imr=sysRegRead(AR5315_IMR); /* flush write buffer */
//printk("enable Interrupt irq 0x%x imr 0x%x \n",irq,imr);
}
/* Disable the specified AR531X_MISC_IRQ interrupt */
@ -501,6 +521,23 @@ void ar5315_misc_intr_init(int irq_base)
setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
}
void __init ar5315_prom_init(void)
{
u32 memsize, memcfg;
is_5315 = 1;
memcfg = sysRegRead(AR5315_MEM_CFG);
memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
memsize <<= 3;
add_memory_region(0, memsize, BOOT_MEM_RAM);
/* Initialize it to AR2315 for now. Real detection will be done
* in ar5315_init_devices() */
mips_machtype = MACH_ATHEROS_AR2315;
}
void __init ar5315_plat_setup(void)
{
unsigned int config = read_c0_config();

34
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h
View File

@ -121,11 +121,11 @@
*/
#define AR5315_SREV (AR5315_DSLBASE + 0x0014)
#define REV_MAJ 0x00f0
#define REV_MAJ_S 4
#define REV_MIN 0x000f
#define REV_MIN_S 0
#define REV_CHIP (REV_MAJ|REV_MIN)
#define AR5315_REV_MAJ 0x00f0
#define AR5315_REV_MAJ_S 4
#define AR5315_REV_MIN 0x000f
#define AR5315_REV_MIN_S 0
#define AR5315_REV_CHIP (AR5315_REV_MAJ|AR5315_REV_MIN)
/*
* Interface Enable
@ -359,21 +359,21 @@
#define AR5315_PCICLK (AR5315_DSLBASE + 0x00a4)
#define PCICLK_INPUT_M 0x3
#define PCICLK_INPUT_S 0
#define AR5315_PCICLK_INPUT_M 0x3
#define AR5315_PCICLK_INPUT_S 0
#define PCICLK_PLLC_CLKM 0
#define PCICLK_PLLC_CLKM1 1
#define PCICLK_PLLC_CLKC 2
#define PCICLK_REF_CLK 3
#define AR5315_PCICLK_PLLC_CLKM 0
#define AR5315_PCICLK_PLLC_CLKM1 1
#define AR5315_PCICLK_PLLC_CLKC 2
#define AR5315_PCICLK_REF_CLK 3
#define PCICLK_DIV_M 0xc
#define PCICLK_DIV_S 2
#define AR5315_PCICLK_DIV_M 0xc
#define AR5315_PCICLK_DIV_S 2
#define PCICLK_IN_FREQ 0
#define PCICLK_IN_FREQ_DIV_6 1
#define PCICLK_IN_FREQ_DIV_8 2
#define PCICLK_IN_FREQ_DIV_10 3
#define AR5315_PCICLK_IN_FREQ 0
#define AR5315_PCICLK_IN_FREQ_DIV_6 1
#define AR5315_PCICLK_IN_FREQ_DIV_8 2
#define AR5315_PCICLK_IN_FREQ_DIV_10 3
/*
* Observation Control Register

34
target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h
View File

@ -1,10 +1,34 @@
#ifndef __AR531X_H
#define __AR531X_H
#include <asm/cpu-info.h>
#include <ar531x_platform.h>
#include "ar5312.h"
#include "ar5315.h"
/*
* Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
* using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
*/
#ifdef CONFIG_ATHEROS_AR5312
#define DO_AR5312(...) \
if (current_cpu_data.cputype != CPU_4KEC) { \
__VA_ARGS__ \
}
#else
#define DO_AR5312(...)
#endif
#ifdef CONFIG_ATHEROS_AR5315
#define DO_AR5315(...) \
if (current_cpu_data.cputype == CPU_4KEC) { \
__VA_ARGS__ \
}
#else
#define DO_AR5315(...)
#endif
#define MIPS_CPU_IRQ_BASE 0x00
#define AR531X_HIGH_PRIO 0x10
#define AR531X_MISC_IRQ_BASE 0x20
@ -89,18 +113,20 @@ struct ar531x_boarddata {
u8 wlan1Mac[6]; /* (ar5212) */
};
#define BOARD_CONFIG_BUFSZ 0x1000
extern char *board_config;
extern char *radio_config;
extern char *board_config, *radio_config;
extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
extern int ar531x_find_config(char *flash_limit);
extern void ar5312_prom_init(void);
extern void ar5312_misc_intr_init(int irq_base);
extern void ar5312_irq_dispatch(void);
extern void ar5312_plat_setup(void);
extern asmlinkage void ar5312_irq_dispatch(void);
extern void ar5315_prom_init(void);
extern void ar5315_misc_intr_init(int irq_base);
extern asmlinkage void ar5315_irq_dispatch(void);
extern void ar5315_plat_setup(void);
extern asmlinkage void ar5315_irq_dispatch(void);
#endif

36
target/linux/atheros-2.6/files/arch/mips/atheros/board.c
View File

@ -106,7 +106,7 @@ int __init ar531x_find_config(char *flash_limit)
if (!bcfg)
return -ENODEV;
board_config = kmalloc(0x1000, GFP_KERNEL);
board_config = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
memcpy(board_config, bcfg, 0x100);
/* Radio config starts 0x100 bytes after board config, regardless
@ -116,9 +116,9 @@ int __init ar531x_find_config(char *flash_limit)
if (!rcfg)
return -ENODEV;
printk("Radio config found at offset 0x%x\n", rcfg - bcfg);
radio_config = board_config + 0x100 + ((rcfg - bcfg) & 0xfff);
rcfg_size = 0x1000 - ((rcfg - bcfg) & 0xfff);
printk("Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, radio_config - board_config);
rcfg_size = BOARD_CONFIG_BUFSZ - ((rcfg - bcfg) & (BOARD_CONFIG_BUFSZ - 1));
memcpy(radio_config, rcfg, rcfg_size);
return 0;
@ -143,18 +143,8 @@ void __init serial_setup(unsigned long mapbase, unsigned int uartclk)
void __init plat_mem_setup(void)
{
switch(mips_machtype) {
#ifdef CONFIG_ATHEROS_AR5312
case MACH_ATHEROS_AR5312:
ar5312_plat_setup();
break;
#endif
#ifdef CONFIG_ATHEROS_AR5315
case MACH_ATHEROS_AR5315:
ar5315_plat_setup();
break;
#endif
}
DO_AR5312(ar5312_plat_setup();)
DO_AR5315(ar5315_plat_setup();)
/* Disable data watchpoints */
write_c0_watchlo0(0);
@ -166,10 +156,22 @@ const char *get_system_type(void)
#ifdef CONFIG_ATHEROS_AR5312
case MACH_ATHEROS_AR5312:
return "Atheros AR5312\n";
case MACH_ATHEROS_AR2312:
return "Atheros AR2312\n";
case MACH_ATHEROS_AR2313:
return "Atheros AR2313\n";
#endif
#ifdef CONFIG_ATHEROS_AR5315
case MACH_ATHEROS_AR5315:
return "Atheros AR5315\n";
case MACH_ATHEROS_AR2315:
return "Atheros AR2315\n";
case MACH_ATHEROS_AR2316:
return "Atheros AR2316\n";
case MACH_ATHEROS_AR2317:
return "Atheros AR2317\n";
case MACH_ATHEROS_AR2318:
return "Atheros AR2318\n";
#endif
}
return "Atheros (unknown)";

20
target/linux/atheros-2.6/files/arch/mips/atheros/irq.c
View File

@ -67,14 +67,8 @@ static struct irqaction spurious_misc = {
asmlinkage void plat_irq_dispatch(void)
{
#ifdef CONFIG_ATHEROS_AR5312
if (mips_machtype == MACH_ATHEROS_AR5312)
ar5312_irq_dispatch();
#endif
#ifdef CONFIG_ATHEROS_AR5315
if (mips_machtype == MACH_ATHEROS_AR5315)
ar5315_irq_dispatch();
#endif
DO_AR5312(ar5312_irq_dispatch();)
DO_AR5315(ar5315_irq_dispatch();)
}
void __init arch_init_irq(void)
@ -83,14 +77,8 @@ void __init arch_init_irq(void)
mips_cpu_irq_init(0);
/* Initialize interrupt controllers */
#ifdef CONFIG_ATHEROS_AR5312
if (mips_machtype == MACH_ATHEROS_AR5312)
ar5312_misc_intr_init(AR531X_MISC_IRQ_BASE);
#endif
#ifdef CONFIG_ATHEROS_AR5315
if (mips_machtype == MACH_ATHEROS_AR5315)
ar5315_misc_intr_init(AR531X_MISC_IRQ_BASE);
#endif
DO_AR5312(ar5312_misc_intr_init(AR531X_MISC_IRQ_BASE);)
DO_AR5315(ar5315_misc_intr_init(AR531X_MISC_IRQ_BASE);)
/* Default "spurious interrupt" handlers */
setup_irq(AR531X_IRQ_NONE, &spurious_irq);

29
target/linux/atheros-2.6/files/arch/mips/atheros/prom.c
View File

@ -27,38 +27,13 @@
void __init prom_init(void)
{
u32 memsize, memcfg;
mips_machgroup = MACH_GROUP_ATHEROS;
mips_machtype = -1;
/*
* Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
* using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
*/
DO_AR5312(ar5312_prom_init();)
DO_AR5315(ar5315_prom_init();)
if (current_cpu_data.cputype == CPU_4KEC) {
mips_machtype = MACH_ATHEROS_AR5315;
memcfg = sysRegRead(AR5315_MEM_CFG);
memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
memsize <<= 3;
} else {
int bank0AC, bank1AC;
mips_machtype = MACH_ATHEROS_AR5312;
memcfg = sysRegRead(AR531X_MEM_CFG1);
bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
+ (bank1AC ? (1 << (bank1AC+1)) : 0);
memsize <<= 20;
}
add_memory_region(0, memsize, BOOT_MEM_RAM);
strcpy(arcs_cmdline, "console=ttyS0,9600 rootfstype=squashfs,jffs2");
}

266
target/linux/atheros-2.6/files/drivers/net/ar2313/ar2313.c
View File

@ -1,9 +1,9 @@
/*
* ar2313.c: Linux driver for the Atheros AR231z Ethernet device.
* ar2313.c: Linux driver for the Atheros AR231x Ethernet device.
*
* Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
*
* Thanks to Atheros for providing hardware and documentation
* enabling me to write this driver.
@ -50,7 +50,10 @@
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <ar531x_platform.h>
#define AR2313_MTU 1692
#define AR2313_PRIOS 1
#define AR2313_QUEUES (2*AR2313_PRIOS)
#define AR2313_DESCR_ENTRIES 64
#undef INDEX_DEBUG
#define DEBUG 0
@ -68,27 +71,11 @@
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#endif
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) {do{} while(0);}
#define AR2313_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define AR2313_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#else
#define AR2313_MOD_INC_USE_COUNT {do{} while(0);}
#define AR2313_MOD_DEC_USE_COUNT {do{} while(0);}
#endif
#define PHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff)
static char ifname[5] = "bond";
module_param_string(ifname, ifname, 5, 0);
#define AR2313_MBOX_SET_BIT 0x8
#define BOARD_IDX_STATIC 0
#define BOARD_IDX_OVERFLOW -1
#include "ar2313_msg.h"
#include "platform.h"
#include "dma.h"
#include "ar2313.h"
@ -154,16 +141,11 @@ MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@open
MODULE_DESCRIPTION("AR2313 Ethernet driver");
#endif
#if DEBUG
static char version[] __initdata =
"ar2313.c: v0.03 2006/07/12 sdekate@arubanetworks.com\n";
#endif /* DEBUG */
#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
// prototypes
static short armiiread(short phy, short reg);
static void armiiwrite(short phy, short reg, short data);
static short armiiread(struct net_device *dev, short phy, short reg);
static void armiiwrite(struct net_device *dev, short phy, short reg, short data);
#ifdef TX_TIMEOUT
static void ar2313_tx_timeout(struct net_device *dev);
#endif
@ -171,13 +153,6 @@ static void ar2313_halt(struct net_device *dev);
static void rx_tasklet_func(unsigned long data);
static void ar2313_multicast_list(struct net_device *dev);
static int probed __initdata = 0;
static unsigned long ar_eth_base;
static unsigned long ar_dma_base;
static unsigned long ar_int_base;
static unsigned long ar_int_mac_mask;
static unsigned long ar_int_phy_mask;
#ifndef ERR
#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
#endif
@ -187,17 +162,10 @@ int __init ar2313_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ar2313_private *sp;
struct ar531x_eth *cfg;
struct resource *res;
int version_disp;
char name[64] ;
unsigned long ar_eth_base;
char buf[64] ;
if (probed)
return -ENODEV;
probed++;
version_disp = 0;
sprintf(name, "%s%%d", ifname) ;
dev = alloc_etherdev(sizeof(struct ar2313_private));
if (dev == NULL) {
@ -210,21 +178,19 @@ int __init ar2313_probe(struct platform_device *pdev)
sp = dev->priv;
sp->dev = dev;
cfg = pdev->dev.platform_data;
sp->cfg = pdev->dev.platform_data;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth_membase");
sprintf(buf, "eth%d_membase", pdev->id);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
if (!res)
return -ENODEV;
sp->link = 0;
ar_eth_base = res->start;
ar_dma_base = ar_eth_base + 0x1000;
ar_int_base = cfg->reset_base;
ar_int_mac_mask = cfg->reset_mac;
ar_int_phy_mask = cfg->reset_phy;
sp->phy = cfg->phy;
sp->phy = sp->cfg->phy;
dev->irq = platform_get_irq_byname(pdev, "eth_irq");
sprintf(buf, "eth%d_irq", pdev->id);
dev->irq = platform_get_irq_byname(pdev, buf);
spin_lock_init(&sp->lock);
@ -247,61 +213,43 @@ int __init ar2313_probe(struct platform_device *pdev)
tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
tasklet_disable(&sp->rx_tasklet);
/* display version info if adapter is found */
if (!version_disp) {
/* set display flag to TRUE so that */
/* we only display this string ONCE */
version_disp = 1;
#if DEBUG
printk(version);
#endif /* DEBUG */
}
#if 0
request_region(PHYSADDR(ar_eth_base), ETHERNET_SIZE*ETHERNET_MACS,
"AR2313ENET");
#endif
sp->eth_regs = ioremap_nocache(PHYSADDR(ar_eth_base), sizeof(*sp->eth_regs));
sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
if (!sp->eth_regs) {
printk("Can't remap eth registers\n");
return(-ENXIO);
}
sp->dma_regs = ioremap_nocache(PHYSADDR(ar_eth_base + 0x1000), sizeof(*sp->dma_regs));
/*
* When there's only one MAC, PHY regs are typically on ENET0,
* even though the MAC might be on ENET1.
* Needto remap PHY regs separately in this case
*/
if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
sp->phy_regs = sp->eth_regs;
else {
sp->phy_regs = ioremap_nocache(virt_to_phys(sp->cfg->phy_base), sizeof(*sp->phy_regs));
if (!sp->phy_regs) {
printk("Can't remap phy registers\n");
return(-ENXIO);
}
}
sp->dma_regs = ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), sizeof(*sp->dma_regs));
dev->base_addr = (unsigned int) sp->dma_regs;
if (!sp->dma_regs) {
printk("Can't remap DMA registers\n");
return(-ENXIO);
}
sp->int_regs = ioremap_nocache(PHYSADDR(ar_int_base), 4);
sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
if (!sp->int_regs) {
printk("Can't remap INTERRUPT registers\n");
return(-ENXIO);
}
strncpy(sp->name, "Atheros AR2313", sizeof (sp->name) - 1);
strncpy(sp->name, "Atheros AR231x", sizeof (sp->name) - 1);
sp->name [sizeof (sp->name) - 1] = '\0';
{
/* XXX: Will have to rewrite this part later */
char *configstart;
unsigned char def_mac[6] = {0, 0xaa, 0xbb, 0xcc, 0xdd, 0xee};
configstart = (char *) cfg->board_config;
if (!configstart) {
printk("no valid mac found, using defaults");
memcpy(dev->dev_addr, def_mac, 6);
} else {
memcpy(dev->dev_addr, ((u8 *)configstart)+102, 6);
/* use the other MAC slot if the first one is empty */
if (!memcmp(dev->dev_addr, "\xff\xff\xff\xff\xff\xff", 6))
memcpy(dev->dev_addr, ((u8 *)configstart)+102 + 6, 6);
}
}
memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
sp->board_idx = BOARD_IDX_STATIC;
if (ar2313_init(dev)) {
@ -546,7 +494,7 @@ static int ar2313_allocate_descriptors(struct net_device *dev)
td->status = 0;
td->devcs = DMA_TX1_CHAINED;
td->addr = 0;
td->descr = K1_TO_PHYS(&sp->tx_ring[(j+1) & (AR2313_DESCR_ENTRIES-1)]);
td->descr = virt_to_phys(&sp->tx_ring[(j+1) & (AR2313_DESCR_ENTRIES-1)]);
}
return 0;
@ -632,7 +580,7 @@ static void ar2313_check_link(struct net_device *dev)
struct ar2313_private *sp = dev->priv;
u16 phyData;
phyData = armiiread(sp->phy, MII_BMSR);
phyData = armiiread(dev, sp->phy, MII_BMSR);
if (sp->phyData != phyData) {
if (phyData & BMSR_LSTATUS) {
/* link is present, ready link partner ability to deterine duplexity */
@ -640,10 +588,10 @@ static void ar2313_check_link(struct net_device *dev)
u16 reg;
sp->link = 1;
reg = armiiread(sp->phy, MII_BMCR);
reg = armiiread(dev, sp->phy, MII_BMCR);
if (reg & BMCR_ANENABLE) {
/* auto neg enabled */
reg = armiiread(sp->phy, MII_LPA);
reg = armiiread(dev, sp->phy, MII_LPA);
duplex = (reg & (LPA_100FULL|LPA_10FULL))? 1:0;
} else {
/* no auto neg, just read duplex config */
@ -677,13 +625,13 @@ ar2313_reset_reg(struct net_device *dev)
unsigned int ethsal, ethsah;
unsigned int flags;
*sp->int_regs |= ar_int_mac_mask;
*sp->int_regs |= sp->cfg->reset_mac;
mdelay(10);
*sp->int_regs &= ~ar_int_mac_mask;
*sp->int_regs &= ~sp->cfg->reset_mac;
mdelay(10);
*sp->int_regs |= ar_int_phy_mask;
*sp->int_regs |= sp->cfg->reset_phy;
mdelay(10);
*sp->int_regs &= ~ar_int_phy_mask;
*sp->int_regs &= ~sp->cfg->reset_phy;
mdelay(10);
sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
@ -696,8 +644,8 @@ ar2313_reset_reg(struct net_device *dev)
DMA_STATUS_RI |
DMA_STATUS_TI |
DMA_STATUS_FBE);
sp->dma_regs->xmt_base = K1_TO_PHYS(sp->tx_ring);
sp->dma_regs->rcv_base = K1_TO_PHYS(sp->rx_ring);
sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
sp->dma_regs->control = (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
@ -947,23 +895,11 @@ static int ar2313_rx_int(struct net_device *dev)
/* set skb */
skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
#ifdef CONFIG_MERLOT
if ((dev->am_pkt_handler == NULL) ||
(dev->am_pkt_handler(skb, dev) == 0)) {
#endif
sp->stats.rx_bytes += skb->len;
skb->protocol = eth_type_trans(skb, dev);
/* pass the packet to upper layers */
#ifdef CONFIG_MERLOT
if (dev->asap_netif_rx)
dev->asap_netif_rx(skb);
else
#endif
netif_rx(skb);
#ifdef CONFIG_MERLOT
}
#endif
skb_new->dev = dev;
/* 16 bit align */
skb_reserve(skb_new, RX_OFFSET+32);
@ -972,7 +908,6 @@ static int ar2313_rx_int(struct net_device *dev)
sp->stats.rx_packets++;
sp->rx_skb[idx] = skb_new;
} else {
sp->stats.rx_dropped++;
}
@ -1138,8 +1073,6 @@ static int ar2313_open(struct net_device *dev)
sp->eth_regs->mac_control |= MAC_CONTROL_RE;
AR2313_MOD_INC_USE_COUNT;
return 0;
}
@ -1158,7 +1091,7 @@ static void ar2313_halt(struct net_device *dev)
sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
/* place phy and MAC in reset */
*sp->int_regs |= (ar_int_mac_mask | ar_int_phy_mask);
*sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
/* free buffers on tx ring */
for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
@ -1208,7 +1141,6 @@ static int ar2313_close(struct net_device *dev)
free_irq(dev->irq, dev);
#endif
AR2313_MOD_DEC_USE_COUNT;
return 0;
}
@ -1255,8 +1187,6 @@ static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev)
idx = DSC_NEXT(idx);
sp->tx_prd = idx;
//dev->trans_start = jiffies;
return 0;
}
@ -1277,7 +1207,7 @@ static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
ecmd->phy_address = 1;
ecmd->advertising = ADVERTISED_MII;
tmp = armiiread(np->phy, MII_ADVERTISE);
tmp = armiiread(dev, np->phy, MII_ADVERTISE);
if (tmp & ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
if (tmp & ADVERTISE_10FULL)
@ -1287,7 +1217,7 @@ static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
if (tmp & ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
tmp = armiiread(np->phy, MII_BMCR);
tmp = armiiread(dev, np->phy, MII_BMCR);
if (tmp & BMCR_ANENABLE) {
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->autoneg = AUTONEG_ENABLE;
@ -1296,7 +1226,7 @@ static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
}
if (ecmd->autoneg == AUTONEG_ENABLE) {
tmp = armiiread(np->phy, MII_LPA);
tmp = armiiread(dev, np->phy, MII_LPA);
if (tmp & (LPA_100FULL|LPA_10FULL)) {
ecmd->duplex = DUPLEX_FULL;
} else {
@ -1344,7 +1274,7 @@ static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
/* WHEW! now lets bang some bits */
tmp = armiiread(np->phy, MII_BMCR);
tmp = armiiread(dev, np->phy, MII_BMCR);
if (ecmd->autoneg == AUTONEG_ENABLE) {
/* turn on autonegotiation */
tmp |= BMCR_ANENABLE;
@ -1360,7 +1290,7 @@ static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
(ecmd->speed == SPEED_100)? 100:10,
(ecmd->duplex == DUPLEX_FULL)? "full":"half");
}
armiiwrite(np->phy, MII_BMCR, tmp);
armiiwrite(dev, np->phy, MII_BMCR, tmp);
np->phyData = 0;
return 0;
}
@ -1400,10 +1330,10 @@ static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
int tmp;
int r = -EINVAL;
/* if autoneg is off, it's an error */
tmp = armiiread(np->phy, MII_BMCR);
tmp = armiiread(dev, np->phy, MII_BMCR);
if (tmp & BMCR_ANENABLE) {
tmp |= (BMCR_ANRESTART);
armiiwrite(np->phy, MII_BMCR, tmp);
armiiwrite(dev, np->phy, MII_BMCR, tmp);
r = 0;
}
return r;
@ -1411,7 +1341,7 @@ static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
/* get link status */
case ETHTOOL_GLINK: {
struct ethtool_value edata = {ETHTOOL_GLINK};
edata.data = (armiiread(np->phy, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
edata.data = (armiiread(dev, np->phy, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
if (copy_to_user(useraddr, &edata, sizeof(edata)))
return -EFAULT;
return 0;
@ -1426,57 +1356,6 @@ static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
switch (cmd) {
case SIOCDEVPRIVATE: {
struct ar2313_cmd scmd;
if (copy_from_user(&scmd, ifr->ifr_data, sizeof(scmd)))
return -EFAULT;
#if DEBUG
printk("%s: ioctl devprivate c=%d a=%x l=%d m=%d d=%x,%x\n",
dev->name, scmd.cmd,
scmd.address, scmd.length,
scmd.mailbox, scmd.data[0], scmd.data[1]);
#endif /* DEBUG */
switch (scmd.cmd) {
case AR2313_READ_DATA:
if(scmd.length==4){
scmd.data[0] = *((u32*)scmd.address);
} else if(scmd.length==2) {
scmd.data[0] = *((u16*)scmd.address);
} else if (scmd.length==1) {
scmd.data[0] = *((u8*)scmd.address);
} else {
return -EOPNOTSUPP;
}
if(copy_to_user(ifr->ifr_data, &scmd, sizeof(scmd)))
return -EFAULT;
break;
case AR2313_WRITE_DATA:
if(scmd.length==4){
*((u32*)scmd.address) = scmd.data[0];
} else if(scmd.length==2) {
*((u16*)scmd.address) = scmd.data[0];
} else if (scmd.length==1) {
*((u8*)scmd.address) = scmd.data[0];
} else {
return -EOPNOTSUPP;
}
break;
case AR2313_GET_VERSION:
// SAMEER: sprintf((char*) &scmd, "%s", ARUBA_VERSION);
if(copy_to_user(ifr->ifr_data, &scmd, sizeof(scmd)))
return -EFAULT;
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
case SIOCETHTOOL:
return netdev_ethtool_ioctl(dev, (void *) ifr->ifr_data);
@ -1486,15 +1365,13 @@ static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
/* Fall Through */
case SIOCGMIIREG: /* Read MII PHY register. */
case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
data->val_out = armiiread(data->phy_id & 0x1f,
data->val_out = armiiread(dev, data->phy_id & 0x1f,
data->reg_num & 0x1f);
return 0;
case SIOCSMIIREG: /* Write MII PHY register. */
case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
if (!capable(CAP_NET_ADMIN))
return -EPERM;
armiiwrite(data->phy_id & 0x1f,
armiiwrite(dev, data->phy_id & 0x1f,
data->reg_num & 0x1f, data->val_in);
return 0;
@ -1521,28 +1398,29 @@ static struct net_device_stats *ar2313_get_stats(struct net_device *dev)
return &sp->stats;
}
static short
armiiread(short phy, short reg)
{
volatile ETHERNET_STRUCT * ethernet;
ethernet = (volatile ETHERNET_STRUCT *)(ar_eth_base); /* always MAC 0 */
ethernet->mii_addr = ((reg << MII_ADDR_REG_SHIFT) |
(phy << MII_ADDR_PHY_SHIFT));
#define MII_ADDR(phy, reg) \
((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
static short
armiiread(struct net_device *dev, short phy, short reg)
{
struct ar2313_private *sp = (struct ar2313_private *)dev->priv;
volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
ethernet->mii_addr = MII_ADDR(phy, reg);
while (ethernet->mii_addr & MII_ADDR_BUSY);
return (ethernet->mii_data >> MII_DATA_SHIFT);
}
static void
armiiwrite(short phy, short reg, short data)
armiiwrite(struct net_device *dev, short phy, short reg, short data)
{
volatile ETHERNET_STRUCT * ethernet;
struct ar2313_private *sp = (struct ar2313_private *)dev->priv;
volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
ethernet = (volatile ETHERNET_STRUCT *)(ar_eth_base); /* always MAC 0 */
while (ethernet->mii_addr & MII_ADDR_BUSY);
ethernet->mii_data = data << MII_DATA_SHIFT;
ethernet->mii_addr = ((reg << MII_ADDR_REG_SHIFT) |
(phy << MII_ADDR_PHY_SHIFT) |
MII_ADDR_WRITE);
ethernet->mii_addr = MII_ADDR(phy, reg) | MII_ADDR_WRITE;
}

42
target/linux/atheros-2.6/files/drivers/net/ar2313/ar2313.h
View File

@ -3,56 +3,18 @@
#include <linux/autoconf.h>
#include <asm/bootinfo.h>
#include <ar531x_platform.h>
#include "platform.h"
extern unsigned long mips_machtype;
#undef ETHERNET_BASE
#define ETHERNET_BASE ar_eth_base
#define ETHERNET_SIZE 0x00100000
#define ETHERNET_MACS 2
#undef DMA_BASE
#define DMA_BASE ar_dma_base
#define DMA_SIZE 0x00100000
/*
* probe link timer - 5 secs
*/
#define LINK_TIMER (5*HZ)
/*
* Interrupt register base address
*/
#define INTERRUPT_BASE PHYS_TO_K1(ar_int_base)
/*
* Reset Register
*/
#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
#define RESET_SYSTEM 0x00000001 /* cold reset full system */
#define RESET_PROC 0x00000002 /* cold reset MIPS core */
#define RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
#define RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
#define RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
#define RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
#define RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
#ifndef K1_TO_PHYS
// hack
#define K1_TO_PHYS(x) (((unsigned int)(x)) & 0x1FFFFFFF) /* kseg1 to physical */
#endif
#ifndef PHYS_TO_K1
// hack
#define PHYS_TO_K1(x) (((unsigned int)(x)) | 0xA0000000) /* physical to kseg1 */
#endif
#define AR2313_TX_TIMEOUT (HZ/4)
/*
@ -111,9 +73,11 @@ struct ar2313_private
int version;
u32 mb[2];
volatile ETHERNET_STRUCT *phy_regs;
volatile ETHERNET_STRUCT *eth_regs;
volatile DMA *dma_regs;
volatile u32 *int_regs;
struct ar531x_eth *cfg;
spinlock_t lock; /* Serialise access to device */

13
target/linux/atheros-2.6/files/drivers/net/ar2313/dma.h
View File

@ -127,9 +127,14 @@
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
typedef struct {
volatile unsigned int status; // OWN, Device control and status.
volatile unsigned int devcs; // pkt Control bits + Length
volatile unsigned int addr; // Current Address.
volatile unsigned int descr; // Next descriptor in chain.
} ar2313_descr_t;
#endif // __ARUBA_DMA_H__

60
target/linux/atheros-2.6/files/drivers/net/ar2313/platform.h
View File

@ -17,43 +17,6 @@
#ifndef PLATFORM_H
#define PLATFORM_H
#define BIT(x) (1 << (x))
#define RESET_BASE 0xBC003020
#define RESET_VALUE 0x00000001
/********************************************************************
* Device controller
********************************************************************/
typedef struct {
volatile unsigned int flash0;
} DEVICE;
#define device (*((volatile DEVICE *) DEV_CTL_BASE))
// DDRC register
#define DEV_WP (1<<26)
/********************************************************************
* DDR controller
********************************************************************/
typedef struct {
volatile unsigned int ddrc0;
volatile unsigned int ddrc1;
volatile unsigned int ddrrefresh;
} DDR;
#define ddr (*((volatile DDR *) DDR_BASE))
// DDRC register
#define DDRC_CS(i) ((i&0x3)<<0)
#define DDRC_WE (1<<2)
/********************************************************************
* Ethernet interfaces
********************************************************************/
#define ETHERNET_BASE 0xB8200000
//
// New Combo structure for Both Eth0 AND eth1
//
@ -84,27 +47,9 @@ typedef struct {
volatile unsigned int reset_control; /* 0x20 */
} INTERRUPT;
#define interrupt (*((volatile INTERRUPT *) INTERRUPT_BASE))
#define INTERRUPT_MISC_TIMER BIT(0)
#define INTERRUPT_MISC_AHBPROC BIT(1)
#define INTERRUPT_MISC_AHBDMA BIT(2)
#define INTERRUPT_MISC_GPIO BIT(3)
#define INTERRUPT_MISC_UART BIT(4)
#define INTERRUPT_MISC_UARTDMA BIT(5)
#define INTERRUPT_MISC_WATCHDOG BIT(6)
#define INTERRUPT_MISC_LOCAL BIT(7)
#define INTERRUPT_GLOBAL_ETH BIT(2)
#define INTERRUPT_GLOBAL_WLAN BIT(3)
#define INTERRUPT_GLOBAL_MISC BIT(4)
#define INTERRUPT_GLOBAL_ITIMER BIT(5)
/********************************************************************
* DMA controller
********************************************************************/
#define DMA_BASE 0xB8201000
typedef struct {
volatile unsigned int bus_mode; /* 0x00 (CSR0) */
volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
@ -120,9 +65,4 @@ typedef struct {
volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
} DMA;
#define dma (*((volatile DMA *) DMA_BASE))
// macro to convert from virtual to physical address
#define phys_addr(x) (x & 0x1fffffff)
#endif /* PLATFORM_H */

2
target/linux/atheros-2.6/files/include/asm-mips/mach-atheros/ar531x_platform.h
View File

@ -20,7 +20,9 @@ struct ar531x_eth {
u32 reset_base;
u32 reset_mac;
u32 reset_phy;
u32 phy_base;
char *board_config;
char *macaddr;
};
#endif /* __AR531X_PLATFORM_H */

11
target/linux/atheros-2.6/patches/100-board.patch
View File

@ -46,7 +46,7 @@ diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
--- linux.old/include/asm-mips/bootinfo.h 2007-02-02 23:55:52.913446632 +0100
+++ linux.dev/include/asm-mips/bootinfo.h 2007-02-03 17:51:02.531494032 +0100
@@ -212,6 +212,13 @@
@@ -212,6 +212,18 @@
#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
@ -54,8 +54,13 @@ diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/booti
+ * Valid machtype for group ATHEROS
+ */
+#define MACH_GROUP_ATHEROS 26
+#define MACH_ATHEROS_AR5312 0 /* Atheros AR5312, AR2312/3/4 */
+#define MACH_ATHEROS_AR5315 1 /* Atheros AR2315/6/7/8 */
+#define MACH_ATHEROS_AR5312 0
+#define MACH_ATHEROS_AR2312 1
+#define MACH_ATHEROS_AR2313 2
+#define MACH_ATHEROS_AR2315 3
+#define MACH_ATHEROS_AR2316 4
+#define MACH_ATHEROS_AR2317 5
+#define MACH_ATHEROS_AR2318 6
+
#define CL_SIZE COMMAND_LINE_SIZE