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wifipineapple-openwrt
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final fix for BCM5354 USB cores, hopefully 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12499 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Imre Kaloz 2008-09-02 11:28:57 +00:00
parent 55cb889f6d
commit 9496fefd91
1 changed files with 13 additions and 3 deletions
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16
target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
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@ -292,6 +292,7 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
* after calling pcibios_enable_device(). * after calling pcibios_enable_device().
*/ */
if (sb_coreid(sbh) == SB_USB) { if (sb_coreid(sbh) == SB_USB) {
printk(KERN_INFO "SB USB 1.1 init\n");
sb_core_disable(sbh, sb_coreflags(sbh, 0, 0)); sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
sb_core_reset(sbh, 1 << 29, 0); sb_core_reset(sbh, 1 << 29, 0);
} }
@ -306,13 +307,22 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
* phy components out of reset. * phy components out of reset.
*/ */
else if (sb_coreid(sbh) == SB_USB20H) { else if (sb_coreid(sbh) == SB_USB20H) {
uint corerev = sb_corerev(sbh);
printk(KERN_INFO "SB USB20H init\n");
printk(KERN_INFO "SB COREREV: %d\n", corerev);
if (!sb_iscoreup(sbh)) { if (!sb_iscoreup(sbh)) {
printk(KERN_INFO "SB USB20H resetting\n");
sb_core_reset(sbh, 0, 0); sb_core_reset(sbh, 0, 0);
writel(0x7FF, (ulong)regs + 0x200); writel(0x7FF, (ulong)regs + 0x200);
udelay(1); udelay(1);
} }
/* PRxxxx: War for 5354 failures. */ /* PRxxxx: War for 5354 failures. */
if (sb_corerev(sbh) == 1) { if (corerev == 1 || corerev == 2) {
uint32 tmp; uint32 tmp;
/* Change Flush control reg */ /* Change Flush control reg */
@ -320,14 +330,14 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
tmp &= ~8; tmp &= ~8;
writel(tmp, (uintptr)regs + 0x400); writel(tmp, (uintptr)regs + 0x400);
tmp = readl((uintptr)regs + 0x400); tmp = readl((uintptr)regs + 0x400);
printk("USB20H fcr: 0x%x\n", tmp); printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
/* Change Shim control reg */ /* Change Shim control reg */
tmp = readl((uintptr)regs + 0x304); tmp = readl((uintptr)regs + 0x304);
tmp &= ~0x100; tmp &= ~0x100;
writel(tmp, (uintptr)regs + 0x304); writel(tmp, (uintptr)regs + 0x304);
tmp = readl((uintptr)regs + 0x304); tmp = readl((uintptr)regs + 0x304);
printk("USB20H shim cr: 0x%x\n", tmp); printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
} }
} else } else