ar71xx: ag71xx: fix ARP frame reception on AR934x switch ports
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30926 3c298f89-4303-0410-b956-a3cf2f4a3e73master
parent
90579991ee
commit
8e0414c16a
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@ -207,6 +207,17 @@
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#define AR934X_REG_OPER_MODE1 0x08
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#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
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#define AR934X_REG_FLOOD_MASK 0x2c
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#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
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#define AR934X_REG_QM_CTRL 0x3c
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#define AR934X_QM_CTRL_ARP_EN BIT(15)
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#define AR934X_REG_AT_CTRL 0x5c
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#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
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#define AR934X_AT_CTRL_AGE_EN BIT(17)
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#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
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#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
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#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
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@ -556,6 +567,19 @@ static void ar7240sw_setup(struct ar7240sw *as)
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/* Setup TAG priority mapping */
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ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
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if (sw_is_ar934x(as)) {
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/* Enable aging, MAC replacing */
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ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
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0x2b /* 5 min age time */ |
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AR934X_AT_CTRL_AGE_EN |
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AR934X_AT_CTRL_LEARN_CHANGE);
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/* Enable ARP frame acknowledge */
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ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
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AR934X_QM_CTRL_ARP_EN);
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/* Enable Broadcast frames transmitted to the CPU */
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ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
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AR934X_FLOOD_MASK_BC_DP(0));
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} else {
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/* Enable ARP frame acknowledge, aging, MAC replacing */
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ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
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AR7240_AT_CTRL_RESERVED |
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@ -563,10 +587,10 @@ static void ar7240sw_setup(struct ar7240sw *as)
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AR7240_AT_CTRL_AGE_EN |
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AR7240_AT_CTRL_ARP_EN |
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AR7240_AT_CTRL_LEARN_CHANGE);
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/* Enable Broadcast frames transmitted to the CPU */
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ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
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AR7240_FLOOD_MASK_BROAD_TO_CPU);
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}
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/* setup MTU */
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ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
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