ramips: add gpio pin 72 in mt7620 chips to dtsi files
describes register set to control last gpio pin on mt7620 platfrom Signed-off-by: Pavel Löbl <lobl.pavel@gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39162 3c298f89-4303-0410-b956-a3cf2f4a3e73master
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18e825e907
commit
81aaef64b0
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@ -150,6 +150,25 @@
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status = "disabled";
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};
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gpio3: gpio@688 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x688 0x24>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <72>;
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ralink,num-gpios = <1>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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i2c@900 {
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compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
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reg = <0x900 0x100>;
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@ -135,6 +135,25 @@
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status = "disabled";
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};
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gpio3: gpio@688 {
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compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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reg = <0x688 0x24>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <72>;
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ralink,num-gpios = <1>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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spi@b00 {
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compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
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reg = <0xb00 0x100>;
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