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[ar71xx] add AR7240 specific fixes for the ag71xx driver 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16737 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Gabor Juhos 2009-07-07 18:06:02 +00:00
parent 23dcbe7aec
commit 80f0f758b2
5 changed files with 57 additions and 1 deletions
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39
target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
View File

@ -289,6 +289,16 @@ static void ar71xx_set_pll_ge1(int speed)
val, AR71XX_ETH1_PLL_SHIFT);
}
static void ar724x_set_pll_ge0(int speed)
{
/* TODO */
}
static void ar724x_set_pll_ge1(int speed)
{
/* TODO */
}
static void ar91xx_set_pll_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
@ -315,6 +325,16 @@ static void ar71xx_ddr_flush_ge1(void)
ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
}
static void ar724x_ddr_flush_ge0(void)
{
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
}
static void ar724x_ddr_flush_ge1(void)
{
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
}
static void ar91xx_ddr_flush_ge0(void)
{
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
@ -405,6 +425,10 @@ static struct platform_device ar71xx_eth1_device = {
#define AR71XX_PLL_VAL_100 0x00001099
#define AR71XX_PLL_VAL_10 0x00991099
#define AR724X_PLL_VAL_1000 0x00110000
#define AR724X_PLL_VAL_100 0x00001099
#define AR724X_PLL_VAL_10 0x00991099
#define AR91XX_PLL_VAL_1000 0x1a000000
#define AR91XX_PLL_VAL_100 0x13000a44
#define AR91XX_PLL_VAL_10 0x00441099
@ -433,6 +457,13 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id)
pll_100 = AR71XX_PLL_VAL_100;
pll_1000 = AR71XX_PLL_VAL_1000;
break;
case AR71XX_SOC_AR7240:
pll_10 = AR724X_PLL_VAL_10;
pll_100 = AR724X_PLL_VAL_100;
pll_1000 = AR724X_PLL_VAL_1000;
break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
pll_10 = AR91XX_PLL_VAL_10;
@ -522,6 +553,14 @@ void __init ar71xx_add_device_eth(unsigned int id)
pdata->has_gbit = 1;
break;
case AR71XX_SOC_AR7240:
pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
: ar724x_ddr_flush_ge0;
pdata->set_pll = id ? ar724x_set_pll_ge1
: ar724x_set_pll_ge0;
pdata->is_ar724x = 1;
break;
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;

3
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
View File

@ -292,6 +292,9 @@ void ar71xx_gpio_function_disable(u32 mask);
#define AR71XX_DDR_REG_FLUSH_USB 0xa4
#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
#define AR724X_DDR_REG_FLUSH_GE0 0x7c
#define AR724X_DDR_REG_FLUSH_GE1 0x80
#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
#define AR91XX_DDR_REG_FLUSH_GE1 0x80
#define AR91XX_DDR_REG_FLUSH_USB 0x84

1
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h
View File

@ -28,6 +28,7 @@ struct ag71xx_platform_data {
u8 has_gbit:1;
u8 is_ar91xx:1;
u8 is_ar724x:1;
u8 has_ar8216:1;
void (* ddr_flush)(void);

10
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
View File

@ -399,12 +399,22 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
if (pdata->is_ar724x)
return;
__raw_writel(value, ag->mii_ctrl);
__raw_readl(ag->mii_ctrl);
}
static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
if (pdata->is_ar724x)
return 0xffffffff;
return __raw_readl(ag->mii_ctrl);
}

5
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
View File

@ -74,7 +74,10 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
pdata->is_ar91xx ? 0x780fff : 0x008001ff);
pdata->set_pll(ag->speed);
if (pdata->set_pll)
pdata->set_pll(ag->speed);
ag71xx_mii_ctrl_set_speed(ag, mii_speed);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);