ar71xx: don't hardwire cpu_has_dsp{,2} to zero
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37845 3c298f89-4303-0410-b956-a3cf2f4a3e73master
parent
5cdb5dbf49
commit
76c34d5180
|
@ -0,0 +1,31 @@
|
|||
From c9da75bfa6cd7a47f5b2a1d183d34c165a06dd1a Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Thu, 22 Aug 2013 11:15:18 +0200
|
||||
Subject: [PATCH] MIPS: ath79: don't hardwire cpu_has_dsp{2} to 0
|
||||
|
||||
The ath79 code supports various SoCs which are using either a 24Kc
|
||||
or a 74Kc core. The 74Kc core has DSP support, so don't hardwire
|
||||
the values to zero.
|
||||
|
||||
Commit 00dc5ce2a653a332190aa29b2e1f3bceaa7d5b8d (MIPS: ath79: don't
|
||||
hardcode the unavailability of the DSP ASE) has fixed this already,
|
||||
but that change got reverted by 475032564ed96c94c085e3e7a90e07d150a7cec9
|
||||
(MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.)
|
||||
|
||||
Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
|
||||
@@ -42,8 +42,6 @@
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
-#define cpu_has_dsp 0
|
||||
-#define cpu_has_dsp2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
|
||||
#define cpu_has_64bits 0
|
|
@ -8,15 +8,15 @@
|
|||
|
||||
#define cpu_has_mips32r1 1
|
||||
#define cpu_has_mips32r2 1
|
||||
@@ -45,6 +46,7 @@
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_dsp2 0
|
||||
@@ -43,6 +44,7 @@
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#define cpu_has_mipsmt 0
|
||||
+#define cpu_has_userlocal 0
|
||||
|
||||
#define cpu_has_64bits 0
|
||||
#define cpu_has_64bit_zero_reg 0
|
||||
@@ -53,5 +55,9 @@
|
||||
@@ -51,5 +53,9 @@
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 32
|
||||
|
|
Loading…
Reference in New Issue