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[cns3xxx]: refresh patches 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27078 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Imre Kaloz 2011-06-01 07:24:41 +00:00
parent a16a93621c
commit 6b89f2292c
2 changed files with 3 additions and 3 deletions
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2
target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/mach-cns3xxx/pcie.c --- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -378,8 +378,6 @@ static int __init cns3xxx_pcie_init(void @@ -375,8 +375,6 @@ static int __init cns3xxx_pcie_init(void
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
iotable_init(cns3xxx_pcie[i].cfg_bases, iotable_init(cns3xxx_pcie[i].cfg_bases,
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));

4
target/linux/cns3xxx/patches/100-laguna_support.patch
View File

@ -874,8 +874,8 @@
+ +
iotable_init(cns3xxx_pcie[i].cfg_bases, iotable_init(cns3xxx_pcie[i].cfg_bases,
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
@@ -386,4 +389,3 @@ static int __init cns3xxx_pcie_init(void @@ -384,4 +387,3 @@ static int __init cns3xxx_pcie_init(void
return 0; return 0;
} }