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sync ath9k with latest git code 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12038 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Imre Kaloz 2008-07-31 09:51:31 +00:00
parent 40997366e6
commit 5e1bdad3a8
15 changed files with 1971 additions and 2637 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
package/ath9k/Makefile
View File

@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=ath9k
PKG_VERSION:=20080722
PKG_VERSION:=20080731
PKG_RELEASE:=1
include $(INCLUDE_DIR)/package.mk

213
package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
View File

@ -32,19 +32,19 @@
#define AR_SUBVENDOR_ID_NOG 0x0e11
#define AR_SUBVENDOR_ID_NEW_A 0x7065
#define HAL_TXERR_XRETRY 0x01
#define HAL_TXERR_FILT 0x02
#define HAL_TXERR_FIFO 0x04
#define HAL_TXERR_XTXOP 0x08
#define HAL_TXERR_TIMER_EXPIRED 0x10
#define ATH9K_TXERR_XRETRY 0x01
#define ATH9K_TXERR_FILT 0x02
#define ATH9K_TXERR_FIFO 0x04
#define ATH9K_TXERR_XTXOP 0x08
#define ATH9K_TXERR_TIMER_EXPIRED 0x10
#define HAL_TX_BA 0x01
#define HAL_TX_PWRMGMT 0x02
#define HAL_TX_DESC_CFG_ERR 0x04
#define HAL_TX_DATA_UNDERRUN 0x08
#define HAL_TX_DELIM_UNDERRUN 0x10
#define HAL_TX_SW_ABORTED 0x40
#define HAL_TX_SW_FILTERED 0x80
#define ATH9K_TX_BA 0x01
#define ATH9K_TX_PWRMGMT 0x02
#define ATH9K_TX_DESC_CFG_ERR 0x04
#define ATH9K_TX_DATA_UNDERRUN 0x08
#define ATH9K_TX_DELIM_UNDERRUN 0x10
#define ATH9K_TX_SW_ABORTED 0x40
#define ATH9K_TX_SW_FILTERED 0x80
#define NBBY 8
#ifndef howmany
@ -102,24 +102,19 @@ struct ath_rx_status {
u_int32_t evm2;
};
#define HAL_RXERR_CRC 0x01
#define HAL_RXERR_PHY 0x02
#define HAL_RXERR_FIFO 0x04
#define HAL_RXERR_DECRYPT 0x08
#define HAL_RXERR_MIC 0x10
#define ATH9K_RXERR_CRC 0x01
#define ATH9K_RXERR_PHY 0x02
#define ATH9K_RXERR_FIFO 0x04
#define ATH9K_RXERR_DECRYPT 0x08
#define ATH9K_RXERR_MIC 0x10
#define HAL_RX_MORE 0x01
#define HAL_RX_MORE_AGGR 0x02
#define HAL_RX_GI 0x04
#define HAL_RX_2040 0x08
#define HAL_RX_DELIM_CRC_PRE 0x10
#define HAL_RX_DELIM_CRC_POST 0x20
#define HAL_RX_DECRYPT_BUSY 0x40
enum hal_bool {
AH_FALSE = 0,
AH_TRUE = 1,
};
#define ATH9K_RX_MORE 0x01
#define ATH9K_RX_MORE_AGGR 0x02
#define ATH9K_RX_GI 0x04
#define ATH9K_RX_2040 0x08
#define ATH9K_RX_DELIM_CRC_PRE 0x10
#define ATH9K_RX_DELIM_CRC_POST 0x20
#define ATH9K_RX_DECRYPT_BUSY 0x40
#define HAL_RXKEYIX_INVALID ((u_int8_t)-1)
#define HAL_TXKEYIX_INVALID ((u_int)-1)
@ -243,7 +238,6 @@ struct hal_ops_config {
u_int16_t ath_hal_antennaSwitchSwap;
int ath_hal_serializeRegMode;
int ath_hal_intrMitigation;
int ath_hal_debug;
#define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2
@ -482,11 +476,11 @@ struct hal_channel_internal {
int8_t maxRegTxPower;
int8_t maxTxPower;
int8_t minTxPower;
enum hal_bool bssSendHere;
bool bssSendHere;
u_int8_t gainI;
enum hal_bool iqCalValid;
bool iqCalValid;
int32_t CalValid;
enum hal_bool oneTimeCalsDone;
bool oneTimeCalsDone;
int8_t iCoff;
int8_t qCoff;
int16_t rawNoiseFloor;
@ -623,49 +617,20 @@ struct hal_country_entry {
u_int8_t iso[3];
};
#define HAL_DBG_RESET 0x00000001
#define HAL_DBG_PHY_IO 0x00000002
#define HAL_DBG_REG_IO 0x00000004
#define HAL_DBG_RF_PARAM 0x00000008
#define HAL_DBG_QUEUE 0x00000010
#define HAL_DBG_EEPROM_DUMP 0x00000020
#define HAL_DBG_EEPROM 0x00000040
#define HAL_DBG_NF_CAL 0x00000080
#define HAL_DBG_CALIBRATE 0x00000100
#define HAL_DBG_CHANNEL 0x00000200
#define HAL_DBG_INTERRUPT 0x00000400
#define HAL_DBG_DFS 0x00000800
#define HAL_DBG_DMA 0x00001000
#define HAL_DBG_REGULATORY 0x00002000
#define HAL_DBG_TX 0x00004000
#define HAL_DBG_TXDESC 0x00008000
#define HAL_DBG_RX 0x00010000
#define HAL_DBG_RXDESC 0x00020000
#define HAL_DBG_ANI 0x00040000
#define HAL_DBG_BEACON 0x00080000
#define HAL_DBG_KEYCACHE 0x00100000
#define HAL_DBG_POWER_MGMT 0x00200000
#define HAL_DBG_MALLOC 0x00400000
#define HAL_DBG_POWER_OVERRIDE 0x01000000
#define HAL_DBG_SPUR_MITIGATE 0x02000000
#define HAL_DBG_UNMASKABLE 0xFFFFFFFF
#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
#define SM(_v, _f) (((_v) << _f##_S) & _f)
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define OS_REG_RMW(_a, _r, _set, _clr) \
#define REG_RMW(_a, _r, _set, _clr) \
REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
#define REG_RMW_FIELD(_a, _r, _f, _v) \
REG_WRITE(_a, _r, \
(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
#define OS_REG_SET_BIT(_a, _r, _f) \
#define REG_SET_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
#define OS_REG_CLR_BIT(_a, _r, _f) \
#define REG_CLR_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
#define OS_REG_ath9k_regd_is_bit_set(_a, _r, _f) \
((REG_READ(_a, _r) & _f) != 0)
#define HAL_COMP_BUF_MAX_SIZE 9216
#define HAL_COMP_BUF_ALIGN_SIZE 512
@ -913,7 +878,7 @@ struct ath_hal {
u_int32_t ah_magic;
u_int16_t ah_devid;
u_int16_t ah_subvendorid;
void *ah_sc;
struct ath_softc *ah_sc;
void __iomem *ah_sh;
u_int16_t ah_countryCode;
u_int32_t ah_macVersion;
@ -936,25 +901,19 @@ struct ath_hal {
u_int16_t ah_currentRD2G;
char ah_iso[4];
enum start_adhoc_option ah_adHocMode;
enum hal_bool ah_commonMode;
bool ah_commonMode;
struct hal_channel_internal ah_channels[150];
u_int ah_nchan;
struct hal_channel_internal *ah_curchan;
u_int16_t ah_rfsilent;
enum hal_bool ah_rfkillEnabled;
enum hal_bool ah_isPciExpress;
bool ah_rfkillEnabled;
bool ah_isPciExpress;
u_int16_t ah_txTrigLevel;
#ifndef ATH_NF_PER_CHAN
struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
#endif
};
#define HDPRINTF(_ah, _m, _fmt, ...) do { \
if (((_ah) == NULL && _m == HAL_DBG_UNMASKABLE) || \
(((struct ath_hal *)(_ah))->ah_config.ath_hal_debug & _m)) \
printk(KERN_DEBUG _fmt , ##__VA_ARGS__); \
} while (0)
enum wireless_mode {
WIRELESS_MODE_11a = 0,
WIRELESS_MODE_11b = 2,
@ -999,38 +958,39 @@ enum hal_status ath_hal_getcapability(struct ath_hal *ah,
const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
u_int mode);
void ath9k_hw_detach(struct ath_hal *ah);
struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
struct ath_hal *ath9k_hw_attach(u_int16_t devid,
struct ath_softc *sc,
void __iomem *mem,
enum hal_status *error);
enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
bool ath9k_regd_init_channels(struct ath_hal *ah,
struct hal_channel *chans,
u_int maxchans, u_int *nchans,
u_int8_t *regclassids,
u_int maxregids, u_int *nregids,
u_int16_t cc, u_int32_t modeSelect,
enum hal_bool enableOutdoor,
enum hal_bool
enableExtendedChannels);
bool enableOutdoor,
bool enableExtendedChannels);
u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
enum hal_int ints);
enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
struct hal_channel *chan,
enum hal_ht_macmode macmode,
u_int8_t txchainmask, u_int8_t rxchainmask,
enum hal_ht_extprotspacing extprotspacing,
enum hal_bool bChannelChange,
bool bChannelChange,
enum hal_status *status);
enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah);
bool ath9k_hw_phy_disable(struct ath_hal *ah);
void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
enum hal_bool *isCalDone);
bool *isCalDone);
void ath9k_hw_ani_monitor(struct ath_hal *ah,
const struct hal_node_stats *stats,
struct hal_channel *chan);
enum hal_bool ath9k_hw_calibrate(struct ath_hal *ah,
bool ath9k_hw_calibrate(struct ath_hal *ah,
struct hal_channel *chan,
u_int8_t rxchainmask,
enum hal_bool longcal,
enum hal_bool *isCalDone);
bool longcal,
bool *isCalDone);
int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
struct hal_channel *chan);
void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
@ -1038,39 +998,34 @@ void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
u_int16_t assocId);
enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
void ath9k_hw_reset_tsf(struct ath_hal *ah);
enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
enum hal_bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
const u_int8_t *mac);
enum hal_bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
u_int16_t entry,
const struct hal_keyval *k,
const u_int8_t *mac,
int xorKey);
enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
u_int32_t setting);
void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah);
enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
enum hal_bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
enum hal_bool bIncTrigLevel);
bool ath9k_hw_intrpend(struct ath_hal *ah);
bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
bool bIncTrigLevel);
void ath9k_hw_procmibevent(struct ath_hal *ah,
const struct hal_node_stats *stats);
enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
enum hal_bool ath9k_hw_setupxtxdesc(struct ath_hal *ah,
struct ath_desc *ds,
u_int txRate1, u_int txTries1,
u_int txRate2, u_int txTries2,
u_int txRate3, u_int txTries3);
enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,
bool ath9k_hw_phycounters(struct ath_hal *ah);
bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
bool ath9k_hw_getcapability(struct ath_hal *ah,
enum hal_capability_type type,
u_int32_t capability,
u_int32_t *result);
enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
bool ath9k_hw_setcapability(struct ath_hal *ah,
enum hal_capability_type type,
u_int32_t capability,
u_int32_t setting,
@ -1078,15 +1033,15 @@ enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
enum hal_bool ath9k_hw_setbssidmask(struct ath_hal *ah,
bool ath9k_hw_setbssidmask(struct ath_hal *ah,
const u_int8_t *mask);
enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
bool ath9k_hw_setpower(struct ath_hal *ah,
enum hal_power_mode mode);
enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
enum hal_ant_setting settings,
struct hal_channel *chan,
u_int8_t *tx_chainmask,
@ -1095,13 +1050,13 @@ enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
u_int32_t cfg);
enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
u_int32_t txdp);
enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
const struct hal_rate_table *rates,
u_int32_t frameLen, u_int16_t rateix,
enum hal_bool shortPreamble);
bool shortPreamble);
void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
struct ath_desc *lastds,
u_int durUpdateEn, u_int rtsctsRate,
@ -1113,14 +1068,14 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
u_int burstDuration);
void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
struct hal_channel *chan);
u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
enum hal_bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
struct hal_txq_info *qInfo);
enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
const struct hal_txq_info *qInfo);
struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
const struct hal_channel *c);
@ -1128,9 +1083,9 @@ void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen, enum hal_pkt_type type,
u_int txPower, u_int keyIx,
enum hal_key_type keyType, u_int flags);
enum hal_bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, enum hal_bool firstSeg,
enum hal_bool lastSeg,
bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, bool firstSeg,
bool lastSeg,
const struct ath_desc *ds0);
u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
u_int32_t *rxc_pcnt,
@ -1141,18 +1096,18 @@ void ath9k_hw_beaconinit(struct ath_hal *ah,
u_int32_t next_beacon, u_int32_t beacon_period);
void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
const struct hal_beacon_state *bs);
enum hal_bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
u_int32_t size, u_int flags);
void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
void ath9k_hw_rxena(struct ath_hal *ah);
void ath9k_hw_setopmode(struct ath_hal *ah);
enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
u_int32_t filter1);
u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
void ath9k_hw_startpcureceive(struct ath_hal *ah);
void ath9k_hw_stoppcurecv(struct ath_hal *ah);
enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
struct ath_desc *ds, u_int32_t pa,
struct ath_desc *nds, u_int64_t tsf);
@ -1164,26 +1119,26 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
u_int aggrLen);
void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
struct ath_desc *ds, u_int vmf);
enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
const struct hal_txq_info *qInfo);
u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
enum hal_bool ath9k_hw_disable(struct ath_hal *ah);
bool ath9k_hw_disable(struct ath_hal *ah);
void ath9k_hw_rfdetach(struct ath_hal *ah);
void ath9k_hw_get_channel_centers(struct ath_hal *ah,
struct hal_channel_internal *chan,
struct chan_centers *centers);
enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
bool ath9k_get_channel_edges(struct ath_hal *ah,
u_int16_t flags, u_int16_t *low,
u_int16_t *high);
enum hal_bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
struct hal_channel *chans,
u_int32_t nchans);
#endif

166
package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
View File

@ -45,7 +45,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
}
if (!ath9k_hw_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to update h/w beacon queue parameters\n",
__func__);
return 0;
@ -76,7 +76,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
int ctsduration = 0;
struct hal_11n_rate_series series[4];
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
__func__, skb, skb->len);
/* setup descriptors */
@ -84,7 +84,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
flags = HAL_TXDESC_NOACK;
if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol) {
if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
ds->ds_link = bf->bf_daddr; /* self-linked */
flags |= HAL_TXDESC_VEOL;
/* Let hardware handle antenna switching. */
@ -97,11 +97,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
* SWBA's
* XXX assumes two antenna
*/
if (sc->sc_stagbeacons)
antenna = ((sc->ast_be_xmit /
sc->sc_nbcnvaps) & 1 ? 2 : 1);
else
antenna = (sc->ast_be_xmit & 1 ? 2 : 1);
antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
}
ds->ds_data = bf->bf_buf_addr;
@ -128,8 +124,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
/* NB: beacon's BufLen must be a multiple of 4 bytes */
ath9k_hw_filltxdesc(ah, ds
, roundup(skb->len, 4) /* buffer length */
, AH_TRUE /* first segment */
, AH_TRUE /* last segment */
, true /* first segment */
, true /* last segment */
, ds /* first descriptor */
);
@ -219,7 +215,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
ASSERT(avp);
if (avp->av_bcbuf == NULL) {
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
__func__, avp, avp->av_bcbuf);
return NULL;
}
@ -272,9 +268,9 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
* the lock again which is a common function and that
* acquires txq lock inside.
*/
if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
ath_tx_draintxq(sc, cabq, AH_FALSE);
DPRINTF(sc, ATH_DEBUG_BEACON,
if (sc->sc_nvaps > 1) {
ath_tx_draintxq(sc, cabq, false);
DPRINTF(sc, ATH_DBG_BEACON,
"%s: flush previous cabq traffic\n", __func__);
}
}
@ -309,7 +305,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
ASSERT(avp);
if (avp->av_bcbuf == NULL) {
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
__func__, avp, avp != NULL ? avp->av_bcbuf : NULL);
return;
}
@ -322,7 +318,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
/* NB: caller is known to have already stopped tx dma */
ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
ath9k_hw_txstart(ah, sc->sc_bhalq);
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
}
@ -377,7 +373,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
struct ath_buf, list);
list_del(&avp->av_bcbuf->list);
if (sc->sc_opmode == HAL_M_HOSTAP || !sc->sc_hasveol) {
if (sc->sc_opmode == HAL_M_HOSTAP ||
!sc->sc_ah->ah_caps.halVEOLSupport) {
int slot;
/*
* Assign the vap to a beacon xmit slot. As
@ -399,8 +396,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
avp->av_bslot = slot;
/* NB: keep looking for a double slot */
}
KASSERT(sc->sc_bslot[avp->av_bslot] == ATH_IF_ID_ANY,
("beacon slot %u not empty?", avp->av_bslot));
BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY);
sc->sc_bslot[avp->av_bslot] = if_id;
sc->sc_nbcnvaps++;
}
@ -409,14 +405,10 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
/* release the previous beacon frame , if it already exists. */
bf = avp->av_bcbuf;
if (bf->bf_mpdu != NULL) {
struct ath_xmit_status tx_status;
skb = (struct sk_buff *)bf->bf_mpdu;
ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
get_dma_mem_context(bf, bf_dmacontext));
tx_status.flags = 0;
tx_status.retries = 0;
ath_tx_complete(sc, skb, &tx_status, NULL);
dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL;
}
@ -424,10 +416,12 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
* NB: the beacon data buffer must be 32-bit aligned;
* we assume the wbuf routines will return us something
* with this alignment (perhaps should assert).
* FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and
* avp->av_btxctl.shortPreamble
*/
skb = ath_get_beacon(sc, if_id, &avp->av_boff, &avp->av_btxctl);
skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);
if (skb == NULL) {
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get skb\n",
DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n",
__func__);
return -ENOMEM;
}
@ -438,8 +432,9 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
* of the beacon frame leaves the tstamp field immediately
* following the header.
*/
if (sc->sc_stagbeacons && avp->av_bslot > 0) {
if (avp->av_bslot > 0) {
u_int64_t tsfadjust;
__le64 val;
int intval;
/* FIXME: Use default value for now: Sujith */
@ -458,15 +453,15 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
* others get a timestamp aligned to the next interval.
*/
tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF;
tsfadjust = cpu_to_le64(tsfadjust<<10); /* TU->TSF */
val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: %s beacons, bslot %d intval %u tsfadjust %llu\n",
__func__, sc->sc_stagbeacons ? "stagger" : "burst",
__func__, "stagger",
avp->av_bslot, intval, (unsigned long long)tsfadjust);
wh = (struct ieee80211_hdr *)skb->data;
memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
memcpy(&wh[1], &val, sizeof(val));
}
bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,
@ -496,13 +491,9 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
bf = avp->av_bcbuf;
if (bf->bf_mpdu != NULL) {
struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
struct ath_xmit_status tx_status;
ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
get_dma_mem_context(bf, bf_dmacontext));
tx_status.flags = 0;
tx_status.retries = 0;
ath_tx_complete(sc, skb, &tx_status, NULL);
dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL;
}
list_add_tail(&bf->list, &sc->sc_bbuf);
@ -527,13 +518,9 @@ void ath_beacon_free(struct ath_softc *sc)
list_for_each_entry(bf, &sc->sc_bbuf, list) {
if (bf->bf_mpdu != NULL) {
struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
struct ath_xmit_status tx_status;
ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
get_dma_mem_context(bf, bf_dmacontext));
tx_status.flags = 0;
tx_status.retries = 0;
ath_tx_complete(sc, skb, &tx_status, NULL);
dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL;
}
}
@ -562,6 +549,9 @@ void ath9k_beacon_tasklet(unsigned long data)
u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
u_int32_t show_cycles = 0;
u_int32_t bc = 0; /* beacon count */
u_int64_t tsf;
u_int32_t tsftu;
u_int16_t intval;
if (sc->sc_noreset) {
show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
@ -586,7 +576,7 @@ void ath9k_beacon_tasklet(unsigned long data)
*/
if (sc->sc_bmisscount < BSTUCK_THRESH) {
if (sc->sc_noreset) {
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: missed %u consecutive beacons\n",
__func__, sc->sc_bmisscount);
if (show_cycles) {
@ -596,19 +586,19 @@ void ath9k_beacon_tasklet(unsigned long data)
* stickiness.
*/
DPRINTF(sc,
ATH_DEBUG_BEACON,
ATH_DBG_BEACON,
"%s: busy times: rx_clear=%d, "
"rx_frame=%d, tx_frame=%d\n",
__func__, rx_clear, rx_frame,
tx_frame);
} else {
DPRINTF(sc,
ATH_DEBUG_BEACON,
ATH_DBG_BEACON,
"%s: unable to obtain "
"busy times\n", __func__);
}
} else {
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: missed %u consecutive beacons\n",
__func__, sc->sc_bmisscount);
}
@ -616,13 +606,13 @@ void ath9k_beacon_tasklet(unsigned long data)
if (sc->sc_noreset) {
if (sc->sc_bmisscount == BSTUCK_THRESH) {
DPRINTF(sc,
ATH_DEBUG_BEACON,
ATH_DBG_BEACON,
"%s: beacon is officially "
"stuck\n", __func__);
ath9k_hw_dmaRegDump(ah);
}
} else {
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: beacon is officially stuck\n",
__func__);
ath_bstuck_process(sc);
@ -634,11 +624,11 @@ void ath9k_beacon_tasklet(unsigned long data)
if (sc->sc_bmisscount != 0) {
if (sc->sc_noreset) {
DPRINTF(sc,
ATH_DEBUG_BEACON,
ATH_DBG_BEACON,
"%s: resume beacon xmit after %u misses\n",
__func__, sc->sc_bmisscount);
} else {
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: resume beacon xmit after %u misses\n",
__func__, sc->sc_bmisscount);
}
@ -646,17 +636,10 @@ void ath9k_beacon_tasklet(unsigned long data)
}
/*
* Generate beacon frames. If we are sending frames
* staggered then calculate the slot for this frame based
* Generate beacon frames. we are sending frames
* staggered so calculate the slot for this frame based
* on the tsf to safeguard against missing an swba.
* Otherwise we are bursting all frames together and need
* to generate a frame for each vap that is up and running.
*/
if (sc->sc_stagbeacons) {
/* staggered beacons */
u_int64_t tsf;
u_int32_t tsftu;
u_int16_t intval;
/* FIXME: Use default value for now - Sujith */
intval = ATH_DEFAULT_BINTVAL;
@ -665,7 +648,7 @@ void ath9k_beacon_tasklet(unsigned long data)
tsftu = TSF_TO_TU(tsf>>32, tsf);
slot = ((tsftu % intval) * ATH_BCBUF) / intval;
if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
__func__, slot, (unsigned long long) tsf, tsftu,
intval, if_id);
@ -677,25 +660,6 @@ void ath9k_beacon_tasklet(unsigned long data)
bc = 1;
}
}
} else {
/* XXX: Clean this up, move work to a helper */
/* burst'd beacons */
u_int32_t *bflink;
bflink = &bfaddr;
/* XXX rotate/randomize order? */
for (slot = 0; slot < ATH_BCBUF; slot++) {
if_id = sc->sc_bslot[slot];
if (if_id != ATH_IF_ID_ANY) {
bf = ath_beacon_generate(sc, if_id);
if (bf != NULL) {
*bflink = bf->bf_daddr;
bflink = &bf->bf_desc->ds_link;
bc++;
}
}
}
*bflink = 0; /* link of last frame */
}
/*
* Handle slot time change when a non-ERP station joins/leaves
* an 11g network. The 802.11 layer notifies us via callback,
@ -719,27 +683,6 @@ void ath9k_beacon_tasklet(unsigned long data)
} else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
ath_setslottime(sc); /* commit change to hardware */
if ((!sc->sc_stagbeacons || slot == 0) && (!sc->sc_diversity)) {
int otherant;
/*
* Check recent per-antenna transmit statistics and flip
* the default rx antenna if noticeably more frames went out
* on the non-default antenna. Only do this if rx diversity
* is off.
* XXX assumes 2 anntenae
*/
otherant = sc->sc_defant & 1 ? 2 : 1;
if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] +
ATH_ANTENNA_DIFF) {
DPRINTF(sc, ATH_DEBUG_BEACON,
"%s: flip defant to %u, %u > %u\n",
__func__, otherant, sc->sc_ant_tx[otherant],
sc->sc_ant_tx[sc->sc_defant]);
ath_setdefantenna(sc, otherant);
}
sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
}
if (bfaddr != 0) {
/*
* Stop any current dma and put the new frame(s) on the queue.
@ -747,7 +690,7 @@ void ath9k_beacon_tasklet(unsigned long data)
* are still pending on the queue.
*/
if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: beacon queue %u did not stop?\n",
__func__, sc->sc_bhalq);
/* NB: the HAL still stops DMA, so proceed */
@ -771,7 +714,7 @@ void ath9k_beacon_tasklet(unsigned long data)
void ath_bstuck_process(struct ath_softc *sc)
{
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: stuck beacon; resetting (bmiss count %u)\n",
__func__, sc->sc_bmisscount);
ath_internal_reset(sc);
@ -834,11 +777,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
*/
/* NB: the beacon interval is kept internally in TU's */
intval = conf.beacon_interval & HAL_BEACON_PERIOD;
if (sc->sc_stagbeacons)
intval /= ATH_BCBUF; /* for staggered beacons */
if ((sc->sc_nostabeacons) &&
(av_opmode == HAL_M_HOSTAP))
nexttbtt = 0;
} else {
intval = conf.beacon_interval & HAL_BEACON_PERIOD;
}
@ -847,13 +786,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
nexttbtt = intval;
else if (intval) /* NB: can be 0 for monitor mode */
nexttbtt = roundup(nexttbtt, intval);
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt, intval, conf.beacon_interval);
/* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
if ((sc->sc_opmode == HAL_M_STA) ||
((sc->sc_opmode == HAL_M_HOSTAP) &&
(av_opmode == HAL_M_STA) &&
(sc->sc_nostabeacons))) {
if (sc->sc_opmode == HAL_M_STA) {
struct hal_beacon_state bs;
u_int64_t tsf;
u_int32_t tsftu;
@ -936,7 +872,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
if (bs.bs_sleepduration > bs.bs_dtimperiod)
bs.bs_sleepduration = bs.bs_dtimperiod;
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: tsf %llu "
"tsf:tu %u "
"intval %u "
@ -963,12 +899,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
, bs.bs_timoffset
);
if (!(sc->sc_nostabeacons)) {
ath9k_hw_set_interrupts(ah, 0);
ath9k_hw_set_sta_beacon_timers(ah, &bs);
sc->sc_imask |= HAL_INT_BMISS;
ath9k_hw_set_interrupts(ah, sc->sc_imask);
}
} else {
u_int64_t tsf;
u_int32_t tsftu;
@ -990,7 +924,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
} while (nexttbtt < tsftu);
}
#undef FUDGE
DPRINTF(sc, ATH_DEBUG_BEACON,
DPRINTF(sc, ATH_DBG_BEACON,
"%s: IBSS nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt,
intval & ~HAL_BEACON_RESET_TSF,
@ -1004,7 +938,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* deal with things.
*/
intval |= HAL_BEACON_ENA;
if (!sc->sc_hasveol)
if (!ah->ah_caps.halVEOLSupport)
sc->sc_imask |= HAL_INT_SWBA;
ath_beaconq_config(sc);
} else if (sc->sc_opmode == HAL_M_HOSTAP) {
@ -1023,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* When using a self-linked beacon descriptor in
* ibss mode load it once here.
*/
if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol)
if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
ath_beacon_start_adhoc(sc, 0);
}
#undef TSF_TO_TU

523
package/ath9k/src/drivers/net/wireless/ath9k/core.c
View File

@ -19,7 +19,7 @@
#include "core.h"
#include "regd.h"
static int ath_outdoor = AH_FALSE; /* enable outdoor use */
static int ath_outdoor; /* enable outdoor use */
static const u_int8_t ath_bcast_mac[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@ -65,7 +65,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
rt = sc->sc_rates[mode];
KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
BUG_ON(!rt);
for (i = 0; i < rt->rateCount; i++)
sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
@ -152,7 +152,7 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
ATH9K_MODE_SEL_11NG_HT40MINUS);
break;
default:
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid mode %u\n",
DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid mode %u\n",
__func__, mode);
return 0;
}
@ -176,8 +176,8 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
static int ath_getchannels(struct ath_softc *sc,
u_int cc,
enum hal_bool outDoor,
enum hal_bool xchanMode)
bool outDoor,
bool xchanMode)
{
struct ath_hal *ah = sc->sc_ah;
struct hal_channel *chans;
@ -187,7 +187,7 @@ static int ath_getchannels(struct ath_softc *sc,
chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
if (chans == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to allocate channel table\n", __func__);
return -ENOMEM;
}
@ -205,7 +205,7 @@ static int ath_getchannels(struct ath_softc *sc,
xchanMode)) {
u_int32_t rd = ah->ah_currentRD;
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to collect channel list from hal; "
"regdomain likely %u country code %u\n",
__func__, rd, cc);
@ -290,7 +290,7 @@ static int ath_stop(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: invalid %u\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
__func__, sc->sc_invalid);
/*
@ -311,7 +311,7 @@ static int ath_stop(struct ath_softc *sc)
if (!sc->sc_invalid)
ath9k_hw_set_interrupts(ah, 0);
ath_draintxq(sc, AH_FALSE);
ath_draintxq(sc, false);
if (!sc->sc_invalid) {
ath_stoprecv(sc);
ath9k_hw_phy_disable(ah);
@ -342,7 +342,7 @@ void ath_scan_start(struct ath_softc *sc)
/* Restore previous power management state. */
DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
now / 1000, now % 1000, __func__, rfilt);
}
@ -361,11 +361,13 @@ void ath_scan_end(struct ath_softc *sc)
u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
sc->sc_scanning = 0;
/* Request for a full reset due to rx packet filter changes */
sc->sc_full_reset = 1;
rfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(ah, rfilt);
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
}
@ -379,13 +381,13 @@ void ath_scan_end(struct ath_softc *sc)
int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
{
struct ath_hal *ah = sc->sc_ah;
enum hal_bool fastcc = AH_TRUE, stopped;
bool fastcc = true, stopped;
enum hal_ht_macmode ht_macmode;
if (sc->sc_invalid) /* if the device is invalid or removed */
return -EIO;
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
__func__,
ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
@ -410,7 +412,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
* the relevant bits of the h/w.
*/
ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
ath_draintxq(sc, AH_FALSE); /* clear pending tx frames */
ath_draintxq(sc, false); /* clear pending tx frames */
stopped = ath_stoprecv(sc); /* turn off frame recv */
/* XXX: do not flush receive queue here. We don't want
@ -418,7 +420,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
* changing channel. */
if (!stopped || sc->sc_full_reset)
fastcc = AH_FALSE;
fastcc = false;
spin_lock_bh(&sc->sc_resetlock);
if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
@ -426,7 +428,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
sc->sc_rx_chainmask,
sc->sc_ht_extprotspacing,
fastcc, &status)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to reset channel %u (%uMhz) "
"flags 0x%x hal status %u\n", __func__,
ath9k_hw_mhz2ieee(ah, hchan->channel,
@ -443,7 +445,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
/* Re-enable rx framework */
if (ath_startrecv(sc) != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to restart recv logic\n", __func__);
return -EIO;
}
@ -507,10 +509,10 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
* sc_chainmask_auto_sel is used for internal global auto-switching
* enabled/disabled setting
*/
if ((sc->sc_no_tx_3_chains == AH_FALSE) ||
(sc->sc_config.chainmask_sel == AH_FALSE))
if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) {
cm->cur_tx_mask = sc->sc_tx_chainmask;
return cm->cur_tx_mask;
}
if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
return cm->cur_tx_mask;
@ -541,56 +543,31 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
return cm->cur_tx_mask;
}
/*
* Update tx/rx chainmask. For legacy association,
* hard code chainmask to 1x1, for 11n association, use
* the chainmask configuration.
*/
void ath_update_chainmask(struct ath_softc *sc, int is_ht)
{
sc->sc_update_chainmask = 1;
if (is_ht) {
sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask;
} else {
sc->sc_tx_chainmask = 1;
sc->sc_rx_chainmask = 1;
}
DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
__func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
}
/******************/
/* VAP management */
/******************/
/*
* Down VAP instance
*
* This routine will stop the indicated VAP and put it in a "down" state.
* The down state is basically an initialization state that can be brought
* back up by calling the opposite up routine.
* This routine will bring the interface out of power save mode, set the
* LED states, update the rate control processing, stop DMA transfers, and
* set the VAP into the down state.
*/
int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags)
{
struct ath_hal *ah = sc->sc_ah;
struct ath_vap *avp;
avp = sc->sc_vaps[if_id];
if (avp == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
__func__, if_id);
return -EINVAL;
}
#ifdef CONFIG_SLOW_ANT_DIV
if (sc->sc_slowAntDiv)
ath_slow_ant_div_stop(&sc->sc_antdiv);
#endif
/* update ratectrl about the new state */
ath_rate_newstate(sc, avp, 0);
/* Reclaim beacon resources */
if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
ath_beacon_return(sc, avp);
}
if (flags & ATH_IF_HW_OFF) {
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
ath9k_hw_set_interrupts(ah, sc->sc_imask & ~HAL_INT_GLOBAL);
sc->sc_beacons = 0;
}
return 0;
}
/*
* VAP in Listen mode
*
@ -608,13 +585,12 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
avp = sc->sc_vaps[if_id];
if (avp == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
__func__, if_id);
return -EINVAL;
}
#ifdef CONFIG_SLOW_ANT_DIV
if (sc->sc_slowAntDiv)
ath_slow_ant_div_stop(&sc->sc_antdiv);
#endif
@ -630,7 +606,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
} else
sc->sc_curaid = 0;
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
__func__, rfilt, print_mac(mac,
sc->sc_curbssid), sc->sc_curaid);
@ -648,210 +624,25 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
return 0;
}
int ath_vap_join(struct ath_softc *sc, int if_id,
const u_int8_t bssid[ETH_ALEN], u_int flags)
{
struct ath_hal *ah = sc->sc_ah;
struct ath_vap *avp;
u_int32_t rfilt = 0;
DECLARE_MAC_BUF(mac);
avp = sc->sc_vaps[if_id];
if (avp == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
__func__, if_id);
return -EINVAL;
}
/* update ratectrl about the new state */
ath_rate_newstate(sc, avp, 0);
rfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(ah, rfilt);
memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
sc->sc_curaid = 0;
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
DPRINTF(sc, ATH_DEBUG_CONFIG,
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
__func__, rfilt,
print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
/*
* Update tx/rx chainmask. For legacy association,
* hard code chainmask to 1x1, for 11n association, use
* the chainmask configuration.
*/
sc->sc_update_chainmask = 1;
if (flags & ATH_IF_HT) {
sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
} else {
sc->sc_tx_chainmask = 1;
sc->sc_rx_chainmask = 1;
}
/* Enable rx chain mask detection if configured to do so */
sc->sc_rx_chainmask_detect = 0;
/* Set aggregation protection mode parameters */
sc->sc_config.ath_aggr_prot = 0;
/*
* Reset our TSF so that its value is lower than the beacon that we are
* trying to catch. Only then hw will update its TSF register with the
* new beacon. Reset the TSF before setting the BSSID to avoid allowing
* in any frames that would update our TSF only to have us clear it
* immediately thereafter.
*/
ath9k_hw_reset_tsf(ah);
/*
* XXXX
* Disable BMISS interrupt when we're not associated
*/
ath9k_hw_set_interrupts(ah,
sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
/* need to reconfigure the beacons when it moves to RUN */
sc->sc_beacons = 0;
return 0;
}
int ath_vap_up(struct ath_softc *sc,
int if_id,
const u_int8_t bssid[ETH_ALEN],
u_int8_t aid, u_int flags)
{
struct ath_hal *ah = sc->sc_ah;
struct ath_vap *avp;
u_int32_t rfilt = 0;
int i, error = 0;
DECLARE_MAC_BUF(mac);
ASSERT(if_id != ATH_IF_ID_ANY);
avp = sc->sc_vaps[if_id];
if (avp == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
__func__, if_id);
return -EINVAL;
}
/* update ratectrl about the new state */
ath_rate_newstate(sc, avp, 1);
rfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(ah, rfilt);
if (avp->av_opmode == HAL_M_STA || avp->av_opmode == HAL_M_IBSS) {
memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
sc->sc_curaid = aid;
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
}
DPRINTF(sc, ATH_DEBUG_CONFIG,
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
__func__, rfilt,
print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
if ((avp->av_opmode != IEEE80211_IF_TYPE_STA) &&
(flags & ATH_IF_PRIVACY)) {
for (i = 0; i < IEEE80211_WEP_NKID; i++)
if (ath9k_hw_keyisvalid(ah, (u_int16_t) i))
ath9k_hw_keysetmac(ah, (u_int16_t) i, bssid);
}
switch (avp->av_opmode) {
case HAL_M_HOSTAP:
case HAL_M_IBSS:
/*
* Allocate and setup the beacon frame.
*
* Stop any previous beacon DMA. This may be
* necessary, for example, when an ibss merge
* causes reconfiguration; there will be a state
* transition from RUN->RUN that means we may
* be called with beacon transmission active.
*/
ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
error = ath_beacon_alloc(sc, if_id);
if (error != 0)
goto bad;
if (flags & ATH_IF_BEACON_ENABLE)
sc->sc_beacons = 0;
break;
case HAL_M_STA:
/*
* start rx chain mask detection if it is enabled.
* Use the default chainmask as starting point.
*/
if (sc->sc_rx_chainmask_detect) {
if (flags & ATH_IF_HT)
sc->sc_rx_chainmask =
ah->ah_caps.halRxChainMask;
else
sc->sc_rx_chainmask = 1;
sc->sc_rx_chainmask_start = 1;
}
break;
default:
break;
}
/* Moved beacon_config after dfs_wait check
* so that ath_beacon_config won't be called duing dfswait
* period - this will fix the beacon stuck afer DFS
* CAC period issue
* Configure the beacon and sleep timers. */
if (!sc->sc_beacons && !(flags & ATH_IF_BEACON_SYNC)) {
ath_beacon_config(sc, if_id);
sc->sc_beacons = 1;
}
/* Reset rssi stats; maybe not the best place... */
if (flags & ATH_IF_HW_ON) {
sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
}
bad:
return error;
}
int ath_vap_attach(struct ath_softc *sc,
int if_id,
struct ieee80211_vif *if_data,
enum hal_opmode opmode,
enum hal_opmode iv_opmode,
int nostabeacons)
enum hal_opmode opmode)
{
struct ath_vap *avp;
if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Invalid interface id = %u\n", __func__, if_id);
return -EINVAL;
}
switch (opmode) {
case HAL_M_STA:
sc->sc_nostabeacons = nostabeacons;
break;
case HAL_M_IBSS:
case HAL_M_MONITOR:
break;
case HAL_M_HOSTAP:
/* copy nostabeacons - for WDS client */
sc->sc_nostabeacons = nostabeacons;
/* XXX not right, beacon buffer is allocated on RUN trans */
if (list_empty(&sc->sc_bbuf))
return -ENOMEM;
@ -868,24 +659,13 @@ int ath_vap_attach(struct ath_softc *sc,
memzero(avp, sizeof(struct ath_vap));
avp->av_if_data = if_data;
/* Set the VAP opmode */
avp->av_opmode = iv_opmode;
avp->av_opmode = opmode;
avp->av_bslot = -1;
INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
spin_lock_init(&avp->av_mcastq.axq_lock);
if (opmode == HAL_M_HOSTAP || opmode == HAL_M_IBSS) {
if (sc->sc_hastsfadd) {
/*
* Multiple vaps are to transmit beacons and we
* have h/w support for TSF adjusting; enable use
* of staggered beacons.
*/
/* XXX check for beacon interval too small */
sc->sc_stagbeacons = 1;
}
}
if (sc->sc_hastsfadd)
ath9k_hw_set_tsfadjust(sc->sc_ah, sc->sc_stagbeacons);
ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
sc->sc_vaps[if_id] = avp;
sc->sc_nvaps++;
@ -906,7 +686,7 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
avp = sc->sc_vaps[if_id];
if (avp == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
__func__, if_id);
return -EINVAL;
}
@ -919,32 +699,17 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
* XXX can we do this w/o affecting other vap's?
*/
ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
ath_draintxq(sc, AH_FALSE); /* stop xmit side */
ath_draintxq(sc, false); /* stop xmit side */
ath_stoprecv(sc); /* stop recv side */
ath_flushrecv(sc); /* flush recv queue */
/* Reclaim any pending mcast bufs on the vap. */
ath_tx_draintxq(sc, &avp->av_mcastq, AH_FALSE);
if (sc->sc_opmode == HAL_M_HOSTAP && sc->sc_nostabeacons)
sc->sc_nostabeacons = 0;
ath_tx_draintxq(sc, &avp->av_mcastq, false);
kfree(avp);
sc->sc_vaps[if_id] = NULL;
sc->sc_nvaps--;
/* restart H/W in case there are other VAPs */
if (sc->sc_nvaps) {
/* Restart rx+tx machines if device is still running. */
if (ath_startrecv(sc) != 0) /* restart recv */
DPRINTF(sc, ATH_DEBUG_FATAL,
"%s: unable to start recv logic\n", __func__);
if (sc->sc_beacons)
/* restart beacons */
ath_beacon_config(sc, ATH_IF_ID_ANY);
ath9k_hw_set_interrupts(ah, sc->sc_imask);
}
return 0;
}
@ -954,7 +719,7 @@ int ath_vap_config(struct ath_softc *sc,
struct ath_vap *avp;
if (if_id >= ATH_BCBUF) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Invalid interface id = %u\n", __func__, if_id);
return -EINVAL;
}
@ -979,7 +744,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
int error = 0;
enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
/*
* Stop anything previously setup. This is safe
@ -1006,8 +771,8 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
spin_lock_bh(&sc->sc_resetlock);
if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
sc->sc_tx_chainmask, sc->sc_rx_chainmask,
sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
sc->sc_ht_extprotspacing, false, &status)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to reset hardware; hal status %u "
"(freq %u flags 0x%x)\n", __func__, status,
sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
@ -1030,7 +795,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
* here except setup the interrupt mask.
*/
if (ath_startrecv(sc) != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to start recv logic\n", __func__);
error = -EIO;
goto done;
@ -1043,14 +808,14 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
if (ah->ah_caps.halGTTSupport)
sc->sc_imask |= HAL_INT_GTT;
if (sc->sc_hashtsupport)
if (ah->ah_caps.halHTSupport)
sc->sc_imask |= HAL_INT_CST;
/*
* Enable MIB interrupts when there are hardware phy counters.
* Note we only do this (at the moment) for station mode.
*/
if (sc->sc_needmib &&
if (ath9k_hw_phycounters(ah) &&
((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
sc->sc_imask |= HAL_INT_MIB;
/*
@ -1101,7 +866,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
struct ath_hal *ah = sc->sc_ah;
if (ath_startrecv(sc) != 0) /* restart recv */
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to start recv logic\n", __func__);
/*
@ -1143,8 +908,8 @@ int ath_reset(struct ath_softc *sc)
if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
ht_macmode,
sc->sc_tx_chainmask, sc->sc_rx_chainmask,
sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
sc->sc_ht_extprotspacing, false, &status)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to reset hardware; hal status %u\n",
__func__, status);
error = -EIO;
@ -1180,11 +945,12 @@ int ath_suspend(struct ath_softc *sc)
/* Interrupt handler. Most of the actual processing is deferred.
* It's the caller's responsibility to ensure the chip is awake. */
int ath_intr(struct ath_softc *sc)
irqreturn_t ath_isr(int irq, void *dev)
{
struct ath_softc *sc = dev;
struct ath_hal *ah = sc->sc_ah;
enum hal_int status;
int sched = ATH_ISR_NOSCHED;
bool sched = false;
do {
if (sc->sc_invalid) {
@ -1193,10 +959,10 @@ int ath_intr(struct ath_softc *sc)
* touch anything. Note this can happen early
* on if the IRQ is shared.
*/
return ATH_ISR_NOTMINE;
return IRQ_NONE;
}
if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
return ATH_ISR_NOTMINE;
return IRQ_NONE;
}
/*
@ -1215,16 +981,16 @@ int ath_intr(struct ath_softc *sc)
*/
if (!status)
return ATH_ISR_NOTMINE;
return IRQ_NONE;
sc->sc_intrstatus = status;
if (status & HAL_INT_FATAL) {
/* need a chip reset */
sched = ATH_ISR_SCHED;
sched = true;
} else if (status & HAL_INT_RXORN) {
/* need a chip reset */
sched = ATH_ISR_SCHED;
sched = true;
} else {
if (status & HAL_INT_SWBA) {
/* schedule a tasklet for beacon handling */
@ -1236,22 +1002,22 @@ int ath_intr(struct ath_softc *sc)
* RXE bit is written, but it doesn't work
* at least on older hardware revs.
*/
sched = ATH_ISR_SCHED;
sched = true;
}
if (status & HAL_INT_TXURN)
/* bump tx trigger level */
ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
ath9k_hw_updatetxtriglevel(ah, true);
/* XXX: optimize this */
if (status & HAL_INT_RX)
sched = ATH_ISR_SCHED;
sched = true;
if (status & HAL_INT_TX)
sched = ATH_ISR_SCHED;
sched = true;
if (status & HAL_INT_BMISS)
sched = ATH_ISR_SCHED;
sched = true;
/* carrier sense timeout */
if (status & HAL_INT_CST)
sched = ATH_ISR_SCHED;
sched = true;
if (status & HAL_INT_MIB) {
/*
* Disable interrupts until we service the MIB
@ -1268,26 +1034,23 @@ int ath_intr(struct ath_softc *sc)
ath9k_hw_set_interrupts(ah, sc->sc_imask);
}
if (status & HAL_INT_TIM_TIMER) {
if (!sc->sc_hasautosleep) {
if (!ah->ah_caps.halAutoSleepSupport) {
/* Clear RxAbort bit so that we can
* receive frames */
ath9k_hw_setrxabort(ah, 0);
/* Set flag indicating we're waiting
* for a beacon */
sc->sc_waitbeacon = 1;
sched = ATH_ISR_SCHED;
sched = true;
}
}
}
} while (0);
if (sched == ATH_ISR_SCHED)
if (sched) {
/* turn off every interrupt except SWBA */
ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
tasklet_schedule(&sc->intr_tq);
}
return sched;
return IRQ_HANDLED;
}
/* Deferred interrupt processing */
@ -1335,11 +1098,6 @@ static void ath9k_tasklet(unsigned long data)
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
}
void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode)
{
ath9k_hw_set11nmac2040(sc->sc_ah, macmode);
}
int ath_init(u_int16_t devid, struct ath_softc *sc)
{
struct ath_hal *ah = NULL;
@ -1352,7 +1110,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
sc->sc_invalid = 1;
sc->sc_debug = DBG_DEFAULT;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
/* Initialize tasklet */
tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
@ -1371,7 +1129,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
if (ah == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to attach hardware; HAL status %u\n",
__func__, status);
error = -ENXIO;
@ -1382,29 +1140,10 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
/* Get the chipset-specific aggr limit. */
sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
/*
* Check if the MAC has multi-rate retry support.
* We do this by trying to setup a fake extended
* descriptor. MAC's that don't have support will
* return false w/o doing anything. MAC's that do
* support it will return true w/o doing anything.
*
* XXX This is lame. Just query a hal property, Luke!
*/
sc->sc_mrretry = ath9k_hw_setupxtxdesc(ah, NULL, 0, 0, 0, 0, 0, 0);
/*
* Check if the device has hardware counters for PHY
* errors. If so we need to enable the MIB interrupt
* so we can act on stat triggers.
*/
if (ath9k_hw_phycounters(ah))
sc->sc_needmib = 1;
/* Get the hardware key cache size. */
sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
if (sc->sc_keymax > ATH_KEYMAX) {
DPRINTF(sc, ATH_DEBUG_KEYCACHE,
DPRINTF(sc, ATH_DBG_KEYCACHE,
"%s: Warning, using only %u entries in %u key cache\n",
__func__, ATH_KEYMAX, sc->sc_keymax);
sc->sc_keymax = ATH_KEYMAX;
@ -1463,14 +1202,14 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
*/
sc->sc_bhalq = ath_beaconq_setup(ah);
if (sc->sc_bhalq == -1) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup a beacon xmit queue\n", __func__);
error = -EIO;
goto bad2;
}
sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
if (sc->sc_cabq == NULL) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup CAB xmit queue\n", __func__);
error = -EIO;
goto bad2;
@ -1485,7 +1224,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
/* Setup data queues */
/* NB: ensure BK queue is the lowest priority h/w queue */
if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for BK traffic\n",
__func__);
error = -EIO;
@ -1493,30 +1232,27 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
}
if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for BE traffic\n",
__func__);
error = -EIO;
goto bad2;
}
if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for VI traffic\n",
__func__);
error = -EIO;
goto bad2;
}
if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for VO traffic\n",
__func__);
error = -EIO;
goto bad2;
}
if (ah->ah_caps.halHTSupport)
sc->sc_hashtsupport = 1;
sc->sc_rc = ath_rate_attach(ah);
if (sc->sc_rc == NULL) {
error = EIO;
@ -1532,8 +1268,6 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
*/
ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL);
}
sc->sc_hasclrkey = ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
HAL_CIPHER_CLR, NULL);
/*
* Check whether the separate key cache entries
@ -1556,26 +1290,11 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
sc->sc_config.txpowlimit_override = 0;
/* 11n Capabilities */
if (sc->sc_hashtsupport) {
if (ah->ah_caps.halHTSupport) {
sc->sc_txaggr = 1;
sc->sc_rxaggr = 1;
}
/* Check for misc other capabilities. */
sc->sc_hasbmask = ah->ah_caps.halBssIdMaskSupport ? 1 : 0;
sc->sc_hastsfadd =
ath9k_hw_getcapability(ah, HAL_CAP_TSF_ADJUST, 0, NULL);
/*
* If we cannot transmit on three chains, prevent chain mask
* selection logic from switching between 2x2 and 3x3 chain
* masks based on RSSI.
*/
sc->sc_no_tx_3_chains =
(ah->ah_caps.halTxChainMask == ATH_CHAINMASK_SEL_3X3) ?
AH_TRUE : AH_FALSE;
sc->sc_config.chainmask_sel = sc->sc_no_tx_3_chains;
sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
@ -1586,37 +1305,15 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
sc->sc_rxchaindetect_delta5GHz = 30;
sc->sc_rxchaindetect_delta2GHz = 30;
/*
* Query the hal about antenna support
* Enable rx fast diversity if hal has support
*/
if (ath9k_hw_getcapability(ah, HAL_CAP_DIVERSITY, 0, NULL)) {
sc->sc_hasdiversity = 1;
ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
1, AH_TRUE, NULL);
sc->sc_diversity = 1;
} else {
sc->sc_hasdiversity = 0;
sc->sc_diversity = 0;
ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
1, AH_FALSE, NULL);
}
ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
sc->sc_defant = ath9k_hw_getdefantenna(ah);
/*
* Not all chips have the VEOL support we want to
* use with IBSS beacons; check here for it.
*/
sc->sc_hasveol = ah->ah_caps.halVEOLSupport;
ath9k_hw_getmac(ah, sc->sc_myaddr);
if (sc->sc_hasbmask) {
if (ah->ah_caps.halBssIdMaskSupport) {
ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
}
sc->sc_hasautosleep = ah->ah_caps.halAutoSleepSupport;
sc->sc_waitbeacon = 0;
sc->sc_slottime = HAL_SLOT_TIME_9; /* default to short slot time */
/* initialize beacon slots */
@ -1627,11 +1324,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
sc->sc_config.swBeaconProcess = 1;
#ifdef CONFIG_SLOW_ANT_DIV
sc->sc_slowAntDiv = 1;
/* range is 40 - 255, we use something in the middle */
ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
#else
sc->sc_slowAntDiv = 0;
#endif
return 0;
@ -1651,7 +1345,7 @@ void ath_deinit(struct ath_softc *sc)
struct ath_hal *ah = sc->sc_ah;
int i;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s\n", __func__);
DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
ath_stop(sc);
if (!sc->sc_invalid)
@ -1695,9 +1389,6 @@ struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
list_add(&an->list, &sc->node_list);
DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
__func__, an, print_mac(mac, addr));
return an;
}
@ -1721,9 +1412,6 @@ void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
spin_unlock_irqrestore(&sc->node_lock, flags);
DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
__func__, an, print_mac(mac, an->an_addr));
kfree(an);
}
@ -1799,6 +1487,7 @@ void ath_newassoc(struct ath_softc *sc,
/**************/
/* Encryption */
/**************/
void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
{
ath9k_hw_keyreset(sc->sc_ah, keyix);
@ -1811,12 +1500,12 @@ int ath_keyset(struct ath_softc *sc,
struct hal_keyval *hk,
const u_int8_t mac[ETH_ALEN])
{
enum hal_bool status;
bool status;
status = ath9k_hw_set_keycache_entry(sc->sc_ah,
keyix, hk, mac, AH_FALSE);
keyix, hk, mac, false);
return status != AH_FALSE;
return status != false;
}
/***********************/
@ -2020,12 +1709,12 @@ int ath_descdma_setup(struct ath_softc *sc,
struct ath_buf *bf;
int i, bsize, error;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
__func__, name, nbuf, ndesc);
/* ath_desc must be a multiple of DWORDs */
if ((sizeof(struct ath_desc) % 4) != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: ath_desc not DWORD aligned\n",
DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
__func__);
ASSERT((sizeof(struct ath_desc) % 4) == 0);
error = -ENOMEM;
@ -2062,7 +1751,7 @@ int ath_descdma_setup(struct ath_softc *sc,
goto fail;
}
ds = dd->dd_desc;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
__func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
@ -2143,14 +1832,6 @@ void ath_internal_reset(struct ath_softc *sc)
ath_reset_end(sc, 0);
}
void ath_setrxfilter(struct ath_softc *sc)
{
u_int32_t rxfilt;
rxfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(sc->sc_ah, rxfilt);
}
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
{
int qnum;

118
package/ath9k/src/drivers/net/wireless/ath9k/core.h
View File

@ -156,13 +156,6 @@ static inline void list_cut_position(struct list_head *list,
} \
} while (0)
#define KASSERT(exp, msg) do { \
if (unlikely(!(exp))) { \
printk msg; \
BUG(); \
} \
} while (0)
/* XXX: remove */
#define memzero(_buf, _len) memset(_buf, 0, _len)
@ -184,23 +177,29 @@ static inline unsigned long get_timestamp(void)
/*************/
enum ATH_DEBUG {
ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
ATH_DEBUG_RECV = 0x00000002, /* basic recv operation */
ATH_DEBUG_BEACON = 0x00000004, /* beacon handling */
ATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
ATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
ATH_DEBUG_BEACON_PROC = 0x00000020, /* beacon ISR proc */
ATH_DEBUG_RATE = 0x00000040, /* rate control */
ATH_DEBUG_CONFIG = 0x00000080, /* configuration */
ATH_DEBUG_KEYCACHE = 0x00000100, /* key cache management */
ATH_DEBUG_NODE = 0x00000200, /* node management */
ATH_DEBUG_AGGR = 0x00000400, /* Aggregation */
ATH_DEBUG_CWM = 0x00000800, /* Channel Width Management */
ATH_DEBUG_FATAL = 0x00001000, /* fatal errors */
ATH_DEBUG_ANY = 0xffffffff
ATH_DBG_RESET = 0x00000001,
ATH_DBG_PHY_IO = 0x00000002,
ATH_DBG_REG_IO = 0x00000004,
ATH_DBG_QUEUE = 0x00000008,
ATH_DBG_EEPROM = 0x00000010,
ATH_DBG_NF_CAL = 0x00000020,
ATH_DBG_CALIBRATE = 0x00000040,
ATH_DBG_CHANNEL = 0x00000080,
ATH_DBG_INTERRUPT = 0x00000100,
ATH_DBG_REGULATORY = 0x00000200,
ATH_DBG_ANI = 0x00000400,
ATH_DBG_POWER_MGMT = 0x00000800,
ATH_DBG_XMIT = 0x00001000,
ATH_DBG_BEACON = 0x00002000,
ATH_DBG_RATE = 0x00004000,
ATH_DBG_CONFIG = 0x00008000,
ATH_DBG_KEYCACHE = 0x00010000,
ATH_DBG_AGGR = 0x00020000,
ATH_DBG_FATAL = 0x00040000,
ATH_DBG_ANY = 0xffffffff
};
#define DBG_DEFAULT (ATH_DEBUG_FATAL)
#define DBG_DEFAULT (ATH_DBG_FATAL)
#define DPRINTF(sc, _m, _fmt, ...) do { \
if (sc->sc_debug & (_m)) \
@ -214,7 +213,6 @@ enum ATH_DEBUG {
/* Per-instance load-time (note: NOT run-time) configurations
* for Atheros Device */
struct ath_config {
u_int8_t chainmask_sel; /* enable automatic tx chainmask selection */
u_int32_t ath_aggr_prot;
u_int16_t txpowlimit;
u_int16_t txpowlimit_override;
@ -249,6 +247,7 @@ struct ath_chainmask_sel {
};
int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
void ath_update_chainmask(struct ath_softc *sc, int is_ht);
/*************************/
/* Descriptor Management */
@ -452,9 +451,8 @@ struct ath_arx {
struct ath_arx_tid tid[WME_NUM_TID];
};
void ath_setrxfilter(struct ath_softc *sc);
int ath_startrecv(struct ath_softc *sc);
enum hal_bool ath_stoprecv(struct ath_softc *sc);
bool ath_stoprecv(struct ath_softc *sc);
void ath_flushrecv(struct ath_softc *sc);
u_int32_t ath_calcrxfilter(struct ath_softc *sc);
void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
@ -635,9 +633,9 @@ struct ath_tx_stat {
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
int ath_tx_setup(struct ath_softc *sc, int haltype);
void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx);
void ath_draintxq(struct ath_softc *sc, bool retry_tx);
void ath_tx_draintxq(struct ath_softc *sc,
struct ath_txq *txq, enum hal_bool retry_tx);
struct ath_txq *txq, bool retry_tx);
void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
void ath_tx_node_cleanup(struct ath_softc *sc,
struct ath_node *an, bool bh_flag);
@ -695,7 +693,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
enum ATH_AGGR_STATUS {
@ -822,10 +820,6 @@ void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
void ath_get_beaconconfig(struct ath_softc *sc,
int if_id,
struct ath_beacon_config *conf);
struct sk_buff *ath_get_beacon(struct ath_softc *sc,
int if_id,
struct ath_beacon_offset *bo,
struct ath_tx_control *txctl);
int ath_update_beacon(struct ath_softc *sc,
int if_id,
struct ath_beacon_offset *bo,
@ -880,23 +874,11 @@ struct ath_vap {
int ath_vap_attach(struct ath_softc *sc,
int if_id,
struct ieee80211_vif *if_data,
enum hal_opmode opmode,
enum hal_opmode iv_opmode,
int nostabeacons);
enum hal_opmode opmode);
int ath_vap_detach(struct ath_softc *sc, int if_id);
int ath_vap_config(struct ath_softc *sc,
int if_id, struct ath_vap_config *if_config);
int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags);
int ath_vap_listen(struct ath_softc *sc, int if_id);
int ath_vap_join(struct ath_softc *sc,
int if_id,
const u_int8_t bssid[ETH_ALEN],
u_int flags);
int ath_vap_up(struct ath_softc *sc,
int if_id,
const u_int8_t bssid[ETH_ALEN],
u_int8_t aid,
u_int flags);
/*********************/
/* Antenna diversity */
@ -972,12 +954,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
#define ATH_ISR_NOSCHED 0x0000 /* Do not schedule bottom half */
/* Schedule the bottom half for execution */
#define ATH_ISR_SCHED 0x0001
/* This was not my interrupt, for shared IRQ's */
#define ATH_ISR_NOTMINE 0x0002
#define RSSI_LPF_THRESHOLD -20
#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
#define ATH_RATE_DUMMY_MARKER 0
@ -1042,34 +1018,13 @@ struct ath_softc {
enum hal_opmode sc_opmode; /* current operating mode */
/* Properties, Config */
unsigned int
sc_invalid : 1, /* being detached */
sc_mrretry : 1, /* multi-rate retry support */
sc_needmib : 1, /* enable MIB stats intr */
sc_hasdiversity : 1, /* rx diversity available */
sc_diversity : 1, /* enable rx diversity */
sc_hasveol : 1, /* tx VEOL support */
sc_beacons : 1, /* beacons running */
sc_hasbmask : 1, /* bssid mask support */
sc_hastsfadd : 1, /* tsf adjust support */
sc_scanning : 1, /* scanning active */
sc_nostabeacons : 1, /* no beacons for station */
sc_hasclrkey : 1, /* CLR key supported */
sc_stagbeacons : 1, /* use staggered beacons */
sc_txaggr : 1, /* enable 11n tx aggregation */
sc_rxaggr : 1, /* enable 11n rx aggregation */
sc_hasautosleep : 1, /* automatic sleep after TIM */
sc_waitbeacon : 1, /* waiting for first beacon
after waking up */
sc_no_tx_3_chains : 1, /* user, hardware, regulatory
or country may disallow transmit on
three chains. */
sc_update_chainmask : 1, /* change chain mask */
sc_rx_chainmask_detect : 1, /* enable rx chain mask detection */
sc_rx_chainmask_start : 1, /* start rx chain mask detection */
sc_hashtsupport : 1, /* supports 11n */
sc_full_reset : 1, /* force full reset */
sc_slowAntDiv : 1; /* enable slow antenna diversity */
u_int8_t sc_invalid; /* being detached */
u_int8_t sc_beacons; /* beacons running */
u_int8_t sc_scanning; /* scanning active */
u_int8_t sc_txaggr; /* enable 11n tx aggregation */
u_int8_t sc_rxaggr; /* enable 11n rx aggregation */
u_int8_t sc_update_chainmask; /* change chain mask */
u_int8_t sc_full_reset; /* force full reset */
enum wireless_mode sc_curmode; /* current phy mode */
u_int16_t sc_curtxpow; /* current tx power limit */
u_int16_t sc_curaid; /* current association id */
@ -1119,7 +1074,7 @@ struct ath_softc {
/* Crypto */
u_int sc_keymax; /* size of key cache */
u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
DECLARE_BITMAP (sc_keymap, ATH_KEYBYTES);/* key use bit map */
u_int8_t sc_splitmic; /* split TKIP MIC keys */
int sc_keytype; /* type of the key being used */
@ -1181,7 +1136,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc);
void ath_deinit(struct ath_softc *sc);
int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
int ath_suspend(struct ath_softc *sc);
int ath_intr(struct ath_softc *sc);
irqreturn_t ath_isr(int irq, void *dev);
int ath_reset(struct ath_softc *sc);
void ath_scan_start(struct ath_softc *sc);
void ath_scan_end(struct ath_softc *sc);
@ -1202,7 +1157,6 @@ void ath_setup_rate(struct ath_softc *sc,
/* Utility Functions */
/*********************/
void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode);
void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
int ath_keyset(struct ath_softc *sc,
u_int16_t keyix,

1501
package/ath9k/src/drivers/net/wireless/ath9k/hw.c
View File

File diff suppressed because it is too large Load Diff

14
package/ath9k/src/drivers/net/wireless/ath9k/hw.h
View File

@ -711,7 +711,7 @@ struct ath_hal_5416 {
u_int32_t ah_txUrnInterruptMask;
struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
enum hal_power_mode ah_powerMode;
enum hal_bool ah_chipFullSleep;
bool ah_chipFullSleep;
u_int32_t ah_atimWindow;
enum hal_ant_setting ah_diversityControl;
u_int16_t ah_antennaSwitchSwap;
@ -754,7 +754,7 @@ struct ath_hal_5416 {
u_int32_t ah_tx6PowerInHalfDbm;
u_int32_t ah_staId1Defaults;
u_int32_t ah_miscMode;
enum hal_bool ah_tpcEnabled;
bool ah_tpcEnabled;
u_int32_t ah_beaconInterval;
enum {
AUTO_32KHZ,
@ -780,9 +780,9 @@ struct ath_hal_5416 {
u_int32_t ah_gpioSelect;
u_int32_t ah_polarity;
u_int32_t ah_gpioBit;
enum hal_bool ah_eepEnabled;
bool ah_eepEnabled;
u_int32_t ah_procPhyErr;
enum hal_bool ah_hasHwPhyCounters;
bool ah_hasHwPhyCounters;
u_int32_t ah_aniPeriod;
struct ar5416AniState *ah_curani;
struct ar5416AniState ah_ani[255];
@ -792,7 +792,7 @@ struct ath_hal_5416 {
int ah_firpwr[5];
u_int16_t ah_ratesArray[16];
u_int32_t ah_intrTxqs;
enum hal_bool ah_intrMitigation;
bool ah_intrMitigation;
u_int32_t ah_cycleCount;
u_int32_t ah_ctlBusy;
u_int32_t ah_extBusy;
@ -899,8 +899,8 @@ struct ath_hal_5416 {
#define HAL_ANI_CCK_TRIG_HIGH 200
#define HAL_ANI_CCK_TRIG_LOW 100
#define HAL_ANI_NOISE_IMMUNE_LVL 4
#define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE
#define HAL_ANI_CCK_WEAK_SIG_THR AH_FALSE
#define HAL_ANI_USE_OFDM_WEAK_SIG true
#define HAL_ANI_CCK_WEAK_SIG_THR false
#define HAL_ANI_SPUR_IMMUNE_LVL 7
#define HAL_ANI_FIRSTEP_LVL 0
#define HAL_ANI_RSSI_THR_HIGH 40

387
package/ath9k/src/drivers/net/wireless/ath9k/main.c
View File

@ -108,7 +108,7 @@ static int ath_setkey_tkip(struct ath_softc *sc,
memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
/* Txmic entry failed. No need to proceed further */
DPRINTF(sc, ATH_DEBUG_KEYCACHE,
DPRINTF(sc, ATH_DBG_KEYCACHE,
"%s Setting TX MIC Key Failed\n", __func__);
return 0;
}
@ -279,65 +279,6 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
rx_status->flag |= RX_FLAG_TSFT;
}
/*
* Update all associated nodes and VAPs
*
* Called when local channel width changed. e.g. if AP mode,
* update all associated STAs when the AP's channel width changes.
*/
static void cwm_rate_updateallnodes(struct ath_softc *sc)
{
int flags = 0, error;
struct ieee80211_vif *vif;
enum ieee80211_if_types opmode;
struct ieee80211_hw *hw = sc->hw;
if (sc->sc_vaps[0]) {
vif = sc->sc_vaps[0]->av_if_data;
opmode = vif->type;
switch (opmode) {
case IEEE80211_IF_TYPE_STA:
/* sync with next received beacon */
flags |= ATH_IF_BEACON_SYNC;
if (hw->conf.ht_conf.ht_supported)
flags |= ATH_IF_HT;
error = ath_vap_up(sc, 0,
/* sc->sc_vaps[i]->av_btxctl->if_id, FIX ME if_id */
/* sc->sc_vaps[i]->bssid, FIX ME bssid */
sc->sc_curbssid,
sc->sc_curaid,
flags);
if (error)/* FIX ME if_id */
DPRINTF(sc, ATH_DEBUG_CWM,
"%s: Unable to up vap: "
"%d\n", __func__, 0);
else
DPRINTF(sc, ATH_DEBUG_CWM,
"%s: VAP up for id: "
"%d\n", __func__, 0);
break;
case IEEE80211_IF_TYPE_IBSS:
case IEEE80211_IF_TYPE_AP:
/* FIXME */
break;
default:
break;
}
}
}
/* Action: switch MAC from 40 to 20 (OR) 20 to 40 based on ch_width arg */
static void cwm_action_mac_change_chwidth(struct ath_softc *sc,
enum hal_ht_macmode ch_width)
{
ath_set_macmode(sc, ch_width);
/* notify rate control of new mode (select new rate table) */
cwm_rate_updateallnodes(sc);
/* XXX: all virtual APs - send ch width action management frame */
}
static u_int8_t parse_mpdudensity(u_int8_t mpdudensity)
{
/*
@ -380,7 +321,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
struct hal_channel hchan;
int error = 0;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Starting driver with "
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
"initial channel: %d MHz\n", __func__, curchan->center_freq);
/* setup initial channel */
@ -391,7 +332,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
/* open ath_dev */
error = ath_open(sc, &hchan);
if (error) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to complete ath_open\n", __func__);
return error;
}
@ -416,12 +357,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
memmove(skb->data, skb->data + padsize, hdrlen);
}
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: transmitting packet, skb: %p\n",
DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
__func__,
skb);
if (ath_tx_start(sc, skb) != 0) {
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TX failed\n", __func__);
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
dev_kfree_skb_any(skb);
/* FIXME: Check for proper return value from ATH_DEV */
return 0;
@ -430,26 +371,16 @@ static int ath9k_tx(struct ieee80211_hw *hw,
return 0;
}
static int ath9k_beacon_update(struct ieee80211_hw *hw,
struct sk_buff *skb)
{
struct ath_softc *sc = hw->priv;
DPRINTF(sc, ATH_DEBUG_BEACON, "%s: Update Beacon\n", __func__);
return ath9k_tx(hw, skb);
}
static void ath9k_stop(struct ieee80211_hw *hw)
{
struct ath_softc *sc = hw->priv;
int error;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Driver halt\n", __func__);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
error = ath_suspend(sc);
if (error)
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: Device is no longer present\n", __func__);
ieee80211_stop_queues(hw);
@ -464,50 +395,74 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
/* Support only vap for now */
if (sc->sc_nvaps)
return -1;
return -ENOBUFS;
switch (conf->type) {
case IEEE80211_IF_TYPE_STA:
ic_opmode = HAL_M_STA;
default:
break;
case IEEE80211_IF_TYPE_IBSS:
ic_opmode = HAL_M_IBSS;
break;
default:
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Only STA and IBSS are supported currently\n",
__func__);
return -EOPNOTSUPP;
}
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Attach a VAP of type: %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
__func__,
ic_opmode);
error = ath_vap_attach(sc, 0, conf->vif, ic_opmode, ic_opmode, 0);
error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
if (error) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to attach vap, error: %d\n",
__func__, error);
goto bad;
return error;
}
return 0;
bad:
return -1;
}
static void ath9k_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf)
{
struct ath_softc *sc = hw->priv;
int error, flags = 0;
struct ath_vap *avp;
int error;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Detach VAP\n", __func__);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
flags |= ATH_IF_HW_OFF;
avp = sc->sc_vaps[0];
if (avp == NULL) {
DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
__func__);
return;
}
error = ath_vap_down(sc, 0, flags);
if (error)
DPRINTF(sc, ATH_DEBUG_FATAL,
"%s: Unable to down vap, error: %d\n", __func__, error);
#ifdef CONFIG_SLOW_ANT_DIV
ath_slow_ant_div_stop(&sc->sc_antdiv);
#endif
/* Update ratectrl */
ath_rate_newstate(sc, avp, 0);
/* Reclaim beacon resources */
if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
ath_beacon_return(sc, avp);
}
/* Set interrupt mask */
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~HAL_INT_GLOBAL);
sc->sc_beacons = 0;
error = ath_vap_detach(sc, 0);
if (error)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to detach vap, error: %d\n",
__func__, error);
}
@ -519,7 +474,7 @@ static int ath9k_config(struct ieee80211_hw *hw,
struct ieee80211_channel *curchan = hw->conf.channel;
struct hal_channel hchan;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Set channel: %d MHz\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
__func__,
curchan->center_freq);
@ -529,7 +484,7 @@ static int ath9k_config(struct ieee80211_hw *hw,
/* set h/w channel */
if (ath_set_channel(sc, &hchan) < 0)
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: Unable to set channel\n",
DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
__func__);
return 0;
@ -540,41 +495,101 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
struct ieee80211_if_conf *conf)
{
struct ath_softc *sc = hw->priv;
int error = 0, flags = 0;
struct sk_buff *beacon;
struct ath_vap *avp;
u_int32_t rfilt = 0;
int error, i;
DECLARE_MAC_BUF(mac);
if (!conf->bssid)
return 0;
switch (vif->type) {
case IEEE80211_IF_TYPE_STA:
/* XXX: Handle (conf->changed & IEEE80211_IFCC_SSID) */
flags |= ATH_IF_HW_ON;
/* sync with next received beacon */
flags |= ATH_IF_BEACON_SYNC;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Bring up VAP: %d\n",
__func__, 0);
error = ath_vap_up(sc, 0, conf->bssid, 0, flags);
if (error) {
DPRINTF(sc, ATH_DEBUG_FATAL,
"%s: Unable to bring up VAP: %d, error: %d\n",
__func__, 0, error);
return -1;
avp = sc->sc_vaps[0];
if (avp == NULL) {
DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
__func__);
return -EINVAL;
}
break;
if ((conf->changed & IEEE80211_IFCC_BSSID) &&
!is_zero_ether_addr(conf->bssid)) {
switch (vif->type) {
case IEEE80211_IF_TYPE_STA:
case IEEE80211_IF_TYPE_IBSS:
if (!(conf->changed & IEEE80211_IFCC_BEACON))
/* Update ratectrl about the new state */
ath_rate_newstate(sc, avp, 0);
/* Set rx filter */
rfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
/* Set BSSID */
memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
sc->sc_curaid = 0;
ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
sc->sc_curaid);
/* Set aggregation protection mode parameters */
sc->sc_config.ath_aggr_prot = 0;
/*
* Reset our TSF so that its value is lower than the
* beacon that we are trying to catch.
* Only then hw will update its TSF register with the
* new beacon. Reset the TSF before setting the BSSID
* to avoid allowing in any frames that would update
* our TSF only to have us clear it
* immediately thereafter.
*/
ath9k_hw_reset_tsf(sc->sc_ah);
/* Disable BMISS interrupt when we're not associated */
ath9k_hw_set_interrupts(sc->sc_ah,
sc->sc_imask &
~(HAL_INT_SWBA | HAL_INT_BMISS));
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
__func__, rfilt,
print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
/* need to reconfigure the beacon */
sc->sc_beacons = 0;
break;
beacon = ieee80211_beacon_get(hw, vif);
if (!beacon)
return -ENOMEM;
ath9k_beacon_update(hw, beacon);
default:
break;
}
}
if ((conf->changed & IEEE80211_IFCC_BEACON) &&
(vif->type == IEEE80211_IF_TYPE_IBSS)) {
/*
* Allocate and setup the beacon frame.
*
* Stop any previous beacon DMA. This may be
* necessary, for example, when an ibss merge
* causes reconfiguration; we may be called
* with beacon transmission active.
*/
ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
error = ath_beacon_alloc(sc, 0);
if (error != 0)
return error;
ath_beacon_sync(sc, 0);
}
/* Check for WLAN_CAPABILITY_PRIVACY ? */
if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
for (i = 0; i < IEEE80211_WEP_NKID; i++)
if (ath9k_hw_keyisvalid(sc->sc_ah, (u_int16_t)i))
ath9k_hw_keysetmac(sc->sc_ah,
(u_int16_t)i,
sc->sc_curbssid);
}
/* Only legacy IBSS for now */
if (vif->type == IEEE80211_IF_TYPE_IBSS)
ath_update_chainmask(sc, 0);
return 0;
}
@ -627,7 +642,7 @@ static void ath9k_sta_notify(struct ieee80211_hw *hw,
spin_lock_irqsave(&sc->node_lock, flags);
if (!an) {
ath_node_attach(sc, (u8 *)addr, 0);
DPRINTF(sc, ATH_DEBUG_NODE, "%s: Attach a node: %s\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
__func__,
print_mac(mac, addr));
} else {
@ -637,12 +652,12 @@ static void ath9k_sta_notify(struct ieee80211_hw *hw,
break;
case STA_NOTIFY_REMOVE:
if (!an)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Removal of a non-existent node\n",
__func__);
else {
ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
DPRINTF(sc, ATH_DEBUG_NODE, "%s: Put a node: %s\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
__func__,
print_mac(mac, addr));
}
@ -669,7 +684,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
qi.tqi_burstTime = params->txop;
qnum = ath_get_hal_qnum(queue, sc);
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: Configure tx [queue/halq] [%d/%d], "
"aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
__func__,
@ -682,7 +697,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
ret = ath_txq_update(sc, qnum, &qi);
if (ret)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: TXQ Update failed\n", __func__);
return ret;
@ -697,7 +712,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
struct ath_softc *sc = hw->priv;
int ret = 0;
DPRINTF(sc, ATH_DEBUG_KEYCACHE, " %s: Set HW Key\n", __func__);
DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
switch (cmd) {
case SET_KEY:
@ -741,7 +756,7 @@ static void ath9k_ht_conf(struct ath_softc *sc,
else
ht_info->tx_chan_width = HAL_HT_MACMODE_20;
cwm_action_mac_change_chwidth(sc, ht_info->tx_chan_width);
ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
bss_conf->ht_conf->ampdu_factor);
ht_info->mpdudensity =
@ -758,16 +773,50 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
struct ieee80211_hw *hw = sc->hw;
struct ieee80211_channel *curchan = hw->conf.channel;
struct hal_channel hchan;
struct ath_vap *avp;
DECLARE_MAC_BUF(mac);
if (bss_conf->assoc) {
/* FIXME : Do we need any other info
* which is part of association */
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Bss Info ASSOC %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
__func__,
bss_conf->aid);
sc->sc_curaid = bss_conf->aid;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Set channel: %d MHz\n",
avp = sc->sc_vaps[0];
if (avp == NULL) {
DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
__func__);
return;
}
/* Update ratectrl about the new state */
ath_rate_newstate(sc, avp, 1);
/* New association, store aid */
if (avp->av_opmode == HAL_M_STA) {
sc->sc_curaid = bss_conf->aid;
ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
sc->sc_curaid);
}
/* Configure the beacon */
ath_beacon_config(sc, 0);
sc->sc_beacons = 1;
/* Reset rssi stats */
sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
/* Update chainmask */
ath_update_chainmask(sc, bss_conf->assoc_ht);
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: bssid %s aid 0x%x\n",
__func__,
print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
__func__,
curchan->center_freq);
@ -776,11 +825,11 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
/* set h/w channel */
if (ath_set_channel(sc, &hchan) < 0)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to set channel\n",
__func__);
} else {
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: Bss Info DISSOC\n", __func__);
sc->sc_curaid = 0;
}
@ -794,7 +843,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
struct ath_softc *sc = hw->priv;
if (changed & BSS_CHANGED_ERP_PREAMBLE) {
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
__func__,
bss_conf->use_short_preamble);
if (bss_conf->use_short_preamble)
@ -804,7 +853,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
}
if (changed & BSS_CHANGED_ERP_CTS_PROT) {
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
__func__,
bss_conf->use_cts_prot);
if (bss_conf->use_cts_prot &&
@ -815,14 +864,14 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
}
if (changed & BSS_CHANGED_HT) {
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed HT %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
__func__,
bss_conf->assoc_ht);
ath9k_ht_conf(sc, bss_conf);
}
if (changed & BSS_CHANGED_ASSOC) {
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed ASSOC %d\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
__func__,
bss_conf->assoc);
ath9k_bss_assoc_info(sc, bss_conf);
@ -861,21 +910,21 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
case IEEE80211_AMPDU_RX_START:
ret = ath_rx_aggr_start(sc, addr, tid, ssn);
if (ret < 0)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to start RX aggregation\n",
__func__);
break;
case IEEE80211_AMPDU_RX_STOP:
ret = ath_rx_aggr_stop(sc, addr, tid);
if (ret < 0)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to stop RX aggregation\n",
__func__);
break;
case IEEE80211_AMPDU_TX_START:
ret = ath_tx_aggr_start(sc, addr, tid, ssn);
if (ret < 0)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to start TX aggregation\n",
__func__);
else
@ -884,14 +933,14 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
case IEEE80211_AMPDU_TX_STOP:
ret = ath_tx_aggr_stop(sc, addr, tid);
if (ret < 0)
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to stop TX aggregation\n",
__func__);
ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
break;
default:
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unknown AMPDU action\n", __func__);
}
@ -1024,7 +1073,7 @@ void ath_setup_channel_list(struct ath_softc *sc,
flags;
sc->sbands[IEEE80211_BAND_2GHZ].n_channels++;
a++;
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: 2MHz channel: %d, "
"channelFlags: 0x%x\n",
__func__,
@ -1051,7 +1100,7 @@ void ath_setup_channel_list(struct ath_softc *sc,
flags = flags;
sc->sbands[IEEE80211_BAND_5GHZ].n_channels++;
b++;
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: 5MHz channel: %d, "
"channelFlags: 0x%x\n",
__func__,
@ -1076,14 +1125,6 @@ void ath_get_beaconconfig(struct ath_softc *sc,
conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
}
struct sk_buff *ath_get_beacon(struct ath_softc *sc,
int if_id,
struct ath_beacon_offset *bo,
struct ath_tx_control *txctl)
{
return NULL;
}
int ath_update_beacon(struct ath_softc *sc,
int if_id,
struct ath_beacon_offset *bo,
@ -1099,7 +1140,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
struct ieee80211_hw *hw = sc->hw;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
DPRINTF(sc, ATH_DEBUG_XMIT,
DPRINTF(sc, ATH_DBG_XMIT,
"%s: TX complete: skb: %p\n", __func__, skb);
if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
@ -1225,7 +1266,7 @@ void ath_setup_rate(struct ath_softc *sc,
maxrates = rt->rateCount;
if ((band_2ghz->n_bitrates != 0) && (band_5ghz->n_bitrates != 0)) {
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: Rates already setup\n", __func__);
return;
}
@ -1252,7 +1293,7 @@ void ath_setup_rate(struct ath_softc *sc,
if (band_2ghz->n_bitrates) {
for (i = 0; i < band_2ghz->n_bitrates; i++) {
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: 2GHz Rate: %2dMbps, ratecode: %2d\n",
__func__,
rates_2ghz[i].bitrate / 10,
@ -1260,7 +1301,7 @@ void ath_setup_rate(struct ath_softc *sc,
}
} else if (band_5ghz->n_bitrates) {
for (i = 0; i < band_5ghz->n_bitrates; i++) {
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: 5Ghz Rate: %2dMbps, ratecode: %2d\n",
__func__,
rates_5ghz[i].bitrate / 10,
@ -1273,7 +1314,7 @@ static int ath_detach(struct ath_softc *sc)
{
struct ieee80211_hw *hw = sc->hw;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Detach ATH hw\n", __func__);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
/* Unregister hw */
@ -1300,7 +1341,7 @@ static int ath_attach(u_int16_t devid,
struct ieee80211_hw *hw = sc->hw;
int error = 0;
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Attach ATH hw\n", __func__);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
error = ath_init(devid, sc);
if (error != 0)
@ -1323,7 +1364,7 @@ static int ath_attach(u_int16_t devid,
sc->rates[IEEE80211_BAND_2GHZ];
sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
if (sc->sc_hashtsupport)
if (sc->sc_ah->ah_caps.halHTSupport)
/* Setup HT capabilities for 2.4Ghz*/
setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
@ -1338,7 +1379,7 @@ static int ath_attach(u_int16_t devid,
sc->sbands[IEEE80211_BAND_5GHZ].band =
IEEE80211_BAND_5GHZ;
if (sc->sc_hashtsupport)
if (sc->sc_ah->ah_caps.halHTSupport)
/* Setup HT capabilities for 5Ghz*/
setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
@ -1355,7 +1396,7 @@ static int ath_attach(u_int16_t devid,
hw->rate_control_algorithm = "ath9k_rate_control";
error = ath_rate_control_register();
if (error != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: Unable to register rate control "
"algorithm:%d\n", __func__, error);
ath_rate_control_unregister();
@ -1385,26 +1426,6 @@ bad:
return error;
}
static irqreturn_t ath_isr(int irq, void *dev_id)
{
struct ath_softc *sc = dev_id;
int sched;
/* always acknowledge the interrupt */
sched = ath_intr(sc);
switch (sched) {
case ATH_ISR_NOSCHED:
return IRQ_HANDLED;
case ATH_ISR_NOTMINE:
return IRQ_NONE;
default:
tasklet_schedule(&sc->intr_tq);
return IRQ_HANDLED;
}
}
static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
void __iomem *mem;

46
package/ath9k/src/drivers/net/wireless/ath9k/phy.c
View File

@ -14,7 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ath9k.h"
#include "core.h"
#include "hw.h"
#include "reg.h"
#include "phy.h"
@ -28,7 +28,7 @@ ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
}
enum hal_bool
bool
ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
{
u_int32_t channelSel = 0;
@ -51,10 +51,10 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HDPRINTF(ah, HAL_DBG_CHANNEL,
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u MHz\n", __func__,
freq);
return AH_FALSE;
return false;
}
channelSel = (channelSel << 2) & 0xff;
@ -85,9 +85,9 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
aModeRefSel = ath9k_hw_reverse_bits(1, 2);
} else {
HDPRINTF(ah, HAL_DBG_CHANNEL,
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u MHz\n", __func__, freq);
return AH_FALSE;
return false;
}
reg32 =
@ -100,10 +100,10 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
AH5416(ah)->ah_curchanRadIndex = -1;
return AH_TRUE;
return true;
}
enum hal_bool
bool
ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
struct hal_channel_internal *chan)
{
@ -150,7 +150,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
refDivA = 1;
channelSel = (freq * 0x8000) / 15;
OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
REG_RMW_FIELD(ah, AR_AN_SYNTH9,
AR_AN_SYNTH9_REFDIVA, refDivA);
}
if (!fracMode) {
@ -171,7 +171,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
AH5416(ah)->ah_curchanRadIndex = -1;
return AH_TRUE;
return true;
}
static void
@ -201,7 +201,7 @@ ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
}
}
enum hal_bool
bool
ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
u_int16_t modesIndex)
{
@ -213,7 +213,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
int regWrites = 0;
if (AR_SREV_9280_10_OR_LATER(ah))
return AH_TRUE;
return true;
eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV);
@ -266,7 +266,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
regWrites);
return AH_TRUE;
return true;
}
void
@ -312,11 +312,11 @@ ath9k_hw_rfdetach(struct ath_hal *ah)
}
}
enum hal_bool
bool
ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
struct hal_channel *chans, u_int32_t nchans)
{
enum hal_bool retVal = AH_TRUE;
bool retVal = true;
int i;
for (i = 0; i < nchans; i++) {
@ -327,7 +327,7 @@ ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
}
enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
{
struct ath_hal_5416 *ahp = AH5416(ah);
@ -362,11 +362,11 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
|| ahp->ah_analogBank6Data == NULL
|| ahp->ah_analogBank6TPCData == NULL
|| ahp->ah_analogBank7Data == NULL) {
HDPRINTF(ah, HAL_DBG_MALLOC,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate RF banks\n",
__func__);
*status = HAL_ENOMEM;
return AH_FALSE;
return false;
}
ahp->ah_addac5416_21 =
@ -374,26 +374,26 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
ahp->ah_iniAddac.ia_rows *
ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
if (ahp->ah_addac5416_21 == NULL) {
HDPRINTF(ah, HAL_DBG_MALLOC,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate ah_addac5416_21\n",
__func__);
*status = HAL_ENOMEM;
return AH_FALSE;
return false;
}
ahp->ah_bank6Temp =
kzalloc((sizeof(u_int32_t) *
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
if (ahp->ah_bank6Temp == NULL) {
HDPRINTF(ah, HAL_DBG_MALLOC,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"%s: cannot allocate ah_bank6Temp\n",
__func__);
*status = HAL_ENOMEM;
return AH_FALSE;
return false;
}
}
return AH_TRUE;
return true;
}
void

10
package/ath9k/src/drivers/net/wireless/ath9k/phy.h
View File

@ -17,19 +17,19 @@
#ifndef PHY_H
#define PHY_H
enum hal_bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
struct hal_channel_internal
*chan);
enum hal_bool ath9k_hw_set_channel(struct ath_hal *ah,
bool ath9k_hw_set_channel(struct ath_hal *ah,
struct hal_channel_internal *chan);
void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
u_int freqIndex, int regWrites);
enum hal_bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
struct hal_channel_internal *chan,
u_int16_t modesIndex);
void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
struct hal_channel *chan);
enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
bool ath9k_hw_init_rf(struct ath_hal *ah,
enum hal_status *status);
#define AR_PHY_BASE 0x9800
@ -518,7 +518,7 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
int r; \
for (r = 0; r < ((iniarray)->ia_rows); r++) { \
REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
HDPRINTF(ah, HAL_DBG_CHANNEL, \
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, \
"RF 0x%x V 0x%x\n", \
INI_RA((iniarray), r, 0), (regData)[r]); \
DO_DELAY(regWr); \

42
package/ath9k/src/drivers/net/wireless/ath9k/rc.c
View File

@ -1149,7 +1149,7 @@ void ath_rate_findrate(struct ath_softc *sc,
{
struct ath_vap *avp = ath_rc_priv->avp;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
if (!num_rates || !num_tries)
return;
@ -1652,7 +1652,7 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
avp = rc_priv->avp;
if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE)
|| info_priv->tx.ts_status & HAL_TXERR_FILT)
|| info_priv->tx.ts_status & ATH9K_TXERR_FILT)
return;
if (info_priv->tx.ts_rssi > 0) {
@ -1667,14 +1667,14 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
* times. This affects how ratectrl updates PER for the failed rate.
*/
if (info_priv->tx.ts_flags &
(HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN) &&
(ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) &&
((sc->sc_ah->ah_txTrigLevel) >= tx_triglevel_max)) {
tx_status = 1;
is_underrun = 1;
}
if ((info_priv->tx.ts_status & HAL_TXERR_XRETRY) ||
(info_priv->tx.ts_status & HAL_TXERR_FIFO))
if ((info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) ||
(info_priv->tx.ts_status & ATH9K_TXERR_FIFO))
tx_status = 1;
ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,
@ -1822,7 +1822,7 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
struct ath_rate_node *rc_priv = sta->rate_ctrl_priv;
int i, j = 0;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
for (i = 0; i < sband->n_bitrates; i++) {
if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) {
@ -1920,7 +1920,7 @@ static void ath_tx_aggr_resp(struct ath_softc *sc,
txtid->addba_exchangeinprogress = 0;
txtid->baw_size = buffersize;
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Resuming tid, buffersize: %d\n",
__func__,
buffersize);
@ -1949,7 +1949,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
u8 *qc, tid;
DECLARE_MAC_BUF(mac);
DPRINTF(sc, ATH_DEBUG_RATE, "%s\n", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
/* allocate driver private area of tx_info */
tx_info->driver_data[0] = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
@ -1974,8 +1974,8 @@ static void ath_get_rate(void *priv, struct net_device *dev,
ATH_RC_PROBE_ALLOWED,
tx_info_priv->rcs,
&is_probe,
AH_FALSE);
if (is_probe == AH_TRUE)
false);
if (is_probe)
sel->probe_idx = ((struct ath_tx_ratectrl *)
sta->rate_ctrl_priv)->probe_rate;
@ -1999,7 +1999,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
spin_unlock_bh(&sc->node_lock);
if (!an) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Node not found to "
"init/chk TX aggr\n", __func__);
return;
@ -2010,13 +2010,13 @@ static void ath_get_rate(void *priv, struct net_device *dev,
ret = ieee80211_start_tx_ba_session(hw,
hdr->addr1, tid);
if (ret)
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Unable to start tx "
"aggr for: %s\n",
__func__,
print_mac(mac, hdr->addr1));
else
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Started tx aggr for: %s\n",
__func__,
print_mac(mac, hdr->addr1));
@ -2034,19 +2034,13 @@ static void ath_rate_init(void *priv, void *priv_sta,
struct ieee80211_hw *hw = local_to_hw(local);
struct ieee80211_conf *conf = &local->hw.conf;
struct ath_softc *sc = hw->priv;
struct hal_channel hchan;
int i, j = 0;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
sta->txrate_idx = rate_lowest_index(local, sband, sta);
hchan.channel = conf->channel->center_freq;
hchan.channelFlags = ath_chan2flags(conf->channel, sc);
if (ath_set_channel(sc, &hchan) < 0)
DPRINTF(sc, ATH_DEBUG_FATAL, "%s: Unable to set channel\n",
__func__);
ath_setup_rates(local, sta);
if (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) {
for (i = 0; i < MCS_SET_SIZE; i++) {
@ -2071,7 +2065,7 @@ static void *ath_rate_alloc(struct ieee80211_local *local)
struct ieee80211_hw *hw = local_to_hw(local);
struct ath_softc *sc = hw->priv;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
return local->hw.priv;
}
@ -2086,10 +2080,10 @@ static void *ath_rate_alloc_sta(void *priv, gfp_t gfp)
struct ath_vap *avp = sc->sc_vaps[0];
struct ath_rate_node *rate_priv;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp);
if (!rate_priv) {
DPRINTF(sc, ATH_DEBUG_FATAL, "%s:Unable to allocate"
DPRINTF(sc, ATH_DBG_FATAL, "%s:Unable to allocate"
"private rate control structure", __func__);
return NULL;
}
@ -2102,7 +2096,7 @@ static void ath_rate_free_sta(void *priv, void *priv_sta)
struct ath_rate_node *rate_priv = priv_sta;
struct ath_softc *sc = priv;
DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
ath_rate_node_free(rate_priv);
}

141
package/ath9k/src/drivers/net/wireless/ath9k/recv.c
View File

@ -80,7 +80,7 @@ static int ath_bar_rx(struct ath_softc *sc,
/* look at BAR contents */
bar = (struct ieee80211_bar *)skb->data;
tidno = (bar->control & IEEE80211_BAR_CTL_TID_M)
tidno = (le16_to_cpu(bar->control) & IEEE80211_BAR_CTL_TID_M)
>> IEEE80211_BAR_CTL_TID_S;
seqno = le16_to_cpu(bar->start_seq_num) >> IEEE80211_SEQ_SEQ_SHIFT;
@ -385,60 +385,6 @@ static void ath_rx_flush_tid(struct ath_softc *sc,
spin_unlock_bh(&rxtid->tidlock);
}
static u_int8_t ath_rx_detect_antenna(struct ath_softc *sc,
struct ath_rx_status *rxstat)
{
#define ATH_RX_CHAINMASK_CLR(_chainmask, _chain) \
((_chainmask) &= ~(1 << (_chain)))
u_int8_t rx_chainmask = sc->sc_rx_chainmask;
int rssiRef, detectThresh, detectDelta;
if (IS_CHAN_5GHZ(&sc->sc_curchan)) {
detectThresh = sc->sc_rxchaindetect_thresh5GHz;
detectDelta = sc->sc_rxchaindetect_delta5GHz;
} else {
detectThresh = sc->sc_rxchaindetect_thresh2GHz;
detectDelta = sc->sc_rxchaindetect_delta2GHz;
}
switch (sc->sc_rxchaindetect_ref) {
case 0:
rssiRef = rxstat->rs_rssi;
if (rssiRef < detectThresh)
return 0;
if (rssiRef - rxstat->rs_rssi_ctl1 > detectDelta)
ATH_RX_CHAINMASK_CLR(rx_chainmask, 1);
if (rssiRef - rxstat->rs_rssi_ctl2 > detectDelta)
ATH_RX_CHAINMASK_CLR(rx_chainmask, 2);
break;
case 1:
rssiRef = rxstat->rs_rssi_ctl1;
if (rssiRef < detectThresh)
return 0;
if (rssiRef - rxstat->rs_rssi_ctl2 > detectDelta)
ATH_RX_CHAINMASK_CLR(rx_chainmask, 2);
break;
case 2:
rssiRef = rxstat->rs_rssi_ctl2;
if (rssiRef < detectThresh)
return 0;
if (rssiRef - rxstat->rs_rssi_ctl1 > detectDelta)
ATH_RX_CHAINMASK_CLR(rx_chainmask, 1);
break;
}
return rx_chainmask;
#undef IS_CHAN_5GHZ
#undef ATH_RX_CHAINMASK_CLR
}
static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
u_int32_t len)
{
@ -457,7 +403,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
if (off != 0)
skb_reserve(skb, sc->sc_cachelsz - off);
} else {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: skbuff alloc of size %u failed\n",
__func__, len);
return NULL;
@ -532,7 +478,7 @@ static void ath_opmode_init(struct ath_softc *sc)
ath9k_hw_setrxfilter(ah, rfilt);
/* configure bssid mask */
if (sc->sc_hasbmask)
if (ah->ah_caps.halBssIdMaskSupport)
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
/* configure operational mode */
@ -545,7 +491,7 @@ static void ath_opmode_init(struct ath_softc *sc)
mfilt[0] = mfilt[1] = ~0;
ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
DPRINTF(sc, ATH_DEBUG_RECV ,
DPRINTF(sc, ATH_DBG_CONFIG ,
"%s: RX filter 0x%x, MC filter %08x:%08x\n",
__func__, rfilt, mfilt[0], mfilt[1]);
}
@ -571,7 +517,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
min(sc->sc_cachelsz,
(u_int16_t)64));
DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
/* Initialize rx descriptors */
@ -579,7 +525,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
"rx", nbufs, 1);
if (error != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate rx descriptors: %d\n",
__func__, error);
break;
@ -669,7 +615,7 @@ u_int32_t ath_calcrxfilter(struct ath_softc *sc)
}
if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS ||
sc->sc_nostabeacons || sc->sc_scanning)
sc->sc_scanning)
rfilt |= HAL_RX_FILTER_BEACON;
/* If in HOSTAP mode, want to enable reception of PSPOLL frames
@ -728,11 +674,11 @@ start_recv:
/* Disable the receive h/w in preparation for a reset. */
enum hal_bool ath_stoprecv(struct ath_softc *sc)
bool ath_stoprecv(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
u_int64_t tsf;
enum hal_bool stopped;
bool stopped;
ath9k_hw_stoppcurecv(ah); /* disable PCU */
ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
@ -798,12 +744,10 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
struct ath_hal *ah = sc->sc_ah;
int type, rx_processed = 0;
u_int phyerr;
u_int8_t rxchainmask, chainreset = 0;
u_int8_t chainreset = 0;
enum hal_status retval;
__le16 fc;
DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__);
do {
/* If handling rx interrupt and flush is in progress => exit */
if (sc->sc_rxflush && (flush == 0))
@ -961,14 +905,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
#endif
/* fall thru for monitor mode handling... */
} else if (ds->ds_rxstat.rs_status != 0) {
if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
rx_status.flags |= ATH_RX_FCS_ERROR;
if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
goto rx_next;
}
if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
/*
* Decrypt error. We only mark packet status
* here and always push up the frame up to let
@ -977,7 +921,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
* error. This let us keep statistics there.
*/
rx_status.flags |= ATH_RX_DECRYPT_ERROR;
} else if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
} else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
/*
* Demic error. We only mark frame status here
* and always push up the frame up to let
@ -992,7 +936,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
* Remove these mic errors.
*/
ds->ds_rxstat.rs_status &=
~HAL_RXERR_MIC;
~ATH9K_RXERR_MIC;
else
rx_status.flags |= ATH_RX_MIC_ERROR;
}
@ -1003,12 +947,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
*/
if (sc->sc_opmode == HAL_M_MONITOR) {
if (ds->ds_rxstat.rs_status &
~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC |
HAL_RXERR_CRC))
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
ATH9K_RXERR_CRC))
goto rx_next;
} else {
if (ds->ds_rxstat.rs_status &
~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC)) {
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
goto rx_next;
}
}
@ -1026,7 +970,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
* to receive another frame.
*/
skb_put(skb, ds->ds_rxstat.rs_datalen);
skb->protocol = ETH_P_CONTROL;
skb->protocol = cpu_to_be16(ETH_P_CONTROL);
rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
rx_status.rateieee =
sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate;
@ -1037,12 +981,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
/* HT rate */
if (rx_status.ratecode & 0x80) {
/* TODO - add table to avoid division */
if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
rx_status.flags |= ATH_RX_40MHZ;
rx_status.rateKbps =
(rx_status.rateKbps * 27) / 13;
}
if (ds->ds_rxstat.rs_flags & HAL_RX_GI)
if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
rx_status.rateKbps =
(rx_status.rateKbps * 10) / 9;
else
@ -1074,7 +1018,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
PCI_DMA_FROMDEVICE);
/* XXX: Ah! make me more readable, use a helper */
if (sc->sc_hashtsupport) {
if (ah->ah_caps.halHTSupport) {
if (ds->ds_rxstat.rs_moreaggr == 0) {
rx_status.rssictl[0] =
ds->ds_rxstat.rs_rssi_ctl0;
@ -1083,7 +1027,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
rx_status.rssictl[2] =
ds->ds_rxstat.rs_rssi_ctl2;
rx_status.rssi = ds->ds_rxstat.rs_rssi;
if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
rx_status.rssiextn[0] =
ds->ds_rxstat.rs_rssi_ext0;
rx_status.rssiextn[1] =
@ -1110,10 +1054,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
type = ath_rx_indicate(sc, skb,
&rx_status, ds->ds_rxstat.rs_keyix);
if (sc->sc_diversity) {
/*
* When using hardware fast diversity, change the
* default rx antenna if rx diversity chooses the
* change the default rx antenna if rx diversity chooses the
* other antenna 3 times in a row.
*/
if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
@ -1123,28 +1065,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
} else {
sc->sc_rxotherant = 0;
}
}
/*
* redo antenna detection for Lenovo devices
*/
if (sc->sc_rx_chainmask_detect && sc->sc_rx_chainmask_start) {
rxchainmask = ath_rx_detect_antenna(sc, &ds->ds_rxstat);
if (rxchainmask) {
sc->sc_rx_chainmask_detect = 0;
sc->sc_rx_chainmask_start = 0;
if (sc->sc_rx_chainmask != rxchainmask) {
sc->sc_rx_chainmask = rxchainmask;
/* we have to do an reset to
* change chain mask */
chainreset = 1;
}
}
}
#ifdef CONFIG_SLOW_ANT_DIV
if (sc->sc_slowAntDiv &&
(rx_status.flags & ATH_RX_RSSI_VALID) &&
if ((rx_status.flags & ATH_RX_RSSI_VALID) &&
ieee80211_is_beacon(fc)) {
ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat);
}
@ -1162,7 +1085,7 @@ rx_next:
} while (TRUE);
if (chainreset) {
DPRINTF(sc, ATH_DEBUG_CONFIG,
DPRINTF(sc, ATH_DBG_CONFIG,
"%s: Reset rx chain mask. "
"Do internal reset\n", __func__);
ASSERT(flush == 0);
@ -1191,7 +1114,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
spin_unlock_bh(&sc->node_lock);
if (!an) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Node not found to initialize RX aggregation\n",
__func__);
return -1;
@ -1216,7 +1139,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
rxtid->seq_next = *ssn;
/* Allocate the receive buffers for this TID */
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Allcating rxbuffer for TID %d\n", __func__, tid);
if (rxtid->rxbuf == NULL) {
@ -1231,7 +1154,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
sizeof(struct ath_rxbuf), GFP_ATOMIC);
}
if (rxtid->rxbuf == NULL) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Unable to allocate RX buffer, "
"refusing ADDBA\n", __func__);
} else {
@ -1239,7 +1162,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
* pointers are null) */
memzero(rxtid->rxbuf, ATH_TID_MAX_BUFS *
sizeof(struct ath_rxbuf));
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Allocated @%p\n", __func__, rxtid->rxbuf);
/* Allow aggregation reception */
@ -1264,7 +1187,7 @@ int ath_rx_aggr_stop(struct ath_softc *sc,
spin_unlock_bh(&sc->node_lock);
if (!an) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: RX aggr stop for non-existent node\n", __func__);
return -1;
}
@ -1290,7 +1213,7 @@ void ath_rx_aggr_teardown(struct ath_softc *sc,
/* De-allocate the receive buffer array allocated when addba started */
if (rxtid->rxbuf) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Deallocating TID %d rxbuff @%p\n",
__func__, tid, rxtid->rxbuf);
kfree(rxtid->rxbuf);

686
package/ath9k/src/drivers/net/wireless/ath9k/regd.c
View File

File diff suppressed because it is too large Load Diff

23
package/ath9k/src/drivers/net/wireless/ath9k/regd.h
View File

@ -19,9 +19,6 @@
#include "ath9k.h"
#define ATH9K_MODE_11A_TURBO ATH9K_MODE_SEL_108A
#define ATH9K_MODE_11G_TURBO ATH9K_MODE_SEL_108G
#define BMLEN 2
#define BMZERO {(u_int64_t) 0, (u_int64_t) 0}
@ -124,7 +121,7 @@
(((_mode == ATH9K_MODE_SEL_11NA_HT40PLUS || \
_mode == ATH9K_MODE_SEL_11NG_HT40PLUS || \
_mode == ATH9K_MODE_SEL_11NA_HT40MINUS || \
_mode == ATH9K_MODE_SEL_11NG_HT40MINUS) ? AH_TRUE : AH_FALSE))
_mode == ATH9K_MODE_SEL_11NG_HT40MINUS) ? true : false))
#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
@ -172,13 +169,13 @@ struct country_code_to_enum_rd {
u_int16_t regDmnEnum;
const char *isoName;
const char *name;
enum hal_bool allow11g;
enum hal_bool allow11aTurbo;
enum hal_bool allow11gTurbo;
enum hal_bool allow11ng20;
enum hal_bool allow11ng40;
enum hal_bool allow11na20;
enum hal_bool allow11na40;
bool allow11g;
bool allow11aTurbo;
bool allow11gTurbo;
bool allow11ng20;
bool allow11ng40;
bool allow11na20;
bool allow11na40;
u_int16_t outdoorChanStart;
};
@ -213,8 +210,8 @@ struct cmode {
u_int32_t flags;
};
#define YES AH_TRUE
#define NO AH_FALSE
#define YES true
#define NO false
struct japan_bandcheck {
u_int16_t freqbandbit;

116
package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
View File

@ -118,11 +118,11 @@ static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
txq->axq_totalqueued++;
txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
DPRINTF(sc, ATH_DEBUG_TX_PROC,
DPRINTF(sc, ATH_DBG_QUEUE,
"%s: txq depth = %d\n", __func__, txq->axq_depth);
if (txq->axq_link != NULL) {
*txq->axq_link = bf->bf_daddr;
DPRINTF(sc, ATH_DEBUG_XMIT,
DPRINTF(sc, ATH_DBG_XMIT,
"%s: link[%u](%p)=%llx (%p)\n",
__func__,
txq->axq_qnum, txq->axq_link,
@ -158,18 +158,18 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
txq->axq_totalqueued++;
txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
DPRINTF(sc, ATH_DEBUG_TX_PROC,
DPRINTF(sc, ATH_DBG_QUEUE,
"%s: txq depth = %d\n", __func__, txq->axq_depth);
if (txq->axq_link == NULL) {
ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
DPRINTF(sc, ATH_DEBUG_XMIT,
DPRINTF(sc, ATH_DBG_XMIT,
"%s: TXDP[%u] = %llx (%p)\n",
__func__, txq->axq_qnum,
ito64(bf->bf_daddr), bf->bf_desc);
} else {
*txq->axq_link = bf->bf_daddr;
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
__func__,
txq->axq_qnum, txq->axq_link,
ito64(bf->bf_daddr), bf->bf_desc);
@ -284,7 +284,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
fc = hdr->frame_control;
rt = sc->sc_currates;
KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
BUG_ON(!rt);
/* Fill misc fields */
@ -334,7 +334,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
/* Try to avoid running out of descriptors */
if (txq->axq_depth >= (ATH_TXBUF - 20)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: TX queue: %d is full, depth: %d\n",
__func__,
txctl->qnum,
@ -558,7 +558,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
if (tid->sched)
return;
tid->sched = AH_TRUE;
tid->sched = true;
list_add_tail(&tid->list, &ac->tid_q);
/*
@ -567,7 +567,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
if (ac->sched)
return;
ac->sched = AH_TRUE;
ac->sched = true;
list_add_tail(&ac->list, &txq->axq_acq);
}
@ -625,7 +625,7 @@ static int ath_tx_num_badfrms(struct ath_softc *sc,
int nbad = 0;
int isaggr = 0;
if (isnodegone || ds->ds_txstat.ts_flags == HAL_TX_SW_ABORTED)
if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
return 0;
isaggr = bf->bf_isaggr;
@ -690,7 +690,7 @@ static u_int32_t ath_pkt_duration(struct ath_softc *sc,
struct ath_buf *bf,
int width,
int half_gi,
enum hal_bool shortPreamble)
bool shortPreamble)
{
const struct hal_rate_table *rt = sc->sc_currates;
u_int32_t nbits, nsymbits, duration, nsymbols;
@ -780,8 +780,8 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
* let rate series flags determine which rates will actually
* use RTS.
*/
if (sc->sc_hashtsupport && bf->bf_isdata) {
KASSERT(an != NULL, ("an == null"));
if (ah->ah_caps.halHTSupport && bf->bf_isdata) {
BUG_ON(!an);
/*
* 802.11g protection not needed, use our default behavior
*/
@ -829,7 +829,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
* in whether or not a short preamble is to be used.
*/
/* NB: cix is set above where RTS/CTS is enabled */
KASSERT(cix != 0xff, ("cix not setup"));
BUG_ON(cix == 0xff);
ctsrate = rt->info[cix].rateCode |
(bf->bf_shpreamble ? rt->info[cix].shortPreamble : 0);
@ -896,7 +896,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
* For non-HT devices, calculate RTS/CTS duration in software
* and disable multi-rate retry.
*/
if (flags && !sc->sc_hashtsupport) {
if (flags && !ah->ah_caps.halHTSupport) {
/*
* Compute the transmit duration based on the frame
* size and the size of an ACK frame. We call into the
@ -1069,7 +1069,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
} else {
if (!tid->cleanup_inprogress && !isnodegone &&
ds->ds_txstat.ts_flags != HAL_TX_SW_ABORTED) {
ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
ath_tx_set_retry(sc, bf);
txpending = 1;
@ -1218,7 +1218,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
tid->addba_exchangeattempts = 0;
spin_unlock_bh(&txq->axq_lock);
tid->cleanup_inprogress = AH_FALSE;
tid->cleanup_inprogress = false;
/* send buffered frames as singles */
ath_tx_flush_tid(sc, tid);
@ -1257,11 +1257,10 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
struct sk_buff *skb;
struct ieee80211_tx_info *tx_info;
struct ath_tx_info_priv *tx_info_priv;
u_int8_t txant;
int nacked, txok, nbad = 0, isrifs = 0;
enum hal_status status;
DPRINTF(sc, ATH_DEBUG_TX_PROC,
DPRINTF(sc, ATH_DBG_QUEUE,
"%s: tx queue %d (%x), link %p\n", __func__,
txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
txq->axq_link);
@ -1345,17 +1344,13 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
spin_unlock_bh(&sc->sc_txbuflock);
}
if (txok) {
txant = ds->ds_txstat.ts_antenna;
sc->sc_ant_tx[txant]++;
}
if (!bf->bf_isampdu) {
/*
* This frame is sent out as a single frame.
* Use hardware retry status for this frame.
*/
bf->bf_retries = ds->ds_txstat.ts_longretry;
if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
bf->bf_isxretried = 1;
nbad = 0;
} else {
@ -1365,9 +1360,9 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
tx_info = IEEE80211_SKB_CB(skb);
tx_info_priv = (struct ath_tx_info_priv *)
tx_info->driver_data[0];
if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
if (ds->ds_txstat.ts_status == 0)
nacked++;
@ -1422,14 +1417,14 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
struct ath_hal *ah = sc->sc_ah;
(void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: tx queue [%u] %x, link %p\n",
DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
__func__, txq->axq_qnum,
ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
}
/* Drain only the data queues */
static void ath_drain_txdataq(struct ath_softc *sc, enum hal_bool retry_tx)
static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
{
struct ath_hal *ah = sc->sc_ah;
int i;
@ -1454,16 +1449,16 @@ static void ath_drain_txdataq(struct ath_softc *sc, enum hal_bool retry_tx)
enum hal_status status;
/* TxDMA not stopped, reset the hal */
DPRINTF(sc, ATH_DEBUG_XMIT,
DPRINTF(sc, ATH_DBG_XMIT,
"%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
spin_lock_bh(&sc->sc_resetlock);
if (!ath9k_hw_reset(ah, sc->sc_opmode,
&sc->sc_curchan, ht_macmode,
sc->sc_tx_chainmask, sc->sc_rx_chainmask,
sc->sc_ht_extprotspacing, AH_TRUE, &status)) {
sc->sc_ht_extprotspacing, true, &status)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to reset hardware; hal status %u\n",
__func__,
status);
@ -1974,10 +1969,10 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
list_del(&ac->list);
ac->sched = AH_FALSE;
ac->sched = false;
list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
list_del(&tid->list);
tid->sched = AH_FALSE;
tid->sched = false;
ath_tid_drain(sc, txq, tid, bh_flag);
}
}
@ -2059,8 +2054,8 @@ static int ath_tx_start_dma(struct ath_softc *sc,
ath9k_hw_filltxdesc(ah,
ds,
sg_dma_len(sg), /* segment length */
AH_TRUE, /* first segment */
(n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
true, /* first segment */
(n_sg == 1) ? true : false, /* last segment */
ds); /* first descriptor */
bf->bf_lastfrm = bf;
@ -2168,7 +2163,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
"tx", nbufs * ATH_FRAG_PER_MSDU, ATH_TXDESC);
if (error != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate tx descriptors: %d\n",
__func__, error);
break;
@ -2178,7 +2173,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
"beacon", ATH_BCBUF, 1);
if (error != 0) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: failed to allocate "
"beacon descripotrs: %d\n",
__func__, error);
@ -2252,7 +2247,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
return NULL;
}
if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: hal qnum %u out of range, max %u!\n",
__func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
ath9k_hw_releasetxqueue(ah, qnum);
@ -2299,7 +2294,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
struct ath_txq *txq;
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: HAL AC %u out of range, max %zu!\n",
__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
return 0;
@ -2319,7 +2314,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
switch (qtype) {
case HAL_TX_QUEUE_DATA:
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: HAL AC %u out of range, max %zu!\n",
__func__,
haltype, ARRAY_SIZE(sc->sc_haltype2q));
@ -2367,7 +2362,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
qi.tqi_readyTime = qi0->tqi_readyTime;
if (!ath9k_hw_settxqueueprops(ah, qnum, &qi)) {
DPRINTF(sc, ATH_DEBUG_FATAL,
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to update hardware queue %u!\n",
__func__, qnum);
error = -EIO;
@ -2445,7 +2440,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
}
void ath_tx_draintxq(struct ath_softc *sc,
struct ath_txq *txq, enum hal_bool retry_tx)
struct ath_txq *txq, bool retry_tx)
{
struct ath_buf *bf, *lastbf;
struct list_head bf_head;
@ -2480,7 +2475,8 @@ void ath_tx_draintxq(struct ath_softc *sc,
lastbf = bf->bf_lastbf;
if (!retry_tx)
lastbf->bf_desc->ds_txstat.ts_flags = HAL_TX_SW_ABORTED;
lastbf->bf_desc->ds_txstat.ts_flags =
ATH9K_TX_SW_ABORTED;
/* remove ath_buf's of the same mpdu from txq */
list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
@ -2507,13 +2503,13 @@ void ath_tx_draintxq(struct ath_softc *sc,
/* Drain the transmit queues and reclaim resources */
void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx)
void ath_draintxq(struct ath_softc *sc, bool retry_tx)
{
/* stop beacon queue. The beacon will be freed when
* we go to INIT state */
if (!sc->sc_invalid) {
(void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: beacon queue %x\n", __func__,
DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
}
@ -2579,7 +2575,7 @@ int ath_tx_aggr_start(struct ath_softc *sc,
spin_unlock_bh(&sc->node_lock);
if (!an) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: Node not found to initialize "
"TX aggregation\n", __func__);
return -1;
@ -2607,7 +2603,7 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
spin_unlock_bh(&sc->node_lock);
if (!an) {
DPRINTF(sc, ATH_DEBUG_AGGR,
DPRINTF(sc, ATH_DBG_AGGR,
"%s: TX aggr stop for non-existent node\n", __func__);
return -1;
}
@ -2632,7 +2628,7 @@ void ath_tx_aggr_teardown(struct ath_softc *sc,
struct list_head bf_head;
INIT_LIST_HEAD(&bf_head);
DPRINTF(sc, ATH_DEBUG_AGGR, "%s: teardown TX aggregation\n", __func__);
DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
if (txtid->cleanup_inprogress) /* cleanup is in progress */
return;
@ -2667,7 +2663,7 @@ void ath_tx_aggr_teardown(struct ath_softc *sc,
if (txtid->baw_head != txtid->baw_tail) {
spin_unlock_bh(&txq->axq_lock);
txtid->cleanup_inprogress = AH_TRUE;
txtid->cleanup_inprogress = true;
} else {
txtid->addba_exchangecomplete = 0;
txtid->addba_exchangeattempts = 0;
@ -2694,7 +2690,7 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
*/
ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
list_del(&ac->list);
ac->sched = AH_FALSE;
ac->sched = false;
/*
* process a single tid per destination
@ -2706,7 +2702,7 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
list_del(&tid->list);
tid->sched = AH_FALSE;
tid->sched = false;
if (tid->paused) /* check next tid to keep h/w busy */
continue;
@ -2734,8 +2730,8 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
/*
* add dest ac to txq if not already added
*/
if (ac->sched == AH_FALSE) {
ac->sched = AH_TRUE;
if (!ac->sched) {
ac->sched = true;
list_add_tail(&ac->list, &txq->axq_acq);
}
}
@ -2763,9 +2759,9 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
tid->seq_start = tid->seq_next = 0;
tid->baw_size = WME_MAX_BA;
tid->baw_head = tid->baw_tail = 0;
tid->sched = AH_FALSE;
tid->paused = AH_FALSE;
tid->cleanup_inprogress = AH_FALSE;
tid->sched = false;
tid->paused = false;
tid->cleanup_inprogress = false;
INIT_LIST_HEAD(&tid->buf_q);
acno = TID_TO_WME_AC(tidno);
@ -2782,7 +2778,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
*/
for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
acno < WME_NUM_AC; acno++, ac++) {
ac->sched = AH_FALSE;
ac->sched = false;
INIT_LIST_HEAD(&ac->tid_q);
switch (acno) {
@ -2832,16 +2828,16 @@ void ath_tx_node_cleanup(struct ath_softc *sc,
if (tid && tid->an != an)
continue;
list_del(&ac->list);
ac->sched = AH_FALSE;
ac->sched = false;
list_for_each_entry_safe(tid,
tid_tmp, &ac->tid_q, list) {
list_del(&tid->list);
tid->sched = AH_FALSE;
tid->sched = false;
ath_tid_drain(sc, txq, tid, bh_flag);
tid->addba_exchangecomplete = 0;
tid->addba_exchangeattempts = 0;
tid->cleanup_inprogress = AH_FALSE;
tid->cleanup_inprogress = false;
}
}