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ralink: fix tx vlan offload and hardware status 

hardware status and tx vlan offload support on all targets
except rt5350. so i modify the IS_ENABLE condition only for
mt7621.
support mt7621 hardware status reference by SDK. but i don't
have mt7621. if not work just set mt7621 FE_REG_FE_COUNTER_BASE
to 0 to let software count.

Signed-off-by: michael lee <igvtee@gmail.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43303 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
John Crispin 2014-11-19 09:19:57 +00:00
parent 0f47bf20de
commit 5cd69085ed
2 changed files with 40 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c
View File

@ -353,18 +353,33 @@ void fe_stats_update(struct fe_priv *priv)
u64_stats_update_begin(&hwstats->syncp);
hwstats->tx_bytes += fe_r32(base);
hwstats->tx_packets += fe_r32(base + 0x04);
hwstats->tx_skip += fe_r32(base + 0x08);
hwstats->tx_collisions += fe_r32(base + 0x0c);
hwstats->rx_bytes += fe_r32(base + 0x20);
hwstats->rx_packets += fe_r32(base + 0x24);
hwstats->rx_overflow += fe_r32(base + 0x28);
hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
hwstats->rx_short_errors += fe_r32(base + 0x30);
hwstats->rx_long_errors += fe_r32(base + 0x34);
hwstats->rx_checksum_errors += fe_r32(base + 0x38);
hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
if (IS_ENABLED(CONFIG_SOC_MT7621)) {
hwstats->rx_bytes += fe_r32(base);
hwstats->rx_packets += fe_r32(base + 0x08);
hwstats->rx_overflow += fe_r32(base + 0x10);
hwstats->rx_fcs_errors += fe_r32(base + 0x14);
hwstats->rx_short_errors += fe_r32(base + 0x18);
hwstats->rx_long_errors += fe_r32(base + 0x1c);
hwstats->rx_checksum_errors += fe_r32(base + 0x20);
hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
hwstats->tx_skip += fe_r32(base + 0x28);
hwstats->tx_collisions += fe_r32(base + 0x2c);
hwstats->tx_bytes += fe_r32(base + 0x30);
hwstats->tx_packets += fe_r32(base + 0x38);
} else {
hwstats->tx_bytes += fe_r32(base);
hwstats->tx_packets += fe_r32(base + 0x04);
hwstats->tx_skip += fe_r32(base + 0x08);
hwstats->tx_collisions += fe_r32(base + 0x0c);
hwstats->rx_bytes += fe_r32(base + 0x20);
hwstats->rx_packets += fe_r32(base + 0x24);
hwstats->rx_overflow += fe_r32(base + 0x28);
hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
hwstats->rx_short_errors += fe_r32(base + 0x30);
hwstats->rx_long_errors += fe_r32(base + 0x34);
hwstats->rx_checksum_errors += fe_r32(base + 0x38);
hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
}
u64_stats_update_end(&hwstats->syncp);
}
@ -391,17 +406,10 @@ static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
do {
start = u64_stats_fetch_begin_bh(&hwstats->syncp);
if (IS_ENABLED(CONFIG_SOC_MT7621)) {
storage->rx_packets = dev->stats.rx_packets;
storage->tx_packets = dev->stats.tx_packets;
storage->rx_bytes = dev->stats.rx_bytes;
storage->tx_bytes = dev->stats.tx_bytes;
} else {
storage->rx_packets = dev->stats.rx_packets;
storage->tx_packets = dev->stats.tx_packets;
storage->rx_bytes = dev->stats.rx_bytes;
storage->tx_bytes = dev->stats.tx_bytes;
}
storage->rx_packets = hwstats->rx_packets;
storage->tx_packets = hwstats->tx_packets;
storage->rx_bytes = hwstats->rx_bytes;
storage->tx_bytes = hwstats->tx_bytes;
storage->collisions = hwstats->tx_collisions;
storage->rx_length_errors = hwstats->rx_short_errors +
hwstats->rx_long_errors;
@ -497,12 +505,12 @@ static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
/* VLAN header offload */
if (vlan_tx_tag_present(skb)) {
if (IS_ENABLED(CONFIG_SOC_MT7620))
if (IS_ENABLED(CONFIG_SOC_MT7621))
txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
else
txd->txd4 |= TX_DMA_INS_VLAN |
((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
(vlan_tx_tag_get(skb) & 0xF);
else
txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
}
/* TSO: fill MSS info in tcp checksum field */

7
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
View File

@ -55,6 +55,11 @@
#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
#define MT7621_REG_MIB_OFFSET 0x2000
#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
#define GSW_REG_GDMA1_MAC_ADRL 0x508
#define GSW_REG_GDMA1_MAC_ADRH 0x50C
@ -90,7 +95,7 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = {
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
};