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ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint 

256 entries is a bit excessive, even for gigabit speeds

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37762 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Felix Fietkau 2013-08-12 17:26:03 +00:00
parent 7fff30d5b9
commit 413a09f44c
1 changed files with 2 additions and 2 deletions
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4
target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
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@ -58,8 +58,8 @@
#define AG71XX_TX_RING_SIZE_DEFAULT 64
#define AG71XX_RX_RING_SIZE_DEFAULT 128
#define AG71XX_TX_RING_SIZE_MAX 256
#define AG71XX_RX_RING_SIZE_MAX 256
#define AG71XX_TX_RING_SIZE_MAX 128
#define AG71XX_RX_RING_SIZE_MAX 128
#ifdef CONFIG_AG71XX_DEBUG
#define DBG(fmt, args...) pr_debug(fmt, ## args)