ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint
256 entries is a bit excessive, even for gigabit speeds Signed-off-by: Felix Fietkau <nbd@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37762 3c298f89-4303-0410-b956-a3cf2f4a3e73master
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@ -58,8 +58,8 @@
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#define AG71XX_TX_RING_SIZE_DEFAULT 64
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#define AG71XX_TX_RING_SIZE_DEFAULT 64
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#define AG71XX_RX_RING_SIZE_DEFAULT 128
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#define AG71XX_RX_RING_SIZE_DEFAULT 128
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#define AG71XX_TX_RING_SIZE_MAX 256
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#define AG71XX_TX_RING_SIZE_MAX 128
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#define AG71XX_RX_RING_SIZE_MAX 256
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#define AG71XX_RX_RING_SIZE_MAX 128
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#ifdef CONFIG_AG71XX_DEBUG
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#ifdef CONFIG_AG71XX_DEBUG
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#define DBG(fmt, args...) pr_debug(fmt, ## args)
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#define DBG(fmt, args...) pr_debug(fmt, ## args)
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