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initial merge of danube, pci is still broken and the new dma code still needs to be tested, before the merge 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9704 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
John Crispin 2007-12-10 20:00:55 +00:00
parent 4aa4b0e463
commit 3a71807c29
26 changed files with 6384 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
target/linux/danube/Makefile Normal file
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#
# Copyright (C) 2007 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
ARCH:=mips
BOARD:=danube
BOARDNAME:=Infineon Danube
FEATURES:=squashfs jffs2 broken
LINUX_VERSION:=2.6.23
include $(INCLUDE_DIR)/target.mk
define Target/Description
Build firmware images for Infineon Danube
endef
$(eval $(call BuildTarget))

14
target/linux/danube/base-files/etc/config/network Normal file
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# Copyright (C) 2006 OpenWrt.org
config interface loopback
option ifname lo
option proto static
option ipaddr 127.0.0.1
option netmask 255.0.0.0
config interface lan
option ifname eth0
#option type bridge
option proto static
option ipaddr 192.168.45.110
option netmask 255.255.255.0

185
target/linux/danube/config-2.6.23 Normal file
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CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_8139TOO is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_ATM is not set
CONFIG_BASE_SMALL=0
CONFIG_BITREVERSE=y
# CONFIG_BT is not set
CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_DANUBE=y
CONFIG_DANUBE_ASC_UART=y
CONFIG_DANUBE_MII0=y
CONFIG_DANUBE_MII1=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
# CONFIG_HOSTAP is not set
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_I2C is not set
# CONFIG_IDE is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
CONFIG_KALLSYMS=y
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_MIPS=y
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD=y
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK2MTD is not set
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_CHAR=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_DANUBE=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_JEDECPROBE is not set
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_START=0x0
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_PAGE_SIZE_16KB is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_64KB is not set
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_RTC is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_DANUBE=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
# CONFIG_TC35815 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_TRAD_SIGNALS=y
# CONFIG_USBPCWATCHDOG is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USER_NS is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIA_RHINE is not set
CONFIG_ZONE_DMA_FLAG=0

16
target/linux/danube/files/arch/mips/danube/Kconfig Normal file
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# copyright 2007 john crispin <blogic@openwrt.org>
menu "Danube built-in"
config DANUBE_ASC_UART
bool "Danube asc uart"
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
default y
config MTD_DANUBE
bool "Danube flash map"
default y
endmenu

10
target/linux/danube/files/arch/mips/danube/Makefile Normal file
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#
# Copyright 2007 openwrt.org
# John Crispin <blogic@openwrt.org>
#
# Makefile for Infineon Danube
#
obj-y := reset.o prom.o setup.o interrupt.o dma-core.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += kgdb_serial.o

757
target/linux/danube/files/arch/mips/danube/dma-core.c Normal file
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#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/stat.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/selection.h>
#include <linux/kmod.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_irq.h>
#include <asm/danube/danube_dma.h>
/*25 descriptors for each dma channel,4096/8/20=25.xx*/
#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
extern void mask_and_ack_danube_irq (unsigned int irq_nr);
extern void enable_danube_irq (unsigned int irq_nr);
extern void disable_danube_irq (unsigned int irq_nr);
u64 *g_desc_list;
_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
_dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
char global_device_name[MAX_DMA_DEVICE_NUM][20] =
{ {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} };
_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
{"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
{"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
{"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
{"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
{"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
{"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
{"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
{"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
{"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
{"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
{"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
{"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
{"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
{"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
{"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
{"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
{"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
{"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
{"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
};
_dma_chan_map *chan_map = default_dma_map;
volatile u32 g_danube_dma_int_status = 0;
volatile int g_danube_dma_in_process = 0;/*0=not in process,1=in process*/
void do_dma_tasklet (unsigned long);
DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0);
u8*
common_buffer_alloc (int len, int *byte_offset, void **opt)
{
u8 *buffer = (u8 *) kmalloc (len * sizeof (u8), GFP_KERNEL);
*byte_offset = 0;
return buffer;
}
void
common_buffer_free (u8 *dataptr, void *opt)
{
if (dataptr)
kfree(dataptr);
}
void
enable_ch_irq (_dma_channel_info *pCh)
{
int chan_no = (int)(pCh - dma_chan);
int flag;
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(0x4a, DANUBE_DMA_CIE);
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
local_irq_restore(flag);
enable_danube_irq(pCh->irq);
}
void
disable_ch_irq (_dma_channel_info *pCh)
{
int flag;
int chan_no = (int) (pCh - dma_chan);
local_irq_save(flag);
g_danube_dma_int_status &= ~(1 << chan_no);
writel(chan_no, DANUBE_DMA_CS);
writel(0, DANUBE_DMA_CIE);
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_danube_irq(pCh->irq);
}
void
open_chan (_dma_channel_info *pCh)
{
int flag;
int chan_no = (int)(pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL);
if(pCh->dir == DANUBE_DMA_RX)
enable_ch_irq(pCh);
local_irq_restore(flag);
}
void
close_chan(_dma_channel_info *pCh)
{
int flag;
int chan_no = (int) (pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
disable_ch_irq(pCh);
local_irq_restore(flag);
}
void
reset_chan (_dma_channel_info *pCh)
{
int chan_no = (int) (pCh - dma_chan);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
}
void
rx_chan_intr_handler (int chan_no)
{
_dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev;
_dma_channel_info *pCh = &dma_chan[chan_no];
struct rx_desc *rx_desc_p;
int tmp;
int flag;
/*handle command complete interrupt */
rx_desc_p = (struct rx_desc*)pCh->desc_base + pCh->curr_desc;
if (rx_desc_p->status.field.OWN == CPU_OWN
&& rx_desc_p->status.field.C
&& rx_desc_p->status.field.data_length < 1536){
/*Every thing is correct, then we inform the upper layer */
pDev->current_rx_chan = pCh->rel_chan_no;
if(pDev->intr_handler)
pDev->intr_handler(pDev, RCV_INT);
pCh->weight--;
} else {
local_irq_save(flag);
tmp = readl(DANUBE_DMA_CS);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
writel(tmp, DANUBE_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
}
}
inline void
tx_chan_intr_handler (int chan_no)
{
_dma_device_info *pDev = (_dma_device_info*)dma_chan[chan_no].dma_dev;
_dma_channel_info *pCh = &dma_chan[chan_no];
int tmp;
int flag;
local_irq_save(flag);
tmp = readl(DANUBE_DMA_CS);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
writel(tmp, DANUBE_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
pDev->current_tx_chan = pCh->rel_chan_no;
if (pDev->intr_handler)
pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
}
void
do_dma_tasklet (unsigned long unused)
{
int i;
int chan_no = 0;
int budget = DMA_INT_BUDGET;
int weight = 0;
int flag;
while (g_danube_dma_int_status)
{
if (budget-- < 0)
{
tasklet_schedule(&dma_tasklet);
return;
}
chan_no = -1;
weight = 0;
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
if ((g_danube_dma_int_status & (1 << i)) && dma_chan[i].weight > 0)
{
if (dma_chan[i].weight > weight)
{
chan_no = i;
weight = dma_chan[chan_no].weight;
}
}
}
if (chan_no >= 0)
{
if (chan_map[chan_no].dir == DANUBE_DMA_RX)
rx_chan_intr_handler(chan_no);
else
tx_chan_intr_handler(chan_no);
} else {
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
dma_chan[i].weight = dma_chan[i].default_weight;
}
}
}
local_irq_save(flag);
g_danube_dma_in_process = 0;
if (g_danube_dma_int_status)
{
g_danube_dma_in_process = 1;
tasklet_schedule(&dma_tasklet);
}
local_irq_restore(flag);
}
irqreturn_t
dma_interrupt (int irq, void *dev_id)
{
_dma_channel_info *pCh;
int chan_no = 0;
int tmp;
pCh = (_dma_channel_info*)dev_id;
chan_no = (int)(pCh - dma_chan);
if (chan_no < 0 || chan_no > 19)
BUG();
tmp = readl(DANUBE_DMA_IRNEN);
writel(0, DANUBE_DMA_IRNEN);
g_danube_dma_int_status |= 1 << chan_no;
writel(tmp, DANUBE_DMA_IRNEN);
mask_and_ack_danube_irq(irq);
if (!g_danube_dma_in_process)
{
g_danube_dma_in_process = 1;
tasklet_schedule(&dma_tasklet);
}
return IRQ_HANDLED;
}
_dma_device_info*
dma_device_reserve (char *dev_name)
{
int i;
for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
{
if (strcmp(dev_name, dma_devs[i].device_name) == 0)
{
if (dma_devs[i].reserved)
return NULL;
dma_devs[i].reserved = 1;
break;
}
}
return &dma_devs[i];
}
void
dma_device_release (_dma_device_info *dev)
{
dev->reserved = 0;
}
void
dma_device_register(_dma_device_info *dev)
{
int i, j;
int chan_no = 0;
u8 *buffer;
int byte_offset;
int flag;
_dma_device_info *pDev;
_dma_channel_info *pCh;
struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p;
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
for (j = 0; j < pCh->desc_len; j++)
{
tx_desc_p = (struct tx_desc*)pCh->desc_base + j;
memset(tx_desc_p, 0, sizeof(struct tx_desc));
}
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
/*check if the descriptor length is changed */
if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, DANUBE_DMA_CDLEN);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 2){};
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
writel(0x30100, DANUBE_DMA_CCTRL); /*reset and enable channel,enable channel later */
local_irq_restore(flag);
}
}
for (i = 0; i < dev->max_rx_chan_num; i++)
{
pCh = dev->rx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
for (j = 0; j < pCh->desc_len; j++)
{
rx_desc_p = (struct rx_desc*)pCh->desc_base + j;
pDev = (_dma_device_info*)(pCh->dma_dev);
buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void*)&(pCh->opt[j]));
if (!buffer)
break;
dma_cache_inv((unsigned long) buffer, pCh->packet_size);
rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
rx_desc_p->status.word = 0;
rx_desc_p->status.field.byte_offset = byte_offset;
rx_desc_p->status.field.OWN = DMA_OWN;
rx_desc_p->status.field.data_length = pCh->packet_size;
}
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
/*check if the descriptor length is changed */
if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, DANUBE_DMA_CDLEN);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 2){};
writel(0x0a, DANUBE_DMA_CIE); /*fix me, should enable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
writel(0x30000, DANUBE_DMA_CCTRL);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
}
}
}
void
dma_device_unregister (_dma_device_info *dev)
{
int i, j;
int chan_no;
_dma_channel_info *pCh;
struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p;
int flag;
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
{
chan_no = (int)(dev->tx_chan[i] - dma_chan);
local_irq_save (flag);
writel(chan_no, DANUBE_DMA_CS);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
pCh->control = DANUBE_DMA_CH_OFF;
writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
{
tx_desc_p = (struct tx_desc*)pCh->desc_base + j;
if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
|| (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0))
{
dev->buffer_free ((u8 *) __va (tx_desc_p->Data_Pointer), (void*)pCh->opt[j]);
}
tx_desc_p->status.field.OWN = CPU_OWN;
memset (tx_desc_p, 0, sizeof (struct tx_desc));
}
//TODO should free buffer that is not transferred by dma
}
}
for (i = 0; i < dev->max_rx_chan_num; i++)
{
pCh = dev->rx_chan[i];
chan_no = (int)(dev->rx_chan[i] - dma_chan);
disable_danube_irq(pCh->irq);
local_irq_save(flag);
g_danube_dma_int_status &= ~(1 << chan_no);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
pCh->control = DANUBE_DMA_CH_OFF;
writel(chan_no, DANUBE_DMA_CS);
writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
{
rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
if ((rx_desc_p->status.field.OWN == CPU_OWN
&& rx_desc_p->status.field.C)
|| (rx_desc_p->status.field.OWN == DMA_OWN
&& rx_desc_p->status.field.data_length > 0)) {
dev->buffer_free ((u8 *)
__va (rx_desc_p->
Data_Pointer),
(void *) pCh->opt[j]);
}
}
}
}
int
dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt)
{
u8 *buf;
int len;
int byte_offset = 0;
void *p = NULL;
_dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
struct rx_desc *rx_desc_p;
/*get the rx data first */
rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
{
return 0;
}
buf = (u8 *) __va (rx_desc_p->Data_Pointer);
*(u32*)dataptr = (u32)buf;
len = rx_desc_p->status.field.data_length;
if (opt)
{
*(int*)opt = (int)pCh->opt[pCh->curr_desc];
}
/*replace with a new allocated buffer */
buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
if (buf)
{
dma_cache_inv ((unsigned long) buf,
pCh->packet_size);
pCh->opt[pCh->curr_desc] = p;
wmb ();
rx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) buf);
rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
wmb ();
} else {
*(u32 *) dataptr = 0;
if (opt)
*(int *) opt = 0;
len = 0;
}
/*increase the curr_desc pointer */
pCh->curr_desc++;
if (pCh->curr_desc == pCh->desc_len)
pCh->curr_desc = 0;
return len;
}
int
dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt)
{
int flag;
u32 tmp, byte_offset;
_dma_channel_info *pCh;
int chan_no;
struct tx_desc *tx_desc_p;
local_irq_save (flag);
pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
chan_no = (int)(pCh - (_dma_channel_info *) dma_chan);
tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc;
while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
{
dma_dev->buffer_free((u8 *) __va (tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
memset(tx_desc_p, 0, sizeof (struct tx_desc));
pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc;
}
tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->curr_desc;
/*Check whether this descriptor is available */
if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C)
{
/*if not , the tell the upper layer device */
dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
local_irq_restore(flag);
printk (KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
return 0;
}
pCh->opt[pCh->curr_desc] = opt;
/*byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
byte_offset = ((u32) CPHYSADDR ((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
dma_cache_wback ((unsigned long) dataptr, len);
wmb ();
tx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) dataptr) - byte_offset;
wmb ();
tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
wmb ();
pCh->curr_desc++;
if (pCh->curr_desc == pCh->desc_len)
pCh->curr_desc = 0;
/*Check whether this descriptor is available */
tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
if (tx_desc_p->status.field.OWN == DMA_OWN)
{
/*if not , the tell the upper layer device */
dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
}
writel(chan_no, DANUBE_DMA_CS);
tmp = readl(DANUBE_DMA_CCTRL);
if (!(tmp & 1))
pCh->open (pCh);
local_irq_restore (flag);
return len;
}
int
map_dma_chan(_dma_chan_map *map)
{
int i, j;
int result;
for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
{
strcpy(dma_devs[i].device_name, global_device_name[i]);
}
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
dma_chan[i].irq = map[i].irq;
result = request_irq(dma_chan[i].irq, dma_interrupt, SA_INTERRUPT, "dma-core", (void*)&dma_chan[i]);
if (result)
{
printk("error, cannot get dma_irq!\n");
free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
return -EFAULT;
}
}
for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
{
dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
dma_devs[i].max_rx_chan_num = 0;
dma_devs[i].max_tx_chan_num = 0;
dma_devs[i].buffer_alloc = &common_buffer_alloc;
dma_devs[i].buffer_free = &common_buffer_free;
dma_devs[i].intr_handler = NULL;
dma_devs[i].tx_burst_len = 4;
dma_devs[i].rx_burst_len = 4;
if (i == 0)
{
writel(0, DANUBE_DMA_PS);
writel(readl(DANUBE_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), DANUBE_DMA_PCTRL); /*enable dma drop */
}
if (i == 1)
{
writel(1, DANUBE_DMA_PS);
writel(0x14, DANUBE_DMA_PCTRL); /*deu port setting */
}
for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
{
dma_chan[j].byte_offset = 0;
dma_chan[j].open = &open_chan;
dma_chan[j].close = &close_chan;
dma_chan[j].reset = &reset_chan;
dma_chan[j].enable_irq = &enable_ch_irq;
dma_chan[j].disable_irq = &disable_ch_irq;
dma_chan[j].rel_chan_no = map[j].rel_chan_no;
dma_chan[j].control = DANUBE_DMA_CH_OFF;
dma_chan[j].default_weight = DANUBE_DMA_CH_DEFAULT_WEIGHT;
dma_chan[j].weight = dma_chan[j].default_weight;
dma_chan[j].curr_desc = 0;
dma_chan[j].prev_desc = 0;
}
for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
{
if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0)
{
if (map[j].dir == DANUBE_DMA_RX)
{
dma_chan[j].dir = DANUBE_DMA_RX;
dma_devs[i].max_rx_chan_num++;
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
dma_chan[j].dma_dev = (void*)&dma_devs[i];
} else if(map[j].dir == DANUBE_DMA_TX)
{ /*TX direction */
dma_chan[j].dir = DANUBE_DMA_TX;
dma_devs[i].max_tx_chan_num++;
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
dma_chan[j].dma_dev = (void*)&dma_devs[i];
} else {
printk ("WRONG DMA MAP!\n");
}
}
}
}
return 0;
}
void
dma_chip_init(void)
{
int i;
// enable DMA from PMU
writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_DMA, DANUBE_PMU_PWDCR);
// reset DMA
writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
// diable all interrupts
writel(0, DANUBE_DMA_IRNEN);
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
writel(i, DANUBE_DMA_CS);
writel(0x2, DANUBE_DMA_CCTRL);
writel(0x80000040, DANUBE_DMA_CPOLL);
writel(readl(DANUBE_DMA_CCTRL) & ~0x1, DANUBE_DMA_CCTRL);
}
}
int
danube_dma_init (void)
{
int i;
dma_chip_init();
if (map_dma_chan(default_dma_map))
BUG();
g_desc_list = (u64*)KSEG1ADDR(__get_free_page(GFP_DMA));
if (g_desc_list == NULL)
{
printk("no memory for desriptor\n");
return -ENOMEM;
}
memset(g_desc_list, 0, PAGE_SIZE);
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8;
dma_chan[i].curr_desc = 0;
dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET;
writel(i, DANUBE_DMA_CS);
writel((u32)CPHYSADDR(dma_chan[i].desc_base), DANUBE_DMA_CDBA);
writel(dma_chan[i].desc_len, DANUBE_DMA_CDLEN);
}
return 0;
}
arch_initcall(danube_dma_init);
void
dma_cleanup(void)
{
int i;
free_page(KSEG0ADDR((unsigned long) g_desc_list));
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
free_irq(dma_chan[i].irq, (void*)&dma_interrupt);
}
EXPORT_SYMBOL (dma_device_reserve);
EXPORT_SYMBOL (dma_device_release);
EXPORT_SYMBOL (dma_device_register);
EXPORT_SYMBOL (dma_device_unregister);
EXPORT_SYMBOL (dma_device_read);
EXPORT_SYMBOL (dma_device_write);
MODULE_LICENSE ("GPL");

219
target/linux/danube/files/arch/mips/danube/interrupt.c Normal file
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/*
* arch/mips/danube/interrupt.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon Danube code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_irq.h>
#include <asm/irq_cpu.h>
void
disable_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET){
writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (disable_danube_irq);
void
mask_and_ack_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
u32 *danube_isr = DANUBE_ICU_IM0_ISR;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET)
{
writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
writel((1 << irq_nr ), danube_isr);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
danube_isr += DANUBE_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (mask_and_ack_danube_irq);
void
enable_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET)
{
writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (enable_danube_irq);
static unsigned int
startup_danube_irq (unsigned int irq)
{
enable_danube_irq (irq);
return 0;
}
static void
end_danube_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_danube_irq (irq);
}
static struct hw_interrupt_type danube_irq_type = {
"DANUBE",
.startup = startup_danube_irq,
.enable = enable_danube_irq,
.disable = disable_danube_irq,
.unmask = enable_danube_irq,
.ack = end_danube_irq,
.mask = disable_danube_irq,
.mask_ack = mask_and_ack_danube_irq,
.end = end_danube_irq,
};
static inline int
ls1bit32(unsigned long x)
{
__asm__ (
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
return 31 - x;
}
void
danube_hw_irqdispatch (int module)
{
u32 irq;
irq = readl(DANUBE_ICU_IM0_IOSR + (module * DANUBE_ICU_OFFSET));
if (irq == 0)
return;
irq = ls1bit32 (irq);
do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
if ((irq == 22) && (module == 0)){
writel(readl(DANUBE_EBU_PCC_ISTAT) | 0x10, DANUBE_EBU_PCC_ISTAT);
}
}
asmlinkage void
plat_irq_dispatch (void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
unsigned int i;
if (pending & CAUSEF_IP7){
do_IRQ(MIPS_CPU_TIMER_IRQ);
goto out;
} else {
for (i = 0; i < 5; i++)
{
if (pending & (CAUSEF_IP2 << i))
{
danube_hw_irqdispatch(i);
goto out;
}
}
}
printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
out:
return;
}
static struct irqaction cascade = {
.handler = no_action,
.flags = IRQF_DISABLED,
.name = "cascade",
};
void __init
arch_init_irq(void)
{
int i;
for (i = 0; i < 5; i++)
{
writel(0, DANUBE_ICU_IM0_IER + (i * DANUBE_ICU_OFFSET));
}
mips_cpu_irq_init();
for (i = 2; i <= 6; i++)
{
setup_irq(i, &cascade);
}
for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
{
#if 0
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
#endif
set_irq_chip_and_handler(i, &danube_irq_type, handle_level_irq);
}
set_c0_status (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
}

304
target/linux/danube/files/arch/mips/danube/pci.c Normal file
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#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_irq.h>
#include <asm/addrspace.h>
#include <linux/vmalloc.h>
#define DANUBE_PCI_MEM_BASE 0x18000000
#define DANUBE_PCI_MEM_SIZE 0x02000000
#define DANUBE_PCI_IO_BASE 0x1AE00000
#define DANUBE_PCI_IO_SIZE 0x00200000
#define DANUBE_PCI_CFG_BUSNUM_SHF 16
#define DANUBE_PCI_CFG_DEVNUM_SHF 11
#define DANUBE_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
struct pci_ops danube_pci_ops = {
.read = danube_pci_read_config_dword,
.write = danube_pci_write_config_dword
};
static struct resource pci_io_resource = {
.name = "io pci IO space",
.start = DANUBE_PCI_IO_BASE,
.end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
.start = DANUBE_PCI_MEM_BASE,
.end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
static struct pci_controller danube_pci_controller = {
.pci_ops = &danube_pci_ops,
.mem_resource = &pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &pci_io_resource,
.io_offset = 0x00000000UL,
};
static u32 danube_pci_mapped_cfg;
static int
danube_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
{
unsigned long cfg_base;
unsigned long flags;
u32 temp;
/* Danube support slot from 0 to 15 */
/* dev_fn 0&0x68 (AD29) is danube itself */
if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
return 1;
local_irq_save(flags);
cfg_base = danube_pci_mapped_cfg;
cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
/* Perform access */
if (access_type == PCI_ACCESS_WRITE)
{
writel(*data, ((u32*)cfg_base));
} else {
*data = readl(((u32*)(cfg_base)));
}
wmb();
/* clean possible Master abort */
cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base)));
cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base));
local_irq_restore(flags);
if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
return 1;
return 0;
}
static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
u32 data = 0;
if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
*val = (data >> ((where & 3) << 3)) & 0xff;
else if (size == 2)
*val = (data >> ((where & 3) << 3)) & 0xffff;
else
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
u32 data = 0;
if (size == 4)
{
data = val;
} else {
if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
else if (size == 2)
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
}
if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
int pcibios_plat_dev_init(struct pci_dev *dev){
u8 pin;
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
switch(pin) {
case 0:
break;
case 1:
//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
break;
case 2:
case 3:
case 4:
printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
default:
printk ("WARNING: invalid interrupt pin %d\n", pin);
return 1;
}
return 0;
}
static void __init danube_pci_startup (void){
/*initialize the first PCI device--danube itself */
u32 temp_buffer;
/*TODO: trigger reset */
writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
0 =>clock input
PADsel of PCI_CR of CGU : 1 =>From CGU
: 0 =>From pad
*/
writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
/* prepare GPIO */
/* PCI_RST: P1.5 ALT 01 */
//pliu20060613: start
writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
//pliu20060613: end
/* PCI_REQ1: P1.13 ALT 01 */
/* PCI_GNT1: P1.14 ALT 01 */
writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
/* PCI_REQ2: P1.15 ALT 10 */
/* PCI_GNT2: P1.7 ALT 10 */
/* enable auto-switching between PCI and EBU */
writel(0xa, PCI_CR_CLK_CTRL);
/* busy, i.e. configuration is not done, PCI access has to be retried */
writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
wmb ();
/* BUS Master/IO/MEM access */
writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
temp_buffer = readl(PCI_CR_PC_ARB);
/* enable external 2 PCI masters */
temp_buffer &= (~(0xf << 16));
/* enable internal arbiter */
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
/* enable internal PCI master reqest */
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
/* enable EBU reqest */
temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
/* enable all external masters request */
temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
writel(temp_buffer, PCI_CR_PC_ARB);
wmb ();
/* FPI ==> PCI MEM address mapping */
/* base: 0xb8000000 == > 0x18000000 */
/* size: 8x4M = 32M */
writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
/* FPI ==> PCI IO address mapping */
/* base: 0xbAE00000 == > 0xbAE00000 */
/* size: 2M */
writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg);
/* PCI ==> FPI address mapping */
/* base: 0x0 ==> 0x0 */
/* size: 32M */
/* BAR1 32M map to SDR address */
writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1);
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
// writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
// writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
/*use 8 dw burse length */
writel(0x303, PCI_CR_FCI_BURST_LENGTH);
writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
wmb();
writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
wmb();
mdelay (1);
writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__, __func__, __LINE__, slot, pin);
switch (slot) {
case 13:
/* IDSEL = AD29 --> USB Host Controller */
return (INT_NUM_IM1_IRL0 + 17);
case 14:
/* IDSEL = AD30 --> mini PCI connector */
//return (INT_NUM_IM1_IRL0 + 14);
return (INT_NUM_IM0_IRL0 + 22);
default:
printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
return 0;
}
}
int pcibios_init(void){
extern int pci_probe_only;
pci_probe_only = 0;
printk ("PCI: Probing PCI hardware on host bus 0.\n");
danube_pci_startup ();
// DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
register_pci_controller(&danube_pci_controller);
return 0;
}
arch_initcall(pcibios_init);

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/*
* arch/mips/danube/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon Danube code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/danube/danube.h>
static char buf[1024];
void
prom_free_prom_memory (void)
{
}
const char *
get_system_type (void)
{
return BOARD_SYSTEM_TYPE;
}
void
prom_putchar (char c)
{
while ((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n')
writel('\r', DANUBE_ASC1_TBUF);
writel(c, DANUBE_ASC1_TBUF);
}
void
prom_printf (const char * fmt, ...)
{
va_list args;
int l;
char *p, *buf_end;
va_start(args, fmt);
l = vsprintf(buf, fmt, args);
va_end(args);
buf_end = buf + l;
for (p = buf; p < buf_end; p++)
{
prom_putchar(*p);
}
}
void __init
prom_init(void)
{
mips_machgroup = MACH_GROUP_DANUBE;
mips_machtype = MACH_INFINEON_DANUBE;
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
}

66
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/*
* arch/mips/danube/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
*
* Rewrite of Infineon Danube code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>
#include <linux/pm.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/danube/danube.h>
static void
danube_machine_restart (char *command)
{
printk (KERN_NOTICE "System restart\n");
local_irq_disable ();
writel(readl(DANUBE_RCU_REQ) | DANUBE_RST_ALL, DANUBE_RCU_REQ);
for (;;);
}
static void
danube_machine_halt (void)
{
printk (KERN_NOTICE "System halted.\n");
local_irq_disable ();
for (;;);
}
static void
danube_machine_power_off (void)
{
printk (KERN_NOTICE "Please turn off the power now.\n");
local_irq_disable ();
for (;;);
}
void
danube_reboot_setup (void)
{
_machine_restart = danube_machine_restart;
_machine_halt = danube_machine_halt;
pm_power_off = danube_machine_power_off;
}

176
target/linux/danube/files/arch/mips/danube/setup.c Normal file
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/*
* arch/mips/danube/setup.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2004 peng.liu@infineon.com
*
* Rewrite of Infineon Danube code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
#include <asm/time.h>
#include <asm/traps.h>
#include <asm/cpu.h>
#include <asm/irq.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_irq.h>
static unsigned int r4k_offset; /* Amount to increment compare reg each time */
static unsigned int r4k_cur; /* What counter should be at next timer irq */
extern void danube_reboot_setup (void);
void prom_printf (const char * fmt, ...);
void
__init bus_error_init (void)
{
/* nothing yet */
}
unsigned int
danube_get_ddr_hz (void)
{
switch (readl(DANUBE_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
case 1:
return CLOCK_133M;
case 2:
return CLOCK_111M;
}
return CLOCK_83M;
}
EXPORT_SYMBOL(danube_get_ddr_hz);
unsigned int
danube_get_cpu_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
switch (readl(DANUBE_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
case 4:
return ddr_clock;
}
return ddr_clock << 1;
}
EXPORT_SYMBOL(danube_get_cpu_hz);
unsigned int
danube_get_fpi_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
if (readl(DANUBE_CGU_SYS) & 0x40)
{
return ddr_clock >> 1;
}
return ddr_clock;
}
EXPORT_SYMBOL(danube_get_fpi_hz);
unsigned int
danube_get_cpu_ver (void)
{
return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(danube_get_cpu_ver);
void
danube_time_init (void)
{
mips_hpt_frequency = danube_get_cpu_hz() / 2;
r4k_offset = mips_hpt_frequency / HZ;
printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
}
int
danube_be_handler(struct pt_regs *regs, int is_fixup)
{
/*TODO*/
printk(KERN_ERR "TODO: BUS error\n");
return MIPS_BE_FATAL;
}
/* ISR GPTU Timer 6 for high resolution timer */
static irqreturn_t
danube_timer6_interrupt(int irq, void *dev_id)
{
timer_interrupt(DANUBE_TIMER6_INT, NULL);
return IRQ_HANDLED;
}
static struct irqaction hrt_irqaction = {
.handler = danube_timer6_interrupt,
.flags = IRQF_DISABLED,
.name = "hrt",
};
void __init
plat_timer_setup (struct irqaction *irq)
{
unsigned int retval;
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
writel(readl(DANUBE_PMU_PWDCR) & ~(DANUBE_PMU_PWDCR_GPT|DANUBE_PMU_PWDCR_FPI), DANUBE_PMU_PWDCR);
writel(0x100, DANUBE_GPTU_GPT_CLC);
writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
if (retval)
{
prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
}
}
void __init
plat_mem_setup (void)
{
u32 status;
prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, danube_get_cpu_ver());
//TODO WHY ???
/* clear RE bit*/
status = read_c0_status();
status &= (~(1<<25));
write_c0_status(status);
danube_reboot_setup();
board_time_init = danube_time_init;
board_be_handler = &danube_be_handler;
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
}

194
target/linux/danube/files/drivers/mtd/maps/danube.c Normal file
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/*
* Driver for DANUBE flashmap
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <linux/init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/cfi.h>
#include <asm/danube/danube.h>
#include <linux/magic.h>
static struct map_info
danube_map = {
.name = "DANUBE_FLASH",
.bankwidth = 2,
.size = 0x400000,
};
static map_word
danube_read16 (struct map_info * map, unsigned long adr)
{
map_word temp;
adr ^= 2;
temp.x[0] = *((__u16 *) (map->virt + adr));
return temp;
}
static void
danube_write16 (struct map_info *map, map_word d, unsigned long adr)
{
adr ^= 2;
*((__u16 *) (map->virt + adr)) = d.x[0];
}
void
danube_copy_from (struct map_info *map, void *to, unsigned long from, ssize_t len)
{
u8 *p;
u8 *to_8;
from = (unsigned long) (from + map->virt);
p = (u8 *) from;
to_8 = (u8 *) to;
while(len--){
*to_8++ = *p++;
}
}
void
danube_copy_to (struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
u8 *p = (u8*) from;
u8 *to_8;
to += (unsigned long) map->virt;
to_8 = (u8*)to;
while(len--){
*p++ = *to_8++;
}
}
static struct mtd_partition
danube_partitions[4] = {
{
name:"U-Boot",
offset:0x00000000,
size:0x00020000,
},
{
name:"U-Boot-Env",
offset:0x00020000,
size:0x00010000,
},
{
name:"kernel",
offset:0x00030000,
size:0x0,
},
{
name:"rootfs",
offset:0x0,
size:0x0,
},
};
#define DANUBE_FLASH_START 0x10000000
#define DANUBE_FLASH_MAX 0x2000000
int
find_uImage_size (unsigned long start_offset){
unsigned long temp;
danube_copy_from(&danube_map, &temp, start_offset + 12, 4);
printk("kernel size is %ld \n", temp + 0x40);
return temp + 0x40;
}
int
detect_squashfs_partition (unsigned long start_offset){
unsigned long temp;
danube_copy_from(&danube_map, &temp, start_offset, 4);
return (temp == SQUASHFS_MAGIC);
}
int __init
init_danube_mtd (void)
{
struct mtd_info *danube_mtd = NULL;
struct mtd_partition *parts = NULL;
unsigned long uimage_size;
writel(0x1d7ff, DANUBE_EBU_BUSCON0);
danube_map.read = danube_read16;
danube_map.write = danube_write16;
danube_map.copy_from = danube_copy_from;
danube_map.copy_to = danube_copy_to;
danube_map.phys = DANUBE_FLASH_START;
danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
danube_map.size = DANUBE_FLASH_MAX;
if (!danube_map.virt) {
printk(KERN_WARNING "Failed to ioremap!\n");
return -EIO;
}
danube_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &danube_map);
if (!danube_mtd) {
iounmap(danube_map.virt);
printk("probing failed\n");
return -ENXIO;
}
danube_mtd->owner = THIS_MODULE;
uimage_size = find_uImage_size(danube_partitions[2].offset);
if(detect_squashfs_partition(danube_partitions[2].offset + uimage_size)){
printk("Found a squashfs following the uImage\n");
} else {
uimage_size &= ~0xffff;
uimage_size += 0x10000;
}
danube_partitions[2].size = uimage_size;
danube_partitions[3].offset = danube_partitions[2].offset + danube_partitions[2].size;
danube_partitions[3].size = ((danube_mtd->size >> 20) * 1024 * 1024) - danube_partitions[3].offset;
parts = &danube_partitions[0];
add_mtd_partitions(danube_mtd, parts, 4);
printk("Added danube flash with %dMB\n", danube_mtd->size >> 20);
return 0;
}
static void
__exit
cleanup_danube_mtd (void)
{
}
module_init (init_danube_mtd);
module_exit (cleanup_danube_mtd);
MODULE_LICENSE ("GPL");
MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");

433
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/*
* drivers/net/danube_mii0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Infineon
*
* Rewrite of Infineon Danube code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <asm/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
#include <linux/ethtool.h>
#include <asm/checksum.h>
#include <linux/init.h>
#include <asm/delay.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_mii0.h>
#include <asm/danube/danube_dma.h>
static struct net_device danube_mii0_dev;
static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
void
danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
{
u32 val = MDIO_ACC_REQUEST |
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
writel(val, DANUBE_PPE32_MDIO_ACC);
}
unsigned short
danube_read_mdio (u32 phy_addr, u32 phy_reg)
{
u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
writel(val, DANUBE_PPE32_MDIO_ACC);
while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
int
danube_switch_open (struct net_device *dev)
{
struct switch_priv* priv = (struct switch_priv*)dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
int i;
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
{
if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
}
netif_start_queue(dev);
return 0;
}
int
switch_release (struct net_device *dev){
struct switch_priv* priv = (struct switch_priv*)dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
int i;
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
netif_stop_queue(dev);
return 0;
}
int
switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
{
struct switch_priv *priv = (struct switch_priv*)dev->priv;
unsigned char* buf = NULL;
struct sk_buff *skb = NULL;
int len = 0;
len = dma_device_read(dma_dev, &buf, (void**)&skb);
if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
{
printk("packet too large %d\n",len);
goto switch_hw_receive_err_exit;
}
/* remove CRC */
len -= 4;
if (skb == NULL )
{
printk("cannot restore pointer\n");
goto switch_hw_receive_err_exit;
}
if (len > (skb->end - skb->tail))
{
printk("BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
goto switch_hw_receive_err_exit;
}
skb_put(skb, len);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb);
priv->stats.rx_packets++;
priv->stats.rx_bytes += len;
return 0;
switch_hw_receive_err_exit:
if (len == 0)
{
if(skb)
dev_kfree_skb_any(skb);
priv->stats.rx_errors++;
priv->stats.rx_dropped++;
return -EIO;
} else {
return len;
}
}
int
switch_hw_tx (char *buf, int len, struct net_device *dev)
{
int ret = 0;
struct switch_priv *priv = dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
ret = dma_device_write(dma_dev, buf, len, priv->skb);
return ret;
}
int
switch_tx (struct sk_buff *skb, struct net_device *dev)
{
int len;
char *data;
struct switch_priv *priv = dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
data = skb->data;
priv->skb = skb;
dev->trans_start = jiffies;
// TODO we got more than 1 dma channel, so we should do something intelligent
// here to select one
dma_dev->current_tx_chan = 0;
wmb();
if (switch_hw_tx(data, len, dev) != len)
{
dev_kfree_skb_any(skb);
priv->stats.tx_errors++;
priv->stats.tx_dropped++;
} else {
priv->stats.tx_packets++;
priv->stats.tx_bytes+=len;
}
return 0;
}
void
switch_tx_timeout (struct net_device *dev)
{
int i;
struct switch_priv* priv = (struct switch_priv*)dev->priv;
priv->stats.tx_errors++;
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
}
netif_wake_queue(dev);
return;
}
int
dma_intr_handler (struct dma_device_info* dma_dev, int status)
{
int i;
switch (status)
{
case RCV_INT:
switch_hw_receive(&danube_mii0_dev, dma_dev);
break;
case TX_BUF_FULL_INT:
printk("tx buffer full\n");
netif_stop_queue(&danube_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
{
if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
}
break;
case TRANSMIT_CPT_INT:
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
netif_wake_queue(&danube_mii0_dev);
break;
}
return 0;
}
unsigned char*
danube_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
{
unsigned char *buffer = NULL;
struct sk_buff *skb = NULL;
skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
if (skb == NULL)
return NULL;
buffer = (unsigned char*)(skb->data);
skb_reserve(skb, 2);
*(int*)opt = (int)skb;
*byte_offset = 2;
return buffer;
}
void
danube_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
{
struct sk_buff *skb = NULL;
if(opt == NULL)
{
kfree(dataptr);
} else {
skb = (struct sk_buff*)opt;
dev_kfree_skb_any(skb);
}
}
static struct net_device_stats*
danube_get_stats (struct net_device *dev)
{
return (struct net_device_stats *)dev->priv;
}
static int
switch_init (struct net_device *dev)
{
u64 retval = 0;
int i;
struct switch_priv *priv;
ether_setup(dev);
printk("%s up\n", dev->name);
dev->open = danube_switch_open;
dev->stop = switch_release;
dev->hard_start_xmit = switch_tx;
dev->get_stats = danube_get_stats;
dev->tx_timeout = switch_tx_timeout;
dev->watchdog_timeo = 10 * HZ;
dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
if (dev->priv == NULL)
return -ENOMEM;
memset(dev->priv, 0, sizeof(struct switch_priv));
priv = dev->priv;
priv->dma_device = dma_device_reserve("PPE");
if (!priv->dma_device){
BUG();
return -ENODEV;
}
priv->dma_device->buffer_alloc = &danube_etop_dma_buffer_alloc;
priv->dma_device->buffer_free = &danube_etop_dma_buffer_free;
priv->dma_device->intr_handler = &dma_intr_handler;
priv->dma_device->max_rx_chan_num = 4;
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
{
priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
}
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
if(i == 0)
priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
else
priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
}
dma_device_register(priv->dma_device);
/*read the mac address from the mac table and put them into the mac table.*/
for (i = 0; i < 6; i++)
{
retval += u_boot_ethaddr[i];
}
//TODO
/* ethaddr not set in u-boot ? */
if (retval == 0)
{
printk("use default MAC address\n");
dev->dev_addr[0] = 0x00;
dev->dev_addr[1] = 0x11;
dev->dev_addr[2] = 0x22;
dev->dev_addr[3] = 0x33;
dev->dev_addr[4] = 0x44;
dev->dev_addr[5] = 0x55;
} else {
for (i = 0; i < 6; i++)
dev->dev_addr[i] = u_boot_ethaddr[i];
}
return 0;
}
static void
danube_sw_chip_init (int mode)
{
writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_DMA, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_PPE, DANUBE_PMU_PWDCR);
wmb();
if(mode == REV_MII_MODE)
writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
else if(mode == MII_MODE)
writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
wmb();
}
int __init
switch_init_module(void)
{
int result = 0;
danube_mii0_dev.init = switch_init;
strcpy(danube_mii0_dev.name, "eth%d");
SET_MODULE_OWNER(dev);
result = register_netdev(&danube_mii0_dev);
if (result)
{
printk("error %i registering device \"%s\"\n", result, danube_mii0_dev.name);
goto out;
}
/* danube eval kit connects the phy/switch in REV mode */
danube_sw_chip_init(REV_MII_MODE);
printk("danube MAC driver loaded!\n");
out:
return result;
}
static void __exit
switch_cleanup(void)
{
struct switch_priv *priv = (struct switch_priv*)danube_mii0_dev.priv;
printk("danube_mii0 cleanup\n");
dma_device_unregister(priv->dma_device);
dma_device_release(priv->dma_device);
kfree(priv->dma_device);
kfree(danube_mii0_dev.priv);
unregister_netdev(&danube_mii0_dev);
return;
}
module_init(switch_init_module);
module_exit(switch_cleanup);

608
target/linux/danube/files/drivers/serial/danube_asc.c Normal file
View File

@ -0,0 +1,608 @@
/*
* Driver for DANUBEASC serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2004 Infineon IFAP DC COM CPE
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/bitops.h>
#include <asm/danube/danube.h>
#include <asm/danube/danube_irq.h>
#include <asm/danube/danube_serial.h>
#define PORT_DANUBEASC 111
#include <linux/serial_core.h>
#define UART_DUMMY_UER_RX 1
static void danubeasc_tx_chars(struct uart_port *port);
extern void prom_printf(const char * fmt, ...);
static struct uart_port danubeasc_port;
static struct uart_driver danubeasc_reg;
static unsigned int uartclk = 0;
extern unsigned int danube_get_fpi_hz(void);
static void
danubeasc_stop_tx (struct uart_port *port)
{
/* fifo underrun shuts up after firing once */
return;
}
static void
danubeasc_start_tx (struct uart_port *port)
{
unsigned long flags;
local_irq_save(flags);
danubeasc_tx_chars(port);
local_irq_restore(flags);
return;
}
static void
danubeasc_stop_rx (struct uart_port *port)
{
/* clear the RX enable bit */
writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
}
static void
danubeasc_enable_ms (struct uart_port *port)
{
/* no modem signals */
return;
}
static void
danubeasc_rx_chars (struct uart_port *port)
{
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
ch = readl(DANUBE_ASC1_RBUF);
rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
/*
* Note that the error handling code is
* out of the main execution path
*/
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
}
rsr &= port->read_status_mask;
if (rsr & ASCSTATE_PE)
flag = TTY_PARITY;
else if (rsr & ASCSTATE_FE)
flag = TTY_FRAME;
}
if ((rsr & port->ignore_status_mask) == 0)
tty_insert_flip_char(tty, ch, flag);
if (rsr & ASCSTATE_ROE)
/*
* Overrun is special, since it's reported
* immediately, and doesn't affect the current
* character
*/
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}
if (ch != 0)
tty_flip_buffer_push(tty);
return;
}
static void
danubeasc_tx_chars (struct uart_port *port)
{
struct circ_buf *xmit = &port->info->xmit;
if (uart_tx_stopped(port)) {
danubeasc_stop_tx(port);
return;
}
while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
{
if (port->x_char) {
writel(port->x_char, DANUBE_ASC1_TBUF);
port->icount.tx++;
port->x_char = 0;
continue;
}
if (uart_circ_empty(xmit))
break;
writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static irqreturn_t
danubeasc_tx_int (int irq, void *port)
{
writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
danubeasc_start_tx(port);
mask_and_ack_danube_irq(irq);
return IRQ_HANDLED;
}
static irqreturn_t
danubeasc_er_int (int irq, void *port)
{
/* clear any pending interrupts */
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
return IRQ_HANDLED;
}
static irqreturn_t
danubeasc_rx_int (int irq, void *port)
{
writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
danubeasc_rx_chars((struct uart_port *) port);
mask_and_ack_danube_irq(irq);
return IRQ_HANDLED;
}
static unsigned int
danubeasc_tx_empty (struct uart_port *port)
{
int status;
status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
static unsigned int
danubeasc_get_mctrl (struct uart_port *port)
{
return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
}
static void
danubeasc_set_mctrl (struct uart_port *port, u_int mctrl)
{
return;
}
static void
danubeasc_break_ctl (struct uart_port *port, int break_state)
{
return;
}
static void
danubeasc1_hw_init (void)
{
/* this setup was probably already done in ROM/u-boot but we do it again*/
/* TODO: GPIO pins are multifunction */
writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
writel(0, DANUBE_ASC1_PISEL);
writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
wmb ();
/*framing, overrun, enable */
writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
DANUBE_ASC1_CON);
}
static int
danubeasc_startup (struct uart_port *port)
{
unsigned long flags;
int retval;
/* this assumes: CON.BRS = CON.FDE = 0 */
if (uartclk == 0)
uartclk = danube_get_fpi_hz();
danubeasc_port.uartclk = uartclk;
danubeasc1_hw_init();
local_irq_save(flags);
retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
if (retval){
printk("failed to request danubeasc_rx_int\n");
return retval;
}
retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
if (retval){
printk("failed to request danubeasc_tx_int\n");
goto err1;
}
retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
if (retval){
printk("failed to request danubeasc_er_int\n");
goto err2;
}
writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
DANUBE_ASC1_IRNREN);
local_irq_restore(flags);
return 0;
err2:
free_irq(DANUBEASC1_TIR, port);
err1:
free_irq(DANUBEASC1_RIR, port);
local_irq_restore(flags);
return retval;
}
static void
danubeasc_shutdown (struct uart_port *port)
{
free_irq(DANUBEASC1_RIR, port);
free_irq(DANUBEASC1_TIR, port);
free_irq(DANUBEASC1_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
writel(0, DANUBE_ASC1_CON);
/* flush and then disable the fifos */
writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
}
static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
{
unsigned int cflag;
unsigned int iflag;
unsigned int quot;
unsigned int baud;
unsigned int con = 0;
unsigned long flags;
cflag = new->c_cflag;
iflag = new->c_iflag;
/* byte size and parity */
switch (cflag & CSIZE) {
case CS7:
con = ASCCON_M_7ASYNC;
break;
case CS5:
case CS6:
default:
con = ASCCON_M_8ASYNC;
break;
}
if (cflag & CSTOPB)
con |= ASCCON_STP;
if (cflag & PARENB) {
if (!(cflag & PARODD))
con &= ~ASCCON_ODD;
else
con |= ASCCON_ODD;
}
port->read_status_mask = ASCSTATE_ROE;
if (iflag & INPCK)
port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
port->ignore_status_mask = 0;
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
if (iflag & IGNBRK) {
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_ROE;
}
if ((cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_UER_RX;
/* set error signals - framing, parity and overrun, enable receiver */
con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
local_irq_save(flags);
/* set up CON */
writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
quot = uart_get_divisor(port, baud);
quot = quot / 2 - 1;
/* disable the baudrate generator */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
/* make sure the fractional divider is off */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
/* set up to use divisor of 2 */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
/* now we can write the new baudrate into the register */
writel(quot, DANUBE_ASC1_BG);
/* turn the baudrate generator back on */
writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
/* enable rx */
writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
local_irq_restore(flags);
}
static const char*
danubeasc_type (struct uart_port *port)
{
return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
}
static void
danubeasc_release_port (struct uart_port *port)
{
return;
}
static int
danubeasc_request_port (struct uart_port *port)
{
return 0;
}
static void
danubeasc_config_port (struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_DANUBEASC;
danubeasc_request_port(port);
}
}
static int
danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
static struct uart_ops danubeasc_pops = {
.tx_empty = danubeasc_tx_empty,
.set_mctrl = danubeasc_set_mctrl,
.get_mctrl = danubeasc_get_mctrl,
.stop_tx = danubeasc_stop_tx,
.start_tx = danubeasc_start_tx,
.stop_rx = danubeasc_stop_rx,
.enable_ms = danubeasc_enable_ms,
.break_ctl = danubeasc_break_ctl,
.startup = danubeasc_startup,
.shutdown = danubeasc_shutdown,
.set_termios = danubeasc_set_termios,
.type = danubeasc_type,
.release_port = danubeasc_release_port,
.request_port = danubeasc_request_port,
.config_port = danubeasc_config_port,
.verify_port = danubeasc_verify_port,
};
static struct uart_port danubeasc_port = {
membase: (void *)DANUBE_ASC1_BASE_ADDR,
mapbase: DANUBE_ASC1_BASE_ADDR,
iotype: SERIAL_IO_MEM,
irq: DANUBEASC1_RIR,
uartclk: 0,
fifosize: 16,
unused: {DANUBEASC1_TIR, DANUBEASC1_EIR},
type: PORT_DANUBEASC,
ops: &danubeasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
};
static void
danubeasc_console_write (struct console *co, const char *s, u_int count)
{
int i, fifocnt;
unsigned long flags;
local_irq_save(flags);
for (i = 0; i < count; i++)
{
/* wait until the FIFO is not full */
do
{
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
if (s[i] == '\0')
{
break;
}
if (s[i] == '\n')
{
writel('\r', DANUBE_ASC1_TBUF);
do
{
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
}
writel(s[i], DANUBE_ASC1_TBUF);
}
local_irq_restore(flags);
}
static int __init
danubeasc_console_setup (struct console *co, char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (uartclk == 0)
uartclk = danube_get_fpi_hz();
co->index = 0;
port = &danubeasc_port;
danubeasc_port.uartclk = uartclk;
danubeasc_port.type = PORT_DANUBEASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);
}
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver danubeasc_reg;
static struct console danubeasc_console = {
name: "ttyS",
write: danubeasc_console_write,
device: uart_console_device,
setup: danubeasc_console_setup,
flags: CON_PRINTBUFFER,
index: -1,
data: &danubeasc_reg,
};
static int __init
danubeasc_console_init (void)
{
register_console(&danubeasc_console);
return 0;
}
console_initcall(danubeasc_console_init);
static struct uart_driver danubeasc_reg = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.nr = 1,
.cons = &danubeasc_console,
};
static int __init
danubeasc_init (void)
{
unsigned char res;
uart_register_driver(&danubeasc_reg);
res = uart_add_one_port(&danubeasc_reg, &danubeasc_port);
return res;
}
static void __exit
danubeasc_exit (void)
{
uart_unregister_driver(&danubeasc_reg);
}
module_init(danubeasc_init);
module_exit(danubeasc_exit);
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("MIPS Danube serial port driver");
MODULE_LICENSE("GPL");

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_H__
#define _DANUBE_H__
/*------------ GENERAL */
#define BOARD_SYSTEM_TYPE "DANUBE"
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
/*------------ ASC1 */
#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
/* FIFO status register */
#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */
#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */
#define ASCOPT_CSIZE 0x3
#define ASCOPT_CS7 0x1
#define ASCOPT_CS8 0x2
#define ASCOPT_PARENB 0x4
#define ASCOPT_STOPB 0x8
#define ASCOPT_PARODD 0x0
#define ASCOPT_CREAD 0x20
/* hardware modified control register */
#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */
#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
/* status register */
#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */
#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
/* clock control */
#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
#define DANUBE_ASC1_CLC_DISS 0x2
/* port input select register */
#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */
#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */
#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
/* control */
#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
/* int enable */
#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4
#define ASC_IRNREN_ERR 0x2
#define ASC_IRNREN_TX 0x1
/*------------ RCU */
#define DANUBE_RCU_BASE_ADDR 0xBF203000
/* reset request */
#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
#define DANUBE_RST_ALL 0x40000000
/*------------ MCD */
#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
/* chip id */
#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
/*------------ GPTU */
#define DANUBE_GPTU_BASE_ADDR 0xB8000300
/* clock control register */
#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */
#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */
#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */
#define DANUBE_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */
#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */
#define DANUBE_CGU_BASE_ADDR 0xBF103000
/* clock mux */
#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
#define CLOCK_111M 111111111
#define CLOCK_133M 133333333
#define CLOCK_167M 166666667
#define CLOCK_333M 333333333
/*------------ CGU */
#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
/* power down control */
#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
#define DANUBE_PMU_PWDCR_DMA 0x20
#define DANUBE_PMU_PWDCR_GPT 0x1000
#define DANUBE_PMU_PWDCR_PPE 0x2000
#define DANUBE_PMU_PWDCR_FPI 0x4000
/*------------ ICU */
#define DANUBE_ICU_BASE_ADDR 0xBF880200
#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
/*------------ ETOP */
#define DANUBE_PPE32_BASE_ADDR 0xBE180000
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
#define MII_MODE 1
#define REV_MII_MODE 2
/* mdio access */
#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
#define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000
#define MDIO_ACC_ADDR_MASK 0x1f
#define MDIO_ACC_ADDR_OFFSET 0x15
#define MDIO_ACC_REG_MASK 0xff
#define MDIO_ACC_REG_OFFSET 0x10
#define MDIO_ACC_VAL_MASK 0xffff
/* configuration */
#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe
/* packet length */
#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000
/* enet */
#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800
/*------------ DMA */
#define DANUBE_DMA_BASE_ADDR 0xBE104100
#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
/*------------ PCI */
#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
#define PCI_MASTER0_REQ_MASK_2BITS 8
#define PCI_MASTER1_REQ_MASK_2BITS 10
#define PCI_MASTER2_REQ_MASK_2BITS 12
#define INTERNAL_ARB_ENABLE_BIT 0
/*------------ GPIO */
#define DANUBE_GPIO_BASE_ADDR 0xBE100B00
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
#endif

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_DMA_H__
#define _DANUBE_DMA_H__
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
#define DANUBE_DMA_CH_ON 1
#define DANUBE_DMA_CH_OFF 0
#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
enum attr_t{
TX = 0,
RX = 1,
RESERVED = 2,
DEFAULT = 3,
};
#define DMA_OWN 1
#define CPU_OWN 0
#define DMA_MAJOR 250
#define DMA_DESC_OWN_CPU 0x0
#define DMA_DESC_OWN_DMA 0x80000000
#define DMA_DESC_CPT_SET 0x40000000
#define DMA_DESC_SOP_SET 0x20000000
#define DMA_DESC_EOP_SET 0x10000000
#define MISCFG_MASK 0x40
#define RDERR_MASK 0x20
#define CHOFF_MASK 0x10
#define DESCPT_MASK 0x8
#define DUR_MASK 0x4
#define EOP_MASK 0x2
#define DMA_DROP_MASK (1<<31)
#define DANUBE_DMA_RX -1
#define DANUBE_DMA_TX 1
typedef struct dma_chan_map {
char dev_name[15];
enum attr_t dir;
int pri;
int irq;
int rel_chan_no;
} _dma_chan_map;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct rx_desc{
u32 data_length:16;
volatile u32 reserved:7;
volatile u32 byte_offset:2;
volatile u32 Burst_length_offset:3;
volatile u32 EoP:1;
volatile u32 Res:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;
/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
}_rx_desc;
typedef struct tx_desc{
volatile u32 data_length:16;
volatile u32 reserved1:7;
volatile u32 byte_offset:5;
volatile u32 EoP:1;
volatile u32 SoP:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;//fix me:should be 28 bits here
}_tx_desc;
#else //BIG
typedef struct rx_desc{
union
{
struct
{
volatile u32 OWN:1;
volatile u32 C:1;
volatile u32 SoP:1;
volatile u32 EoP:1;
volatile u32 Burst_length_offset:3;
volatile u32 byte_offset:2;
volatile u32 reserve:7;
volatile u32 data_length:16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_rx_desc;
typedef struct tx_desc{
union
{
struct
{
volatile u32 OWN:1;
volatile u32 C:1;
volatile u32 SoP:1;
volatile u32 EoP:1;
volatile u32 byte_offset:5;
volatile u32 reserved:7;
volatile u32 data_length:16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_tx_desc;
#endif //ENDIAN
typedef struct dma_channel_info{
/*relative channel number*/
int rel_chan_no;
/*class for this channel for QoS*/
int pri;
/*specify byte_offset*/
int byte_offset;
/*direction*/
int dir;
/*irq number*/
int irq;
/*descriptor parameter*/
int desc_base;
int desc_len;
int curr_desc;
int prev_desc;/*only used if it is a tx channel*/
/*weight setting for WFQ algorithm*/
int weight;
int default_weight;
int packet_size;
int burst_len;
/*on or off of this channel*/
int control;
/**optional information for the upper layer devices*/
#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
void* opt[64];
#else
void* opt[25];
#endif
/*Pointer to the peripheral device who is using this channel*/
void* dma_dev;
/*channel operations*/
void (*open)(struct dma_channel_info* pCh);
void (*close)(struct dma_channel_info* pCh);
void (*reset)(struct dma_channel_info* pCh);
void (*enable_irq)(struct dma_channel_info* pCh);
void (*disable_irq)(struct dma_channel_info* pCh);
}_dma_channel_info;
typedef struct dma_device_info{
/*device name of this peripheral*/
char device_name[15];
int reserved;
int tx_burst_len;
int rx_burst_len;
int default_weight;
int current_tx_chan;
int current_rx_chan;
int num_tx_chan;
int num_rx_chan;
int max_rx_chan_num;
int max_tx_chan_num;
_dma_channel_info* tx_chan[20];
_dma_channel_info* rx_chan[20];
/*functions, optional*/
u8* (*buffer_alloc)(int len,int* offset, void** opt);
void (*buffer_free)(u8* dataptr, void* opt);
int (*intr_handler)(struct dma_device_info* info, int status);
void * priv; /* used by peripheral driver only */
}_dma_device_info;
_dma_device_info* dma_device_reserve(char* dev_name);
void dma_device_release(_dma_device_info* dev);
void dma_device_register(_dma_device_info* info);
void dma_device_unregister(_dma_device_info* info);
int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
#endif

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_IRQ__
#define _DANUBE_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define MIPS_CPU_TIMER_IRQ 7
#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_danube_irq (unsigned int irq_nr);
#endif

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#ifndef DANUBE_SW_H
#define DANUBE_SW_H
/******************************************************************************
**
** FILE NAME : danube_sw.h
** PROJECT : Danube
** MODULES : ETH Interface (MII0)
**
** DATE : 11 AUG 2005
** AUTHOR : Wu Qi Ming
** DESCRIPTION : ETH Interface (MII0) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 11 AUG 2005 Wu Qi Ming Initiate Version
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
#define SET_ETH_REG SIOCDEVPRIVATE+6
#define VLAN_TOOLS SIOCDEVPRIVATE+7
#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
#define SET_VLAN_COS SIOCDEVPRIVATE+9
#define SET_DSCP_COS SIOCDEVPRIVATE+10
#define ENABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+11
#define DISABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+12
#define VLAN_CLASS_FIRST SIOCDEVPRIVATE+13
#define VLAN_CLASS_SECOND SIOCDEVPRIVATE+14
#define ENABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+15
#define DISABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+16
#define PASS_UNICAST_PACKETS SIOCDEVPRIVATE+17
#define FILTER_UNICAST_PACKETS SIOCDEVPRIVATE+18
#define KEEP_BROADCAST_PACKETS SIOCDEVPRIVATE+19
#define DROP_BROADCAST_PACKETS SIOCDEVPRIVATE+20
#define KEEP_MULTICAST_PACKETS SIOCDEVPRIVATE+21
#define DROP_MULTICAST_PACKETS SIOCDEVPRIVATE+22
/*===mac table commands==*/
#define RESET_MAC_TABLE 0
#define READ_MAC_ENTRY 1
#define WRITE_MAC_ENTRY 2
#define ADD_MAC_ENTRY 3
/*====vlan commands===*/
#define CHANGE_VLAN_CTRL 0
#define READ_VLAN_ENTRY 1
#define UPDATE_VLAN_ENTRY 2
#define CLEAR_VLAN_ENTRY 3
#define RESET_VLAN_TABLE 4
#define ADD_VLAN_ENTRY 5
/*
** MDIO constants.
*/
#define MDIO_BASE_STATUS_REG 0x1
#define MDIO_BASE_CONTROL_REG 0x0
#define MDIO_PHY_ID_HIGH_REG 0x2
#define MDIO_PHY_ID_LOW_REG 0x3
#define MDIO_BC_NEGOTIATE 0x0200
#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
#define MDIO_BC_AUTO_NEG_MASK 0x1000
#define MDIO_BC_SPEED_SELECT_MASK 0x2000
#define MDIO_STATUS_100_FD 0x4000
#define MDIO_STATUS_100_HD 0x2000
#define MDIO_STATUS_10_FD 0x1000
#define MDIO_STATUS_10_HD 0x0800
#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
#define MDIO_ADVERTISMENT_REG 0x4
#define MDIO_ADVERT_100_FD 0x100
#define MDIO_ADVERT_100_HD 0x080
#define MDIO_ADVERT_10_FD 0x040
#define MDIO_ADVERT_10_HD 0x020
#define MDIO_LINK_UP_MASK 0x4
#define MDIO_START 0x1
#define MDIO_READ 0x2
#define MDIO_WRITE 0x1
#define MDIO_PREAMBLE 0xfffffffful
#define PHY_RESET 0x8000
#define AUTO_NEGOTIATION_ENABLE 0X1000
#define AUTO_NEGOTIATION_COMPLETE 0x20
#define RESTART_AUTO_NEGOTIATION 0X200
/*ETOP_MDIO_CFG MASKS*/
#define SMRST_MASK 0X2000
#define PHYA1_MASK 0X1F00
#define PHYA0_MASK 0XF8
#define UMM1_MASK 0X4
#define UMM0_MASK 0X2
/*ETOP_MDIO_ACCESS MASKS*/
#define MDIO_RA_MASK 0X80000000
#define MDIO_RW_MASK 0X40000000
/*ENET_MAC_CFG MASKS*/
#define BP_MASK 1<<12
#define CGEN_MASK 1<<11
#define IFG_MASK 0x3F<<5
#define IPAUS_MASK 1<<4
#define EPAUS_MASK 1<<3
#define DUPLEX_MASK 1<<2
#define SPEED_MASK 0x2
#define LINK_MASK 1
/*ENETS_CoS_CFG MASKS*/
#define VLAN_MASK 2
#define DSCP_MASK 1
/*ENET_CFG MASKS*/
#define VL2_MASK 1<<29
#define FTUC_MASK 1<<25
#define DPBC_MASK 1<<24
#define DPMC_MASK 1<<23
#define PHY0_ADDR 0
#define PHY1_ADDR 1
#define P1M 0
#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#else //not CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#endif //CONFIG_CPU_LITTLE_ENDIAN
typedef struct vlan_cos_req{
int pri;
int cos_value;
}_vlan_cos_req;
typedef struct dscp_cos_req{
int dscp;
int cos_value;
}_dscp_cos_req;
typedef struct vlan_req{
int cmd;
int index;
u32 data;
u32 entry_value;
}_vlan_req;
typedef struct data_req{
int index;
u32 value;
}_data_req;
enum duplex
{
half,
full,
autoneg
};
struct switch_priv {
struct net_device_stats stats;
int rx_packetlen;
u8 *rx_packetdata;
int rx_status;
int tx_packetlen;
#ifdef CONFIG_NET_HW_FLOWCONTROL
int fc_bit;
#endif //CONFIG_NET_HW_FLOWCONTROL
u8 *tx_packetdata;
int tx_status;
struct dma_device_info *dma_device;
struct sk_buff *skb;
spinlock_t lock;
int mdio_phy_addr;
int current_speed;
int current_speed_selection;
int rx_queue_len;
int full_duplex;
enum duplex current_duplex;
};
#endif //DANUBE_SW_H

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/* incaAscSio.h - (DANUBE) ASC UART tty driver header */
#ifndef __DANUBE_ASC_H
#define __DANUBE_ASC_H
/******************************************************************************
**
** FILE NAME : serial.c
** PROJECT : Danube
** MODULES : ASC/UART
**
** DATE : 27 MAR 2006
** AUTHOR : Liu Peng
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
/* channel operating modes */
/*#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
*/
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define DANUBEASC_TXFIFO_FL 1
#define DANUBEASC_RXFIFO_FL 1
#define DANUBEASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __DANUBE_ASC_H */

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#ifndef __DANUBE_IRQ_H
#define __DANUBE_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>
#endif

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#
# Copyright (C) 2006 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Image/BuildKernel
$(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma
mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma -e \
0x80002000 \
-n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
-d $(KDIR)/vmlinux.lzma $(KDIR)/uImage
cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-uImage
endef
define Image/Build/squashfs
cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-$(1).image
$(call prepare_generic_squashfs,$(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-$(1).image)
endef
define Image/Build/jffs2-64k
dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=64k conv=sync
cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-$(1).image
endef
define Image/Build
$(call Image/Build/$(1),$(1))
endef
$(eval $(call BuildImage))

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target/linux/danube/patches/100-board.patch Normal file
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@ -0,0 +1,66 @@
Index: linux-2.6.23/arch/mips/Kconfig
===================================================================
--- linux-2.6.23.orig/arch/mips/Kconfig 2007-10-16 22:12:19.000000000 +0200
+++ linux-2.6.23/arch/mips/Kconfig 2007-10-16 22:12:21.000000000 +0200
@@ -58,6 +58,17 @@
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
+config DANUBE
+ bool "Danube support"
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SYS_HAS_CPU_MIPS32_R1
+ select HAVE_STD_PC_SERIAL_PORT
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_HAS_EARLY_PRINTK
+ select HW_HAS_PCI
+
config MACH_DECSTATION
bool "DECstations"
select BOOT_ELF32
@@ -605,6 +615,7 @@
source "arch/mips/tx4927/Kconfig"
source "arch/mips/tx4938/Kconfig"
source "arch/mips/vr41xx/Kconfig"
+source "arch/mips/danube/Kconfig"
endmenu
Index: linux-2.6.23/arch/mips/Makefile
===================================================================
--- linux-2.6.23.orig/arch/mips/Makefile 2007-10-16 22:12:21.000000000 +0200
+++ linux-2.6.23/arch/mips/Makefile 2007-10-16 22:12:21.000000000 +0200
@@ -276,6 +276,13 @@
cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/mach-cobalt
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
+#
+# Infineon DANUBE
+#
+core-$(CONFIG_DANUBE) += arch/mips/danube/
+cflags-$(CONFIG_DANUBE) += -Iinclude/asm-mips/mach-danube
+load-$(CONFIG_DANUBE) += 0xffffffff80002000
+
#
# DECstation family
#
Index: linux-2.6.23/include/asm-mips/bootinfo.h
===================================================================
--- linux-2.6.23.orig/include/asm-mips/bootinfo.h 2007-10-16 22:12:19.000000000 +0200
+++ linux-2.6.23/include/asm-mips/bootinfo.h 2007-10-16 22:12:21.000000000 +0200
@@ -208,6 +208,13 @@
#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */
#define MACH_WRPPMC 1
+/*
+ * Valid machtype for group ATHEROS
+ */
+#define MACH_GROUP_DANUBE 29
+#define MACH_INFINEON_DANUBE 0
+
+
#define CL_SIZE COMMAND_LINE_SIZE
const char *get_system_type(void);

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target/linux/danube/patches/110-drivers.patch Normal file
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@ -0,0 +1,68 @@
Index: linux-2.6.23/drivers/serial/Kconfig
===================================================================
--- linux-2.6.23.orig/drivers/serial/Kconfig 2007-11-04 17:29:22.000000000 +0100
+++ linux-2.6.23/drivers/serial/Kconfig 2007-11-04 17:29:25.000000000 +0100
@@ -1259,4 +1259,10 @@
Currently, only 8250 compatible ports are supported, but
others can easily be added.
+config SERIAL_DANUBE
+ bool "Danube serial driver"
+ depends on DANUBE
+ help
+ Driver for the danubes built in ASC hardware
+
endmenu
Index: linux-2.6.23/drivers/serial/Makefile
===================================================================
--- linux-2.6.23.orig/drivers/serial/Makefile 2007-11-04 17:29:22.000000000 +0100
+++ linux-2.6.23/drivers/serial/Makefile 2007-11-04 17:29:25.000000000 +0100
@@ -64,3 +64,4 @@
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+obj-$(CONFIG_SERIAL_DANUBE) += danube_asc.o
Index: linux-2.6.23/drivers/mtd/maps/Makefile
===================================================================
--- linux-2.6.23.orig/drivers/mtd/maps/Makefile 2007-11-04 17:29:22.000000000 +0100
+++ linux-2.6.23/drivers/mtd/maps/Makefile 2007-11-04 17:29:25.000000000 +0100
@@ -71,3 +71,4 @@
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
+obj-$(CONFIG_MTD_DANUBE) += danube.o
Index: linux-2.6.23/drivers/net/Kconfig
===================================================================
--- linux-2.6.23.orig/drivers/net/Kconfig 2007-11-04 17:29:25.000000000 +0100
+++ linux-2.6.23/drivers/net/Kconfig 2007-11-11 16:48:24.000000000 +0100
@@ -339,6 +339,18 @@
source "drivers/net/arm/Kconfig"
+config DANUBE_MII0
+ tristate "Infineon Danube eth0 driver"
+ depends on DANUBE
+ help
+ Support for the MII0 inside the Danube SOC
+
+config DANUBE_MII1
+ tristate "Infineon Danube eth1 driver"
+ depends on DANUBE
+ help
+ Support for the MII1 inside the Danube SOC
+
config AX88796
tristate "ASIX AX88796 NE2000 clone support"
depends on ARM || MIPS
Index: linux-2.6.23/drivers/net/Makefile
===================================================================
--- linux-2.6.23.orig/drivers/net/Makefile 2007-11-04 17:29:25.000000000 +0100
+++ linux-2.6.23/drivers/net/Makefile 2007-11-11 16:47:14.000000000 +0100
@@ -208,6 +208,7 @@
obj-$(CONFIG_FEC_8XX) += fec_8xx/
obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
obj-$(CONFIG_MLX4_CORE) += mlx4/
+obj-$(CONFIG_DANUBE_MII0) += danube_mii0.o
obj-$(CONFIG_MACB) += macb.o

15
target/linux/danube/patches/160-cfi-swap.patch Normal file
View File

@ -0,0 +1,15 @@
Index: linux-2.6.23/drivers/mtd/chips/cfi_cmdset_0002.c
===================================================================
--- linux-2.6.23.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2007-11-02 23:02:29.000000000 +0100
+++ linux-2.6.23/drivers/mtd/chips/cfi_cmdset_0002.c 2007-11-02 23:07:15.000000000 +0100
@@ -1007,7 +1007,9 @@
int ret = 0;
map_word oldd;
int retry_cnt = 0;
-
+#ifdef CONFIG_DANUBE
+ adr ^= 2;
+#endif
adr += chip->start;
spin_lock(chip->mutex);

88
target/linux/danube/series Normal file
View File

@ -0,0 +1,88 @@
Makefile
base-files/etc/config/network
config-2.6.23
files/arch/mips/danube/Kconfig
files/arch/mips/danube/Makefile
files/arch/mips/danube/built-in.o
files/arch/mips/danube/dma-core.c
files/arch/mips/danube/dma-core.h
files/arch/mips/danube/dma-core.o
files/arch/mips/danube/interrupt.c
files/arch/mips/danube/interrupt.o
files/arch/mips/danube/kgdb_serial.c
files/arch/mips/danube/pci.c
files/arch/mips/danube/prom.c
files/arch/mips/danube/prom.o
files/arch/mips/danube/reset.c
files/arch/mips/danube/reset.o
files/arch/mips/danube/setup.c
files/arch/mips/danube/setup.o
files/drivers/mtd/maps/danube.c
files/drivers/serial/danube_asc.c
files/drivers/serial/danube_asc.c~
files/drivers/serial/danube_asc.o
files/include/asm-mips/danube/adm6996.h
files/include/asm-mips/danube/atm_mib.h
files/include/asm-mips/danube/danube.h
files/include/asm-mips/danube/danube_bcu.h
files/include/asm-mips/danube/danube_cgu.h
files/include/asm-mips/danube/danube_deu.h
files/include/asm-mips/danube/danube_deu_structs.h
files/include/asm-mips/danube/danube_dma.h
files/include/asm-mips/danube/danube_eth2.h
files/include/asm-mips/danube/danube_eth2_fw.h
files/include/asm-mips/danube/danube_eth2_fw_with_dplus.h
files/include/asm-mips/danube/danube_eth2_fw_with_dplus_sb.h
files/include/asm-mips/danube/danube_eth_d2.h
files/include/asm-mips/danube/danube_eth_fw_d2.h
files/include/asm-mips/danube/danube_gpio.h
files/include/asm-mips/danube/danube_gptu.h
files/include/asm-mips/danube/danube_icu.h
files/include/asm-mips/danube/danube_led.h
files/include/asm-mips/danube/danube_mei.h
files/include/asm-mips/danube/danube_mei_app.h
files/include/asm-mips/danube/danube_mei_app_ioctl.h
files/include/asm-mips/danube/danube_mei_bsp.h
files/include/asm-mips/danube/danube_mei_ioctl.h
files/include/asm-mips/danube/danube_mei_linux.h
files/include/asm-mips/danube/danube_misc.h
files/include/asm-mips/danube/danube_pmu.h
files/include/asm-mips/danube/danube_ppa_api.h
files/include/asm-mips/danube/danube_ppa_eth_fw_d2.h
files/include/asm-mips/danube/danube_ppa_eth_fw_d3.h
files/include/asm-mips/danube/danube_ppa_hook.h
files/include/asm-mips/danube/danube_ppa_ppe_d3_hal.h
files/include/asm-mips/danube/danube_ppa_ppe_hal.h
files/include/asm-mips/danube/danube_ppa_stack_al.h
files/include/asm-mips/danube/danube_ppe.h
files/include/asm-mips/danube/danube_ppe_fw.h
files/include/asm-mips/danube/danube_ppe_fw_fix_for_pci.h
files/include/asm-mips/danube/danube_rcu.h
files/include/asm-mips/danube/danube_sdio_controller.h
files/include/asm-mips/danube/danube_sdio_controller_registers.h
files/include/asm-mips/danube/danube_ssc.h
files/include/asm-mips/danube/danube_sw.h
files/include/asm-mips/danube/danube_wdt.h
files/include/asm-mips/danube/danube_ws.h
files/include/asm-mips/danube/emulation.h
files/include/asm-mips/danube/ifx_mps.h
files/include/asm-mips/danube/ifx_peripheral_definitions.h
files/include/asm-mips/danube/ifx_sd_card.h
files/include/asm-mips/danube/ifx_serial.h
files/include/asm-mips/danube/ifx_ssc.h
files/include/asm-mips/danube/ifx_ssc_defines.h
files/include/asm-mips/danube/ifx_types.h
files/include/asm-mips/danube/infineon_sdio.h
files/include/asm-mips/danube/infineon_sdio_card.h
files/include/asm-mips/danube/infineon_sdio_cmds.h
files/include/asm-mips/danube/infineon_sdio_controller.h
files/include/asm-mips/danube/irq.h
files/include/asm-mips/danube/memcopy.h
files/include/asm-mips/danube/mps.h
files/include/asm-mips/danube/port.h
files/include/asm-mips/danube/ppe.h
files/include/asm-mips/danube/serial.h
files/include/asm-mips/mach-danube/irq.h
image/Makefile
patches/100-board.patch
patches/110-drivers.patch