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danube gpio cleanup 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9740 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
John Crispin 2007-12-13 21:27:12 +00:00
parent 2b860fac24
commit 2d6e7f4ecc
2 changed files with 25 additions and 17 deletions
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6
target/linux/danube/files/drivers/char/danube_gpio.c
View File

@ -60,9 +60,7 @@
static int port_major = 0;
static int danube_port_pin_usage[MAX_PORTS][PINS_PER_PORT]; // Map for pin usage
static u32 danube_port_bases[MAX_PORTS]
= { DANUBE_GPIO,
DANUBE_GPIO + 0x00000030
}; // Base addresses for ports
= { DANUBE_GPIO_BASE_ADDR, DANUBE_GPIO_P0_PUDEN };
static struct semaphore port_sem;
@ -827,8 +825,6 @@ danube_port_init (void)
int t = 0;
int i = 0;
int err = 0;
u32 pins = 0;
printk ("Danube Port Initialization\n");
sema_init (&port_sem, 1);

36
target/linux/danube/files/include/asm-mips/danube/danube.h
View File

@ -275,17 +275,6 @@
#define INTERNAL_ARB_ENABLE_BIT 0
/*------------ GPIO */
#define DANUBE_GPIO_BASE_ADDR 0xBE100B00
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
/*------------ WDT */
#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
@ -314,9 +303,32 @@
#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25)
#define LED_CON0_AD0 (1 << 24)
/*------------ GPIO */
#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
#endif