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ath9k: fix issues with 5/10 mhz channel bandwidth (#14916) 

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39689 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Felix Fietkau 2014-02-22 13:43:48 +00:00
parent 1577a27b74
commit 26fc63878b
2 changed files with 33 additions and 2 deletions
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31
package/kernel/mac80211/patches/300-pending_work.patch
View File

@ -1,3 +1,21 @@
commit b14fbb554fc65a2e0b5c41a319269b0350f187e7
Author: Felix Fietkau <nbd@openwrt.org>
Date: Sat Feb 22 14:35:25 2014 +0100
ath9k: do not set half/quarter channel flags in AR_PHY_MODE
5/10 MHz channel bandwidth is configured via the PLL clock, instead of
the AR_PHY_MODE register. Using that register is AR93xx specific, and
makes the mode incompatible with earlier chipsets.
In some early versions, these flags were apparently applied at the wrong
point in time and thus did not cause connectivity issues, however now
they are causing problems, as pointed out in this OpenWrt ticket:
https://dev.openwrt.org/ticket/14916
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
commit 0f1cb7be2551b30b02cd54c897e0e29e483cfda5
Author: Felix Fietkau <nbd@openwrt.org>
Date: Sat Feb 22 13:43:29 2014 +0100
@ -3296,3 +3314,16 @@ Date: Thu Jan 23 20:06:34 2014 +0100
"%17s: %2d\n", "MCI Reset",
sc->debug.stats.reset[RESET_TYPE_MCI]);
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -868,10 +868,6 @@ static void ar9003_hw_set_rfmode(struct
if (IS_CHAN_A_FAST_CLOCK(ah, chan))
rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
- if (IS_CHAN_QUARTER_RATE(chan))
- rfMode |= AR_PHY_MODE_QUARTER;
- if (IS_CHAN_HALF_RATE(chan))
- rfMode |= AR_PHY_MODE_HALF;
if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,

4
package/kernel/mac80211/patches/550-ath9k_entropy_from_adc.patch
View File

@ -18,7 +18,7 @@
void (*spectral_scan_trigger)(struct ath_hw *ah);
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1768,6 +1768,26 @@ static void ar9003_hw_tx99_set_txpower(s
@@ -1764,6 +1764,26 @@ static void ar9003_hw_tx99_set_txpower(s
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
}
@ -45,7 +45,7 @@
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
{
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
@@ -1798,6 +1818,7 @@ void ar9003_hw_attach_phy_ops(struct ath
@@ -1794,6 +1814,7 @@ void ar9003_hw_attach_phy_ops(struct ath
priv_ops->set_radar_params = ar9003_hw_set_radar_params;
priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;