imx6: update gw5400-a dts
- remove common imx6q-ventana.dtsi - there isn't enough commonality to warrent this - rename user led's to 1-based - add alises used by bootloader - clean up iomux gpios - fix pfuze slave address - enable sata - add delay after release of pci reset downstream from PCIe switch - remove PCIe clock configuration as its now handled in updated driver Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38081 3c298f89-4303-0410-b956-a3cf2f4a3e73master
Luka Perkov
parent
964174bc4f
commit
19570640aa
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@ -10,16 +10,43 @@
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*/
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/dts-v1/;
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#include "imx6q-ventana.dtsi"
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#include "imx6q.dtsi"
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/ {
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model = "Gateworks Ventana GW5400-A";
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compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
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/* these are used by bootloader for disabling nodes */
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aliases {
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ethernet0 = &fec;
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ethernet1 = ð1;
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sky2 = ð1;
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ssi0 = &ssi1;
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ssi1 = &ssi2;
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ipu0 = &ipu1;
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ipu1 = &ipu2;
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usdhc0 = &usdhc1;
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usdhc1 = &usdhc2;
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usdhc2 = &usdhc3;
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usdhc3 = &usdhc4;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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usb0 = &usbh3;
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usb1 = &usbotg;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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spi4 = &ecspi5;
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pwm0 = &pwm1;
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pwm1 = &pwm2;
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pwm2 = &pwm3;
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pwm3 = &pwm4;
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can0 = &can1;
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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};
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/* SDRAM addressing */
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@ -34,20 +61,23 @@
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leds {
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compatible = "gpio-leds";
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led0: user0 {
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label = "user0";
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gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG# */
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led0: user1 {
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label = "user1";
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gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led1: user1 {
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label = "user1";
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gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR# */
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led1: user2 {
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label = "user2";
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gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
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default-state = "off";
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};
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led2: user2 {
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label = "user2";
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gpios = <&gpio4 15 0>; /* 111 -> MX6_LOCLEDR# */
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led2: user3 {
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label = "user3";
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gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
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default-state = "off";
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};
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};
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@ -102,34 +132,23 @@
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* USB OTG Power Enable */
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MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
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/* 3:19 SPINOR_CS0# */
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MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
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/* 1:09 MX6_DIO0 (could also be PWM1_PWM0) */
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MX6Q_PAD_GPIO_9__GPIO1_IO09 0x80000000
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/* 1:19 MX6_DIO1 (could also be PWM2_PWM0) */
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MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
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/* 2:09 MX6_DIO2 (could also be PWM3_PWM0) */
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MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
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/* 2:10 MX6_DIO3 (could also be PWM3_PWM0) */
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MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x80000000
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/* 1:16 USBHUB_RST# */
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MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
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/* PCIE IRQ */
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MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
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/* PCIE RST */
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MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x08000000
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/* 1:12 MIPI_DIO */
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MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000
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/* AUD4_MCK */
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MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
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MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
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MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
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MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user0 led */
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MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user1 led */
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MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user2 led */
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/* let bootloader choose these based on hwconfig */
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#if 0
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MX6Q_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* MX6_DIO0 (or PWM1_PWM0) */
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MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x80000000 /* MX6_DIO1 (or PWM2_PWM0) */
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MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* MX6_DIO2 (or PWM3_PWM0) */
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MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* MX6_DIO3 (or PWM3_PWM0) */
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#endif
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MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
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MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
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MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x08000000 /* PCIE RST */
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MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
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MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 /* AUD4_MCK */
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>;
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};
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};
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@ -262,7 +281,6 @@
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&can1 {
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reg = <0x02090000 0x4000>;
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interrupts = <0 110 0x04>;
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//clock-frequency
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status = "okay";
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};
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@ -271,7 +289,7 @@
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};
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&pcie {
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reset-gpios = <&gpio1 29 0>;
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reset-gpio = <&gpio1 29 0>;
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status = "okay";
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eth1: sky2@8 { /* MAC/PHY on bus 8 */
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@ -365,7 +383,7 @@
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pmic: pfuze@08 {
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compatible = "fsl,pfuze100";
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reg = <0x0a>;
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reg = <0x08>;
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};
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pciswitch: pex8609@3f {
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@ -426,3 +444,7 @@
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crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
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};
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};
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&sata {
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status = "okay";
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};
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@ -1,51 +0,0 @@
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/*
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* Copyright 2013 Gateworks Corporation
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx6q.dtsi"
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/ {
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model = "Gateworks Ventana";
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system-serial = "";
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// these are used by bootloader for disabling nodes
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aliases {
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// ethernet0 = ð0;
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// ethernet1 = ð1;
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ssi0 = &ssi1;
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ssi1 = &ssi2;
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ipu0 = &ipu1;
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ipu1 = &ipu2;
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// mipi_csi = &mipi_csi;
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// mipi_dsi = &mipi_dsi;
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usdhc0 = &usdhc1;
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usdhc1 = &usdhc2;
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usdhc2 = &usdhc3;
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usdhc3 = &usdhc4;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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usb0 = &usbh3;
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usb1 = &usbotg;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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spi4 = &ecspi5;
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pwm0 = &pwm1;
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pwm1 = &pwm2;
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pwm2 = &pwm3;
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pwm3 = &pwm4;
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can0 = &can1;
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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};
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};
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@ -25,7 +25,38 @@
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};
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ecspi1 {
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@@ -205,6 +213,12 @@
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@@ -187,6 +195,30 @@
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MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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+
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+ /* No strobe */
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+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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+ MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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+ MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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+ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
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+ MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
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+ MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
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+ MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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+ MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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+ MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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+ MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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+ MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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+ MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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+ MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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+ MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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+ MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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+ MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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+ >;
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+ };
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};
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i2c1 {
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@@ -205,6 +237,12 @@
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MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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>;
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};
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@ -38,7 +69,7 @@
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};
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i2c3 {
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@@ -214,6 +228,12 @@
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@@ -214,6 +252,12 @@
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MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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@ -51,7 +82,7 @@
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};
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uart1 {
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@@ -223,6 +243,12 @@
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@@ -223,6 +267,12 @@
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MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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@ -64,7 +95,7 @@
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};
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uart2 {
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@@ -232,6 +258,21 @@
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@@ -232,6 +282,21 @@
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MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
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>;
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};
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@ -86,7 +117,7 @@
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};
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uart4 {
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@@ -242,6 +283,15 @@
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@@ -242,6 +307,15 @@
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>;
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};
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};
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@ -112,7 +143,7 @@
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/micrel_phy.h>
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@@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
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@@ -145,6 +146,38 @@ static void __init imx6q_sabrelite_init(
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imx6q_sabrelite_cko1_setup();
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}
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@ -137,48 +168,21 @@
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; // GPIO1-7 output high
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+ pci_write_config_dword(dev, 0x644, dw);
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+
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+ mdelay(1);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
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+ mx6_ventana_pciesw_early_fixup);
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+
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+/*
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+ * configure PCIe core clock and PCIe ref clock
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+ *
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+ * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
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+ */
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+static void __init imx6q_ventana_pcie_setup(void)
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+{
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+ struct clk *axi_sel, *axi, *ref;
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+
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+ axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
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+ axi = clk_get_sys(NULL, "axi");
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+ ref = clk_get_sys(NULL, "pcie_ref_125m");
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+ if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
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+ pr_err("pcie setup failed - can't get clocks\n");
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+ goto put_clk;
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+ }
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+ clk_set_parent(axi_sel, axi);
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+ clk_prepare_enable(ref);
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+
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+put_clk:
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+ if (!IS_ERR(axi_sel))
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+ clk_put(axi_sel);
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+ if (!IS_ERR(axi))
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+ clk_put(axi);
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+ if (!IS_ERR(ref))
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+ clk_put(ref);
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+}
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+
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+static void __init imx6q_ventana_init(void)
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+{
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+ imx6q_ventana_pcie_setup();
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+ imx6q_sabrelite_cko1_setup();
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+}
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+
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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@@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
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@@ -163,6 +196,9 @@ static void __init imx6q_usb_init(void)
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static void __init imx6q_init_machine(void)
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{
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Reference in New Issue