ralink: set v3.10 as default
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37497 3c298f89-4303-0410-b956-a3cf2f4a3e73master
John Crispin
parent
bd2cbce22c
commit
020c18be59
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@ -13,7 +13,7 @@ SUBTARGETS:=rt288x rt305x rt3883 mt7620a
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CFLAGS:=-Os -pipe -fno-caller-saves -mno-branch-likely
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FEATURES:=squashfs gpio
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LINUX_VERSION:=3.9.10
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LINUX_VERSION:=3.10.1
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES+=\
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@ -1,154 +0,0 @@
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From 67d6534cdc4f90e6998a79ac57d5318412f18486 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 11 Apr 2013 05:34:59 +0000
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Subject: [PATCH 100/164] MIPS: move mips_{set,get}_machine_name() to a more
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generic place
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Previously this functionality was only available to users of the mips_machine
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api. Moving the code to prom.c allows us to also add a OF wrapper.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5164/
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---
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arch/mips/include/asm/mips_machine.h | 4 ----
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arch/mips/include/asm/prom.h | 3 +++
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arch/mips/kernel/mips_machine.c | 21 ---------------------
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arch/mips/kernel/proc.c | 2 +-
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arch/mips/kernel/prom.c | 31 +++++++++++++++++++++++++++++++
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5 files changed, 35 insertions(+), 26 deletions(-)
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--- a/arch/mips/include/asm/mips_machine.h
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+++ b/arch/mips/include/asm/mips_machine.h
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@@ -42,13 +42,9 @@ extern long __mips_machines_end;
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#ifdef CONFIG_MIPS_MACHINE
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int mips_machtype_setup(char *id) __init;
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void mips_machine_setup(void) __init;
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-void mips_set_machine_name(const char *name) __init;
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-char *mips_get_machine_name(void);
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#else
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static inline int mips_machtype_setup(char *id) { return 1; }
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static inline void mips_machine_setup(void) { }
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-static inline void mips_set_machine_name(const char *name) { }
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-static inline char *mips_get_machine_name(void) { return NULL; }
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#endif /* CONFIG_MIPS_MACHINE */
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#endif /* __ASM_MIPS_MACHINE_H */
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--- a/arch/mips/include/asm/prom.h
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+++ b/arch/mips/include/asm/prom.h
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@@ -48,4 +48,7 @@ extern void __dt_setup_arch(struct boot_
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static inline void device_tree_init(void) { }
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#endif /* CONFIG_OF */
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+extern char *mips_get_machine_name(void);
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+extern void mips_set_machine_name(const char *name);
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+
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#endif /* __ASM_PROM_H */
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--- a/arch/mips/kernel/mips_machine.c
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+++ b/arch/mips/kernel/mips_machine.c
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@@ -13,7 +13,6 @@
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#include <asm/mips_machine.h>
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static struct mips_machine *mips_machine __initdata;
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-static char *mips_machine_name = "Unknown";
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#define for_each_machine(mach) \
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for ((mach) = (struct mips_machine *)&__mips_machines_start; \
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@@ -21,25 +20,6 @@ static char *mips_machine_name = "Unknow
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(unsigned long)(mach) < (unsigned long)&__mips_machines_end; \
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(mach)++)
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-__init void mips_set_machine_name(const char *name)
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-{
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- char *p;
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-
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- if (name == NULL)
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- return;
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-
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- p = kstrdup(name, GFP_KERNEL);
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- if (!p)
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- pr_err("MIPS: no memory for machine_name\n");
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-
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- mips_machine_name = p;
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-}
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-
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-char *mips_get_machine_name(void)
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-{
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- return mips_machine_name;
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-}
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-
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__init int mips_machtype_setup(char *id)
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{
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struct mips_machine *mach;
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@@ -79,7 +59,6 @@ __init void mips_machine_setup(void)
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return;
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mips_set_machine_name(mips_machine->mach_name);
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- pr_info("MIPS: machine is %s\n", mips_machine_name);
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if (mips_machine->mach_setup)
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mips_machine->mach_setup();
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--- a/arch/mips/kernel/proc.c
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+++ b/arch/mips/kernel/proc.c
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@@ -12,7 +12,7 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsregs.h>
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#include <asm/processor.h>
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-#include <asm/mips_machine.h>
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+#include <asm/prom.h>
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unsigned int vced_count, vcei_count;
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--- a/arch/mips/kernel/prom.c
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+++ b/arch/mips/kernel/prom.c
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@@ -23,6 +23,22 @@
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#include <asm/page.h>
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#include <asm/prom.h>
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+static char mips_machine_name[64] = "Unknown";
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+
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+__init void mips_set_machine_name(const char *name)
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+{
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+ if (name == NULL)
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+ return;
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+
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+ strncpy(mips_machine_name, name, sizeof(mips_machine_name));
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+ pr_info("MIPS: machine is %s\n", mips_get_machine_name());
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+}
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+
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+char *mips_get_machine_name(void)
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+{
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+ return mips_machine_name;
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+}
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+
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int __init early_init_dt_scan_memory_arch(unsigned long node,
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const char *uname, int depth,
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void *data)
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@@ -50,6 +66,18 @@ void __init early_init_dt_setup_initrd_a
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}
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#endif
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+int __init early_init_dt_scan_model(unsigned long node, const char *uname,
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+ int depth, void *data)
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+{
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+ if (!depth) {
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+ char *model = of_get_flat_dt_prop(node, "model", NULL);
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+
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+ if (model)
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+ mips_set_machine_name(model);
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+ }
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+ return 0;
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+}
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+
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void __init early_init_devtree(void *params)
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{
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/* Setup flat device-tree pointer */
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@@ -65,6 +93,9 @@ void __init early_init_devtree(void *par
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/* Scan memory nodes */
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of_scan_flat_dt(early_init_dt_scan_root, NULL);
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of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
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+
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+ /* try to load the mips machine name */
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+ of_scan_flat_dt(early_init_dt_scan_model, NULL);
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}
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void __init __dt_setup_arch(struct boot_param_header *bph)
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@ -1,35 +0,0 @@
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From ca19f83f8551e6dd19073f04ad91639e98d6e22e Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 10 Apr 2013 09:07:27 +0200
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Subject: [PATCH 101/164] MIPS: ralink: add PCI IRQ handling
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The Ralink IRQ code was not handling the PCI IRQ yet. Add this functionaility
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to make PCI work on rt3883.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5165/
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---
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arch/mips/ralink/irq.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/arch/mips/ralink/irq.c
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+++ b/arch/mips/ralink/irq.c
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@@ -31,6 +31,7 @@
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#define INTC_INT_GLOBAL BIT(31)
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#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
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+#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
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#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
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#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
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#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
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@@ -104,6 +105,9 @@ asmlinkage void plat_irq_dispatch(void)
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else if (pending & STATUSF_IP6)
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do_IRQ(RALINK_CPU_IRQ_WIFI);
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+ else if (pending & STATUSF_IP4)
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+ do_IRQ(RALINK_CPU_IRQ_PCI);
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+
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else if (pending & STATUSF_IP2)
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do_IRQ(RALINK_CPU_IRQ_INTC);
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@ -1,35 +0,0 @@
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From 48cf6bc7019d418e18831214731a55ec7320abb3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 19:01:49 +0100
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Subject: [PATCH 102/164] MIPS: ralink: add RT3352 register defines
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Add a few missing defines that are needed to make USB and clock detection work
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on the RT3352.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5166/
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
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#define RT305X_GPIO_MODE_SDRAM BIT(8)
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#define RT305X_GPIO_MODE_RGMII BIT(9)
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+#define RT3352_SYSC_REG_SYSCFG0 0x010
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+#define RT3352_SYSC_REG_SYSCFG1 0x014
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+#define RT3352_SYSC_REG_CLKCFG1 0x030
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+#define RT3352_SYSC_REG_RSTCTRL 0x034
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+#define RT3352_SYSC_REG_USB_PS 0x05c
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+
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+#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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+#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
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+#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
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+#define RT3352_RSTCTRL_UHST BIT(22)
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+#define RT3352_RSTCTRL_UDEV BIT(25)
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+#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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+
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#endif
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@ -1,47 +0,0 @@
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From 93ded6b41dfdf71f2d2b2cf96e26f5784f373f5c Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 22 Mar 2013 19:25:59 +0100
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Subject: [PATCH 103/164] MIPS: ralink: fix RT305x clock setup
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Add a few missing clocks.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5167/
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---
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arch/mips/ralink/rt305x.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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+ unsigned long wmac_rate = 40000000;
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+
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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if (soc_is_rt305x() || soc_is_rt3350()) {
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@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
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BUG();
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}
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+ if (soc_is_rt3352() || soc_is_rt5350()) {
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+ u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
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+
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+ if (!(val & RT3352_CLKCFG0_XTAL_SEL))
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+ wmac_rate = 20000000;
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+ }
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+
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000100.timer", wdt_rate);
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+ ralink_clk_add("10000120.watchdog", wdt_rate);
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ralink_clk_add("10000500.uart", uart_rate);
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ralink_clk_add("10000c00.uartlite", uart_rate);
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+ ralink_clk_add("10100000.ethernet", sys_rate);
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+ ralink_clk_add("10180000.wmac", wmac_rate);
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}
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void __init ralink_of_remap(void)
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@ -1,24 +0,0 @@
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From cd202a8165e847e1c7bf8454982149730376f27a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 16 Mar 2013 16:28:54 +0100
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Subject: [PATCH 104/164] MIPS: ralink: add missing comment in irq driver
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Trivial patch that adds a comment that makes the code more readable.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5168/
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---
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arch/mips/ralink/irq.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/mips/ralink/irq.c
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+++ b/arch/mips/ralink/irq.c
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@@ -166,6 +166,7 @@ static int __init intc_of_init(struct de
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irq_set_chained_handler(irq, ralink_intc_irq_handler);
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irq_set_handler_data(irq, domain);
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+ /* tell the kernel which irq is used for performance monitoring */
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cp0_perfcount_irq = irq_create_mapping(domain, 9);
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return 0;
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@ -1,32 +0,0 @@
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From 4c77c43dbef08096dd3798d4e421495b2c048285 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 25 Mar 2013 11:19:58 +0100
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Subject: [PATCH 105/164] MIPS: ralink: add RT5350 sdram register defines
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Add a few missing defines that are needed to make memory detection work on the
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RT5350.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5169/
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -97,6 +97,14 @@ static inline int soc_is_rt5350(void)
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#define RT5350_SYSCFG0_CPUCLK_320 0x2
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#define RT5350_SYSCFG0_CPUCLK_300 0x3
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+#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
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+#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
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+#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
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+#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
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+#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
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+#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
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+#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
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+
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/* multi function gpio pins */
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#define RT305X_GPIO_I2C_SD 1
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#define RT305X_GPIO_I2C_SCLK 2
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@ -1,28 +0,0 @@
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From 3d38304ce93752b9f196b22b7abeb8296fff7ba7 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 9 Apr 2013 18:31:15 +0200
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Subject: [PATCH 106/164] MIPS: ralink: make early_printk work on RT2880
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RT2880 has a different location for the early serial port.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5170/
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---
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arch/mips/ralink/early_printk.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/arch/mips/ralink/early_printk.c
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+++ b/arch/mips/ralink/early_printk.c
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@@ -11,7 +11,11 @@
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#include <asm/addrspace.h>
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+#ifdef CONFIG_SOC_RT288X
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+#define EARLY_UART_BASE 0x300c00
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+#else
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#define EARLY_UART_BASE 0x10000c00
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+#endif
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#define UART_REG_RX 0x00
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#define UART_REG_TX 0x04
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@ -1,36 +0,0 @@
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From 5dad33f0c1dd0b1605df6571e3493799106f36ee Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 12 Apr 2013 22:12:09 +0200
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Subject: [PATCH 107/164] MIPS: ralink: rename gpio_pinmux to rt_gpio_pinmux
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Add proper namespacing to the variable.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5171/
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---
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arch/mips/ralink/common.h | 2 +-
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arch/mips/ralink/rt305x.c | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -24,7 +24,7 @@ struct ralink_pinmux {
|
||||
int uart_shift;
|
||||
void (*wdt_reset)(void);
|
||||
};
|
||||
-extern struct ralink_pinmux gpio_pinmux;
|
||||
+extern struct ralink_pinmux rt_gpio_pinmux;
|
||||
|
||||
struct ralink_soc_info {
|
||||
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -114,7 +114,7 @@ void rt305x_wdt_reset(void)
|
||||
rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
|
||||
}
|
||||
|
||||
-struct ralink_pinmux gpio_pinmux = {
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.mode = mode_mux,
|
||||
.uart = uart_mux,
|
||||
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
From 7a77fb07f96b8c7fa446ca1b62eddf7213362a70 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 22:16:12 +0200
|
||||
Subject: [PATCH 108/164] MIPS: ralink: make the RT305x pinmuxing structure
|
||||
static
|
||||
|
||||
These structures are exported via struct ralink_pinmux rt_gpio_pinmux and can
|
||||
hence be static.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5172/
|
||||
---
|
||||
arch/mips/ralink/rt305x.c | 6 +++---
|
||||
1 file changed, 3 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -22,7 +22,7 @@
|
||||
|
||||
enum rt305x_soc_type rt305x_soc;
|
||||
|
||||
-struct ralink_pinmux_grp mode_mux[] = {
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
{
|
||||
.name = "i2c",
|
||||
.mask = RT305X_GPIO_MODE_I2C,
|
||||
@@ -61,7 +61,7 @@ struct ralink_pinmux_grp mode_mux[] = {
|
||||
}, {0}
|
||||
};
|
||||
|
||||
-struct ralink_pinmux_grp uart_mux[] = {
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
{
|
||||
.name = "uartf",
|
||||
.mask = RT305X_GPIO_MODE_UARTF,
|
||||
@@ -103,7 +103,7 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
}, {0}
|
||||
};
|
||||
|
||||
-void rt305x_wdt_reset(void)
|
||||
+static void rt305x_wdt_reset(void)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From b9ed5175f31c55122690a3e9af1cea2d1937768d Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 12:40:23 +0200
|
||||
Subject: [PATCH 109/164] MIPS: ralink: add pci group to struct ralink_pinmux
|
||||
|
||||
This will be used for RT3662/RT3883.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Acked-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5173/
|
||||
---
|
||||
arch/mips/ralink/common.h | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -23,6 +23,9 @@ struct ralink_pinmux {
|
||||
struct ralink_pinmux_grp *uart;
|
||||
int uart_shift;
|
||||
void (*wdt_reset)(void);
|
||||
+ struct ralink_pinmux_grp *pci;
|
||||
+ int pci_shift;
|
||||
+ u32 pci_mask;
|
||||
};
|
||||
extern struct ralink_pinmux rt_gpio_pinmux;
|
||||
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
From f4c0850f31389bbb6b8d806be7786efc62af1e84 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 12:45:27 +0200
|
||||
Subject: [PATCH 110/164] MIPS: ralink: add uart mask to struct ralink_pinmux
|
||||
|
||||
Add a field for the uart muxing mask and set it inside the rt305x setup code.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5744/
|
||||
---
|
||||
arch/mips/ralink/common.h | 1 +
|
||||
arch/mips/ralink/rt305x.c | 5 +++--
|
||||
2 files changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -22,6 +22,7 @@ struct ralink_pinmux {
|
||||
struct ralink_pinmux_grp *mode;
|
||||
struct ralink_pinmux_grp *uart;
|
||||
int uart_shift;
|
||||
+ u32 uart_mask;
|
||||
void (*wdt_reset)(void);
|
||||
struct ralink_pinmux_grp *pci;
|
||||
int pci_shift;
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -91,12 +91,12 @@ static struct ralink_pinmux_grp uart_mux
|
||||
.name = "gpio uartf",
|
||||
.mask = RT305X_GPIO_MODE_GPIO_UARTF,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
- .gpio_last = RT305X_GPIO_14,
|
||||
+ .gpio_last = RT305X_GPIO_10,
|
||||
}, {
|
||||
.name = "gpio i2s",
|
||||
.mask = RT305X_GPIO_MODE_GPIO_I2S,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
- .gpio_last = RT305X_GPIO_14,
|
||||
+ .gpio_last = RT305X_GPIO_10,
|
||||
}, {
|
||||
.name = "gpio",
|
||||
.mask = RT305X_GPIO_MODE_GPIO,
|
||||
@@ -118,6 +118,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.mode = mode_mux,
|
||||
.uart = uart_mux,
|
||||
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
|
||||
.wdt_reset = rt305x_wdt_reset,
|
||||
};
|
||||
|
||||
|
|
@ -1,264 +0,0 @@
|
|||
From 9a63b5b2e6684a80053b866de0c83adf284be857 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 27 Jan 2013 09:17:20 +0100
|
||||
Subject: [PATCH 111/164] MIPS: ralink: adds support for RT2880 SoC family
|
||||
|
||||
Add support code for rt2880 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5176/
|
||||
---
|
||||
arch/mips/Kconfig | 2 +-
|
||||
arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
|
||||
arch/mips/ralink/Kconfig | 3 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/rt288x.c | 139 ++++++++++++++++++++++++++++
|
||||
6 files changed, 198 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
create mode 100644 arch/mips/ralink/rt288x.c
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -1164,7 +1164,7 @@ config BOOT_ELF32
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT
|
||||
int
|
||||
- default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
|
||||
+ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
|
||||
default "6" if MIPS_CPU_SCACHE
|
||||
default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
|
||||
default "5"
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
@@ -0,0 +1,49 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _RT288X_REGS_H_
|
||||
+#define _RT288X_REGS_H_
|
||||
+
|
||||
+#define RT2880_SYSC_BASE 0x00300000
|
||||
+
|
||||
+#define SYSC_REG_CHIP_NAME0 0x00
|
||||
+#define SYSC_REG_CHIP_NAME1 0x04
|
||||
+#define SYSC_REG_CHIP_ID 0x0c
|
||||
+#define SYSC_REG_SYSTEM_CONFIG 0x10
|
||||
+#define SYSC_REG_CLKCFG 0x30
|
||||
+
|
||||
+#define RT2880_CHIP_NAME0 0x38325452
|
||||
+#define RT2880_CHIP_NAME1 0x20203038
|
||||
+
|
||||
+#define CHIP_ID_ID_MASK 0xff
|
||||
+#define CHIP_ID_ID_SHIFT 8
|
||||
+#define CHIP_ID_REV_MASK 0xff
|
||||
+
|
||||
+#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
|
||||
+#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
|
||||
+#define SYSTEM_CONFIG_CPUCLK_250 0x0
|
||||
+#define SYSTEM_CONFIG_CPUCLK_266 0x1
|
||||
+#define SYSTEM_CONFIG_CPUCLK_280 0x2
|
||||
+#define SYSTEM_CONFIG_CPUCLK_300 0x3
|
||||
+
|
||||
+#define RT2880_GPIO_MODE_I2C BIT(0)
|
||||
+#define RT2880_GPIO_MODE_UART0 BIT(1)
|
||||
+#define RT2880_GPIO_MODE_SPI BIT(2)
|
||||
+#define RT2880_GPIO_MODE_UART1 BIT(3)
|
||||
+#define RT2880_GPIO_MODE_JTAG BIT(4)
|
||||
+#define RT2880_GPIO_MODE_MDIO BIT(5)
|
||||
+#define RT2880_GPIO_MODE_SDRAM BIT(6)
|
||||
+#define RT2880_GPIO_MODE_PCI BIT(7)
|
||||
+
|
||||
+#define CLKCFG_SRAM_CS_N_WDT BIT(9)
|
||||
+
|
||||
+#endif
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -6,6 +6,9 @@ choice
|
||||
help
|
||||
Select Ralink MIPS SoC type.
|
||||
|
||||
+ config SOC_RT288X
|
||||
+ bool "RT288x"
|
||||
+
|
||||
config SOC_RT305X
|
||||
bool "RT305x"
|
||||
select USB_ARCH_HAS_HCD
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -8,6 +8,7 @@
|
||||
|
||||
obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
|
||||
+obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -5,6 +5,11 @@ core-$(CONFIG_RALINK) += arch/mips/rali
|
||||
cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
|
||||
|
||||
#
|
||||
+# Ralink RT288x
|
||||
+#
|
||||
+load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
|
||||
+
|
||||
+#
|
||||
# Ralink RT305x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/rt288x.c
|
||||
@@ -0,0 +1,139 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+#include <asm/mipsregs.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+#include <asm/mach-ralink/rt288x.h>
|
||||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = RT2880_GPIO_MODE_I2C,
|
||||
+ .gpio_first = 1,
|
||||
+ .gpio_last = 2,
|
||||
+ }, {
|
||||
+ .name = "spi",
|
||||
+ .mask = RT2880_GPIO_MODE_SPI,
|
||||
+ .gpio_first = 3,
|
||||
+ .gpio_last = 6,
|
||||
+ }, {
|
||||
+ .name = "uartlite",
|
||||
+ .mask = RT2880_GPIO_MODE_UART0,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "jtag",
|
||||
+ .mask = RT2880_GPIO_MODE_JTAG,
|
||||
+ .gpio_first = 17,
|
||||
+ .gpio_last = 21,
|
||||
+ }, {
|
||||
+ .name = "mdio",
|
||||
+ .mask = RT2880_GPIO_MODE_MDIO,
|
||||
+ .gpio_first = 22,
|
||||
+ .gpio_last = 23,
|
||||
+ }, {
|
||||
+ .name = "sdram",
|
||||
+ .mask = RT2880_GPIO_MODE_SDRAM,
|
||||
+ .gpio_first = 24,
|
||||
+ .gpio_last = 39,
|
||||
+ }, {
|
||||
+ .name = "pci",
|
||||
+ .mask = RT2880_GPIO_MODE_PCI,
|
||||
+ .gpio_first = 40,
|
||||
+ .gpio_last = 71,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static void rt288x_wdt_reset(void)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ /* enable WDT reset output on pin SRAM_CS_N */
|
||||
+ t = rt_sysc_r32(SYSC_REG_CLKCFG);
|
||||
+ t |= CLKCFG_SRAM_CS_N_WDT;
|
||||
+ rt_sysc_w32(t, SYSC_REG_CLKCFG);
|
||||
+}
|
||||
+
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .wdt_reset = rt288x_wdt_reset,
|
||||
+};
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
||||
+{
|
||||
+ unsigned long cpu_rate;
|
||||
+ u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
|
||||
+ t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
|
||||
+
|
||||
+ switch (t) {
|
||||
+ case SYSTEM_CONFIG_CPUCLK_250:
|
||||
+ cpu_rate = 250000000;
|
||||
+ break;
|
||||
+ case SYSTEM_CONFIG_CPUCLK_266:
|
||||
+ cpu_rate = 266666667;
|
||||
+ break;
|
||||
+ case SYSTEM_CONFIG_CPUCLK_280:
|
||||
+ cpu_rate = 280000000;
|
||||
+ break;
|
||||
+ case SYSTEM_CONFIG_CPUCLK_300:
|
||||
+ cpu_rate = 300000000;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ ralink_clk_add("cpu", cpu_rate);
|
||||
+ ralink_clk_add("300100.timer", cpu_rate / 2);
|
||||
+ ralink_clk_add("300120.watchdog", cpu_rate / 2);
|
||||
+ ralink_clk_add("300500.uart", cpu_rate / 2);
|
||||
+ ralink_clk_add("300c00.uartlite", cpu_rate / 2);
|
||||
+ ralink_clk_add("400000.ethernet", cpu_rate / 2);
|
||||
+}
|
||||
+
|
||||
+void __init ralink_of_remap(void)
|
||||
+{
|
||||
+ rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
|
||||
+ rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
|
||||
+
|
||||
+ if (!rt_sysc_membase || !rt_memc_membase)
|
||||
+ panic("Failed to remap core resources");
|
||||
+}
|
||||
+
|
||||
+void prom_soc_init(struct ralink_soc_info *soc_info)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
|
||||
+ const char *name;
|
||||
+ u32 n0;
|
||||
+ u32 n1;
|
||||
+ u32 id;
|
||||
+
|
||||
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||||
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||||
+ id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
|
||||
+
|
||||
+ if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
|
||||
+ soc_info->compatible = "ralink,r2880-soc";
|
||||
+ name = "RT2880";
|
||||
+ } else {
|
||||
+ panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
|
||||
+ }
|
||||
+
|
||||
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
|
||||
+ "Ralink %s id:%u rev:%u",
|
||||
+ name,
|
||||
+ (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
|
||||
+ (id & CHIP_ID_REV_MASK));
|
||||
+}
|
||||
|
|
@ -1,552 +0,0 @@
|
|||
From b91aa2fcc93a92d851baa0745790a999e1f31592 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 27 Jan 2013 09:39:02 +0100
|
||||
Subject: [PATCH 112/164] MIPS: ralink: adds support for RT3883 SoC family
|
||||
|
||||
Add support code for rt3883 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5185/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 5 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/rt3883.c | 242 +++++++++++++++++++++++++++
|
||||
5 files changed, 500 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
create mode 100644 arch/mips/ralink/rt3883.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
@@ -0,0 +1,247 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 SoC register definitions
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#ifndef _RT3883_REGS_H_
|
||||
+#define _RT3883_REGS_H_
|
||||
+
|
||||
+#include <linux/bitops.h>
|
||||
+
|
||||
+#define RT3883_SDRAM_BASE 0x00000000
|
||||
+#define RT3883_SYSC_BASE 0x10000000
|
||||
+#define RT3883_TIMER_BASE 0x10000100
|
||||
+#define RT3883_INTC_BASE 0x10000200
|
||||
+#define RT3883_MEMC_BASE 0x10000300
|
||||
+#define RT3883_UART0_BASE 0x10000500
|
||||
+#define RT3883_PIO_BASE 0x10000600
|
||||
+#define RT3883_FSCC_BASE 0x10000700
|
||||
+#define RT3883_NANDC_BASE 0x10000810
|
||||
+#define RT3883_I2C_BASE 0x10000900
|
||||
+#define RT3883_I2S_BASE 0x10000a00
|
||||
+#define RT3883_SPI_BASE 0x10000b00
|
||||
+#define RT3883_UART1_BASE 0x10000c00
|
||||
+#define RT3883_PCM_BASE 0x10002000
|
||||
+#define RT3883_GDMA_BASE 0x10002800
|
||||
+#define RT3883_CODEC1_BASE 0x10003000
|
||||
+#define RT3883_CODEC2_BASE 0x10003800
|
||||
+#define RT3883_FE_BASE 0x10100000
|
||||
+#define RT3883_ROM_BASE 0x10118000
|
||||
+#define RT3883_USBDEV_BASE 0x10112000
|
||||
+#define RT3883_PCI_BASE 0x10140000
|
||||
+#define RT3883_WLAN_BASE 0x10180000
|
||||
+#define RT3883_USBHOST_BASE 0x101c0000
|
||||
+#define RT3883_BOOT_BASE 0x1c000000
|
||||
+#define RT3883_SRAM_BASE 0x1e000000
|
||||
+#define RT3883_PCIMEM_BASE 0x20000000
|
||||
+
|
||||
+#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
|
||||
+#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
|
||||
+
|
||||
+#define RT3883_SYSC_SIZE 0x100
|
||||
+#define RT3883_TIMER_SIZE 0x100
|
||||
+#define RT3883_INTC_SIZE 0x100
|
||||
+#define RT3883_MEMC_SIZE 0x100
|
||||
+#define RT3883_UART0_SIZE 0x100
|
||||
+#define RT3883_UART1_SIZE 0x100
|
||||
+#define RT3883_PIO_SIZE 0x100
|
||||
+#define RT3883_FSCC_SIZE 0x100
|
||||
+#define RT3883_NANDC_SIZE 0x0f0
|
||||
+#define RT3883_I2C_SIZE 0x100
|
||||
+#define RT3883_I2S_SIZE 0x100
|
||||
+#define RT3883_SPI_SIZE 0x100
|
||||
+#define RT3883_PCM_SIZE 0x800
|
||||
+#define RT3883_GDMA_SIZE 0x800
|
||||
+#define RT3883_CODEC1_SIZE 0x800
|
||||
+#define RT3883_CODEC2_SIZE 0x800
|
||||
+#define RT3883_FE_SIZE 0x10000
|
||||
+#define RT3883_ROM_SIZE 0x4000
|
||||
+#define RT3883_USBDEV_SIZE 0x4000
|
||||
+#define RT3883_PCI_SIZE 0x40000
|
||||
+#define RT3883_WLAN_SIZE 0x40000
|
||||
+#define RT3883_USBHOST_SIZE 0x40000
|
||||
+#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
|
||||
+#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
|
||||
+
|
||||
+/* SYSC registers */
|
||||
+#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
|
||||
+#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
|
||||
+#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
|
||||
+#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
|
||||
+#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
|
||||
+#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
|
||||
+#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
|
||||
+#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
|
||||
+#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
|
||||
+#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
|
||||
+#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
|
||||
+#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
|
||||
+#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
|
||||
+#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
|
||||
+#define RT3883_SYSC_REG_PMU 0x88
|
||||
+#define RT3883_SYSC_REG_PMU1 0x8c
|
||||
+
|
||||
+#define RT3883_CHIP_NAME0 0x38335452
|
||||
+#define RT3883_CHIP_NAME1 0x20203338
|
||||
+
|
||||
+#define RT3883_REVID_VER_ID_MASK 0x0f
|
||||
+#define RT3883_REVID_VER_ID_SHIFT 8
|
||||
+#define RT3883_REVID_ECO_ID_MASK 0x0f
|
||||
+
|
||||
+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
|
||||
+#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
|
||||
+#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
|
||||
+#define RT3883_SYSCFG0_CPUCLK_250 0x0
|
||||
+#define RT3883_SYSCFG0_CPUCLK_384 0x1
|
||||
+#define RT3883_SYSCFG0_CPUCLK_480 0x2
|
||||
+#define RT3883_SYSCFG0_CPUCLK_500 0x3
|
||||
+
|
||||
+#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
|
||||
+#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
|
||||
+#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
|
||||
+#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
|
||||
+#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
|
||||
+
|
||||
+#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
|
||||
+#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
|
||||
+#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
|
||||
+#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
|
||||
+
|
||||
+#define RT3883_GPIO_MODE_I2C BIT(0)
|
||||
+#define RT3883_GPIO_MODE_SPI BIT(1)
|
||||
+#define RT3883_GPIO_MODE_UART0_SHIFT 2
|
||||
+#define RT3883_GPIO_MODE_UART0_MASK 0x7
|
||||
+#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
|
||||
+#define RT3883_GPIO_MODE_UARTF 0x0
|
||||
+#define RT3883_GPIO_MODE_PCM_UARTF 0x1
|
||||
+#define RT3883_GPIO_MODE_PCM_I2S 0x2
|
||||
+#define RT3883_GPIO_MODE_I2S_UARTF 0x3
|
||||
+#define RT3883_GPIO_MODE_PCM_GPIO 0x4
|
||||
+#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
|
||||
+#define RT3883_GPIO_MODE_GPIO_I2S 0x6
|
||||
+#define RT3883_GPIO_MODE_GPIO 0x7
|
||||
+#define RT3883_GPIO_MODE_UART1 BIT(5)
|
||||
+#define RT3883_GPIO_MODE_JTAG BIT(6)
|
||||
+#define RT3883_GPIO_MODE_MDIO BIT(7)
|
||||
+#define RT3883_GPIO_MODE_GE1 BIT(9)
|
||||
+#define RT3883_GPIO_MODE_GE2 BIT(10)
|
||||
+#define RT3883_GPIO_MODE_PCI_SHIFT 11
|
||||
+#define RT3883_GPIO_MODE_PCI_MASK 0x7
|
||||
+#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
|
||||
+#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
|
||||
+#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
|
||||
+#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
|
||||
+#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
|
||||
+#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
|
||||
+#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
|
||||
+#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
|
||||
+#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
|
||||
+#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
|
||||
+#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
|
||||
+
|
||||
+#define RT3883_GPIO_I2C_SD 1
|
||||
+#define RT3883_GPIO_I2C_SCLK 2
|
||||
+#define RT3883_GPIO_SPI_CS0 3
|
||||
+#define RT3883_GPIO_SPI_CLK 4
|
||||
+#define RT3883_GPIO_SPI_MOSI 5
|
||||
+#define RT3883_GPIO_SPI_MISO 6
|
||||
+#define RT3883_GPIO_7 7
|
||||
+#define RT3883_GPIO_10 10
|
||||
+#define RT3883_GPIO_14 14
|
||||
+#define RT3883_GPIO_UART1_TXD 15
|
||||
+#define RT3883_GPIO_UART1_RXD 16
|
||||
+#define RT3883_GPIO_JTAG_TDO 17
|
||||
+#define RT3883_GPIO_JTAG_TDI 18
|
||||
+#define RT3883_GPIO_JTAG_TMS 19
|
||||
+#define RT3883_GPIO_JTAG_TCLK 20
|
||||
+#define RT3883_GPIO_JTAG_TRST_N 21
|
||||
+#define RT3883_GPIO_MDIO_MDC 22
|
||||
+#define RT3883_GPIO_MDIO_MDIO 23
|
||||
+#define RT3883_GPIO_LNA_PE_A0 32
|
||||
+#define RT3883_GPIO_LNA_PE_A1 33
|
||||
+#define RT3883_GPIO_LNA_PE_A2 34
|
||||
+#define RT3883_GPIO_LNA_PE_G0 35
|
||||
+#define RT3883_GPIO_LNA_PE_G1 36
|
||||
+#define RT3883_GPIO_LNA_PE_G2 37
|
||||
+#define RT3883_GPIO_PCI_AD0 40
|
||||
+#define RT3883_GPIO_PCI_AD31 71
|
||||
+#define RT3883_GPIO_GE2_TXD0 72
|
||||
+#define RT3883_GPIO_GE2_TXD1 73
|
||||
+#define RT3883_GPIO_GE2_TXD2 74
|
||||
+#define RT3883_GPIO_GE2_TXD3 75
|
||||
+#define RT3883_GPIO_GE2_TXEN 76
|
||||
+#define RT3883_GPIO_GE2_TXCLK 77
|
||||
+#define RT3883_GPIO_GE2_RXD0 78
|
||||
+#define RT3883_GPIO_GE2_RXD1 79
|
||||
+#define RT3883_GPIO_GE2_RXD2 80
|
||||
+#define RT3883_GPIO_GE2_RXD3 81
|
||||
+#define RT3883_GPIO_GE2_RXDV 82
|
||||
+#define RT3883_GPIO_GE2_RXCLK 83
|
||||
+#define RT3883_GPIO_GE1_TXD0 84
|
||||
+#define RT3883_GPIO_GE1_TXD1 85
|
||||
+#define RT3883_GPIO_GE1_TXD2 86
|
||||
+#define RT3883_GPIO_GE1_TXD3 87
|
||||
+#define RT3883_GPIO_GE1_TXEN 88
|
||||
+#define RT3883_GPIO_GE1_TXCLK 89
|
||||
+#define RT3883_GPIO_GE1_RXD0 90
|
||||
+#define RT3883_GPIO_GE1_RXD1 91
|
||||
+#define RT3883_GPIO_GE1_RXD2 92
|
||||
+#define RT3883_GPIO_GE1_RXD3 93
|
||||
+#define RT3883_GPIO_GE1_RXDV 94
|
||||
+#define RT3883_GPIO_GE1_RXCLK 95
|
||||
+
|
||||
+#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
|
||||
+#define RT3883_RSTCTRL_FLASH BIT(26)
|
||||
+#define RT3883_RSTCTRL_UDEV BIT(25)
|
||||
+#define RT3883_RSTCTRL_PCI BIT(24)
|
||||
+#define RT3883_RSTCTRL_PCIE BIT(23)
|
||||
+#define RT3883_RSTCTRL_UHST BIT(22)
|
||||
+#define RT3883_RSTCTRL_FE BIT(21)
|
||||
+#define RT3883_RSTCTRL_WLAN BIT(20)
|
||||
+#define RT3883_RSTCTRL_UART1 BIT(29)
|
||||
+#define RT3883_RSTCTRL_SPI BIT(18)
|
||||
+#define RT3883_RSTCTRL_I2S BIT(17)
|
||||
+#define RT3883_RSTCTRL_I2C BIT(16)
|
||||
+#define RT3883_RSTCTRL_NAND BIT(15)
|
||||
+#define RT3883_RSTCTRL_DMA BIT(14)
|
||||
+#define RT3883_RSTCTRL_PIO BIT(13)
|
||||
+#define RT3883_RSTCTRL_UART BIT(12)
|
||||
+#define RT3883_RSTCTRL_PCM BIT(11)
|
||||
+#define RT3883_RSTCTRL_MC BIT(10)
|
||||
+#define RT3883_RSTCTRL_INTC BIT(9)
|
||||
+#define RT3883_RSTCTRL_TIMER BIT(8)
|
||||
+#define RT3883_RSTCTRL_SYS BIT(0)
|
||||
+
|
||||
+#define RT3883_INTC_INT_SYSCTL BIT(0)
|
||||
+#define RT3883_INTC_INT_TIMER0 BIT(1)
|
||||
+#define RT3883_INTC_INT_TIMER1 BIT(2)
|
||||
+#define RT3883_INTC_INT_IA BIT(3)
|
||||
+#define RT3883_INTC_INT_PCM BIT(4)
|
||||
+#define RT3883_INTC_INT_UART0 BIT(5)
|
||||
+#define RT3883_INTC_INT_PIO BIT(6)
|
||||
+#define RT3883_INTC_INT_DMA BIT(7)
|
||||
+#define RT3883_INTC_INT_NAND BIT(8)
|
||||
+#define RT3883_INTC_INT_PERFC BIT(9)
|
||||
+#define RT3883_INTC_INT_I2S BIT(10)
|
||||
+#define RT3883_INTC_INT_UART1 BIT(12)
|
||||
+#define RT3883_INTC_INT_UHST BIT(18)
|
||||
+#define RT3883_INTC_INT_UDEV BIT(19)
|
||||
+
|
||||
+/* FLASH/SRAM/Codec Controller registers */
|
||||
+#define RT3883_FSCC_REG_FLASH_CFG0 0x00
|
||||
+#define RT3883_FSCC_REG_FLASH_CFG1 0x04
|
||||
+#define RT3883_FSCC_REG_CODEC_CFG0 0x40
|
||||
+#define RT3883_FSCC_REG_CODEC_CFG1 0x44
|
||||
+
|
||||
+#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
|
||||
+#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
|
||||
+#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
|
||||
+#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
|
||||
+#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
|
||||
+
|
||||
+#endif /* _RT3883_REGS_H_ */
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -15,6 +15,11 @@ choice
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
|
||||
+ config SOC_RT3883
|
||||
+ bool "RT3883"
|
||||
+ select USB_ARCH_HAS_OHCI
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
+
|
||||
endchoice
|
||||
|
||||
choice
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
+obj-$(CONFIG_SOC_RT3883) += rt3883.o
|
||||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff8
|
||||
# Ralink RT305x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
+
|
||||
+#
|
||||
+# Ralink RT3883
|
||||
+#
|
||||
+load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -0,0 +1,242 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+#include <asm/mipsregs.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+#include <asm/mach-ralink/rt3883.h>
|
||||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = RT3883_GPIO_MODE_I2C,
|
||||
+ .gpio_first = RT3883_GPIO_I2C_SD,
|
||||
+ .gpio_last = RT3883_GPIO_I2C_SCLK,
|
||||
+ }, {
|
||||
+ .name = "spi",
|
||||
+ .mask = RT3883_GPIO_MODE_SPI,
|
||||
+ .gpio_first = RT3883_GPIO_SPI_CS0,
|
||||
+ .gpio_last = RT3883_GPIO_SPI_MISO,
|
||||
+ }, {
|
||||
+ .name = "uartlite",
|
||||
+ .mask = RT3883_GPIO_MODE_UART1,
|
||||
+ .gpio_first = RT3883_GPIO_UART1_TXD,
|
||||
+ .gpio_last = RT3883_GPIO_UART1_RXD,
|
||||
+ }, {
|
||||
+ .name = "jtag",
|
||||
+ .mask = RT3883_GPIO_MODE_JTAG,
|
||||
+ .gpio_first = RT3883_GPIO_JTAG_TDO,
|
||||
+ .gpio_last = RT3883_GPIO_JTAG_TCLK,
|
||||
+ }, {
|
||||
+ .name = "mdio",
|
||||
+ .mask = RT3883_GPIO_MODE_MDIO,
|
||||
+ .gpio_first = RT3883_GPIO_MDIO_MDC,
|
||||
+ .gpio_last = RT3883_GPIO_MDIO_MDIO,
|
||||
+ }, {
|
||||
+ .name = "ge1",
|
||||
+ .mask = RT3883_GPIO_MODE_GE1,
|
||||
+ .gpio_first = RT3883_GPIO_GE1_TXD0,
|
||||
+ .gpio_last = RT3883_GPIO_GE1_RXCLK,
|
||||
+ }, {
|
||||
+ .name = "ge2",
|
||||
+ .mask = RT3883_GPIO_MODE_GE2,
|
||||
+ .gpio_first = RT3883_GPIO_GE2_TXD0,
|
||||
+ .gpio_last = RT3883_GPIO_GE2_RXCLK,
|
||||
+ }, {
|
||||
+ .name = "pci",
|
||||
+ .mask = RT3883_GPIO_MODE_PCI,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "lna a",
|
||||
+ .mask = RT3883_GPIO_MODE_LNA_A,
|
||||
+ .gpio_first = RT3883_GPIO_LNA_PE_A0,
|
||||
+ .gpio_last = RT3883_GPIO_LNA_PE_A2,
|
||||
+ }, {
|
||||
+ .name = "lna g",
|
||||
+ .mask = RT3883_GPIO_MODE_LNA_G,
|
||||
+ .gpio_first = RT3883_GPIO_LNA_PE_G0,
|
||||
+ .gpio_last = RT3883_GPIO_LNA_PE_G2,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
+ {
|
||||
+ .name = "uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_UARTF,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "pcm uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_PCM_UARTF,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "pcm i2s",
|
||||
+ .mask = RT3883_GPIO_MODE_PCM_I2S,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "i2s uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_I2S_UARTF,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "pcm gpio",
|
||||
+ .mask = RT3883_GPIO_MODE_PCM_GPIO,
|
||||
+ .gpio_first = RT3883_GPIO_11,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "gpio uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO_UARTF,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_10,
|
||||
+ }, {
|
||||
+ .name = "gpio i2s",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO_I2S,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_10,
|
||||
+ }, {
|
||||
+ .name = "gpio",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static struct ralink_pinmux_grp pci_mux[] = {
|
||||
+ {
|
||||
+ .name = "pci-dev",
|
||||
+ .mask = 0,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host2",
|
||||
+ .mask = 1,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host1",
|
||||
+ .mask = 2,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-fnc",
|
||||
+ .mask = 3,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-gpio",
|
||||
+ .mask = 7,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static void rt3883_wdt_reset(void)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ /* enable WDT reset output on GPIO 2 */
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
|
||||
+ t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
|
||||
+}
|
||||
+
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .uart = uart_mux,
|
||||
+ .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = RT3883_GPIO_MODE_GPIO,
|
||||
+ .wdt_reset = rt3883_wdt_reset,
|
||||
+ .pci = pci_mux,
|
||||
+ .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
|
||||
+ .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
|
||||
+};
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
||||
+{
|
||||
+ unsigned long cpu_rate, sys_rate;
|
||||
+ u32 syscfg0;
|
||||
+ u32 clksel;
|
||||
+ u32 ddr2;
|
||||
+
|
||||
+ syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
|
||||
+ clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
|
||||
+ RT3883_SYSCFG0_CPUCLK_MASK);
|
||||
+ ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
|
||||
+
|
||||
+ switch (clksel) {
|
||||
+ case RT3883_SYSCFG0_CPUCLK_250:
|
||||
+ cpu_rate = 250000000;
|
||||
+ sys_rate = (ddr2) ? 125000000 : 83000000;
|
||||
+ break;
|
||||
+ case RT3883_SYSCFG0_CPUCLK_384:
|
||||
+ cpu_rate = 384000000;
|
||||
+ sys_rate = (ddr2) ? 128000000 : 96000000;
|
||||
+ break;
|
||||
+ case RT3883_SYSCFG0_CPUCLK_480:
|
||||
+ cpu_rate = 480000000;
|
||||
+ sys_rate = (ddr2) ? 160000000 : 120000000;
|
||||
+ break;
|
||||
+ case RT3883_SYSCFG0_CPUCLK_500:
|
||||
+ cpu_rate = 500000000;
|
||||
+ sys_rate = (ddr2) ? 166000000 : 125000000;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ ralink_clk_add("cpu", cpu_rate);
|
||||
+ ralink_clk_add("10000100.timer", sys_rate);
|
||||
+ ralink_clk_add("10000120.watchdog", sys_rate);
|
||||
+ ralink_clk_add("10000500.uart", 40000000);
|
||||
+ ralink_clk_add("10000b00.spi", sys_rate);
|
||||
+ ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
+ ralink_clk_add("10100000.ethernet", sys_rate);
|
||||
+}
|
||||
+
|
||||
+void __init ralink_of_remap(void)
|
||||
+{
|
||||
+ rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
|
||||
+ rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
|
||||
+
|
||||
+ if (!rt_sysc_membase || !rt_memc_membase)
|
||||
+ panic("Failed to remap core resources");
|
||||
+}
|
||||
+
|
||||
+void prom_soc_init(struct ralink_soc_info *soc_info)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
|
||||
+ const char *name;
|
||||
+ u32 n0;
|
||||
+ u32 n1;
|
||||
+ u32 id;
|
||||
+
|
||||
+ n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
|
||||
+ n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
|
||||
+ id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
|
||||
+
|
||||
+ if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
|
||||
+ soc_info->compatible = "ralink,rt3883-soc";
|
||||
+ name = "RT3883";
|
||||
+ } else {
|
||||
+ panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
|
||||
+ }
|
||||
+
|
||||
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
|
||||
+ "Ralink %s ver:%u eco:%u",
|
||||
+ name,
|
||||
+ (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
|
||||
+ (id & RT3883_REVID_ECO_ID_MASK));
|
||||
+}
|
||||
|
|
@ -1,351 +0,0 @@
|
|||
From 878887d15bdee87366b7d3952d1c74c4b68a0782 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:49:02 +0100
|
||||
Subject: [PATCH 113/164] MIPS: ralink: adds support for MT7620 SoC family
|
||||
|
||||
Add support code for mt7620 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5177/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 76 ++++++++++
|
||||
arch/mips/ralink/Kconfig | 3 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/mt7620.c | 214 ++++++++++++++++++++++++++++
|
||||
5 files changed, 299 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
create mode 100644 arch/mips/ralink/mt7620.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -0,0 +1,76 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _MT7620_REGS_H_
|
||||
+#define _MT7620_REGS_H_
|
||||
+
|
||||
+#define MT7620_SYSC_BASE 0x10000000
|
||||
+
|
||||
+#define SYSC_REG_CHIP_NAME0 0x00
|
||||
+#define SYSC_REG_CHIP_NAME1 0x04
|
||||
+#define SYSC_REG_CHIP_REV 0x0c
|
||||
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
|
||||
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
|
||||
+#define SYSC_REG_CPLL_CONFIG0 0x54
|
||||
+#define SYSC_REG_CPLL_CONFIG1 0x58
|
||||
+
|
||||
+#define MT7620N_CHIP_NAME0 0x33365452
|
||||
+#define MT7620N_CHIP_NAME1 0x20203235
|
||||
+
|
||||
+#define MT7620A_CHIP_NAME0 0x3637544d
|
||||
+#define MT7620A_CHIP_NAME1 0x20203032
|
||||
+
|
||||
+#define CHIP_REV_PKG_MASK 0x1
|
||||
+#define CHIP_REV_PKG_SHIFT 16
|
||||
+#define CHIP_REV_VER_MASK 0xf
|
||||
+#define CHIP_REV_VER_SHIFT 8
|
||||
+#define CHIP_REV_ECO_MASK 0xf
|
||||
+
|
||||
+#define CPLL_SW_CONFIG_SHIFT 31
|
||||
+#define CPLL_SW_CONFIG_MASK 0x1
|
||||
+#define CPLL_CPU_CLK_SHIFT 24
|
||||
+#define CPLL_CPU_CLK_MASK 0x1
|
||||
+#define CPLL_MULT_RATIO_SHIFT 16
|
||||
+#define CPLL_MULT_RATIO 0x7
|
||||
+#define CPLL_DIV_RATIO_SHIFT 10
|
||||
+#define CPLL_DIV_RATIO 0x3
|
||||
+
|
||||
+#define SYSCFG0_DRAM_TYPE_MASK 0x3
|
||||
+#define SYSCFG0_DRAM_TYPE_SHIFT 4
|
||||
+#define SYSCFG0_DRAM_TYPE_SDRAM 0
|
||||
+#define SYSCFG0_DRAM_TYPE_DDR1 1
|
||||
+#define SYSCFG0_DRAM_TYPE_DDR2 2
|
||||
+
|
||||
+#define MT7620_GPIO_MODE_I2C BIT(0)
|
||||
+#define MT7620_GPIO_MODE_UART0_SHIFT 2
|
||||
+#define MT7620_GPIO_MODE_UART0_MASK 0x7
|
||||
+#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
|
||||
+#define MT7620_GPIO_MODE_UARTF 0x0
|
||||
+#define MT7620_GPIO_MODE_PCM_UARTF 0x1
|
||||
+#define MT7620_GPIO_MODE_PCM_I2S 0x2
|
||||
+#define MT7620_GPIO_MODE_I2S_UARTF 0x3
|
||||
+#define MT7620_GPIO_MODE_PCM_GPIO 0x4
|
||||
+#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
|
||||
+#define MT7620_GPIO_MODE_GPIO_I2S 0x6
|
||||
+#define MT7620_GPIO_MODE_GPIO 0x7
|
||||
+#define MT7620_GPIO_MODE_UART1 BIT(5)
|
||||
+#define MT7620_GPIO_MODE_MDIO BIT(8)
|
||||
+#define MT7620_GPIO_MODE_RGMII1 BIT(9)
|
||||
+#define MT7620_GPIO_MODE_RGMII2 BIT(10)
|
||||
+#define MT7620_GPIO_MODE_SPI BIT(11)
|
||||
+#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
|
||||
+#define MT7620_GPIO_MODE_WLED BIT(13)
|
||||
+#define MT7620_GPIO_MODE_JTAG BIT(15)
|
||||
+#define MT7620_GPIO_MODE_EPHY BIT(15)
|
||||
+#define MT7620_GPIO_MODE_WDT BIT(22)
|
||||
+
|
||||
+#endif
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -20,6 +20,9 @@ choice
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
|
||||
+ config SOC_MT7620
|
||||
+ bool "MT7620"
|
||||
+
|
||||
endchoice
|
||||
|
||||
choice
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
obj-$(CONFIG_SOC_RT3883) += rt3883.o
|
||||
+obj-$(CONFIG_SOC_MT7620) += mt7620.o
|
||||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff8
|
||||
# Ralink RT3883
|
||||
#
|
||||
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
+
|
||||
+#
|
||||
+# Ralink MT7620
|
||||
+#
|
||||
+load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -0,0 +1,214 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+#include <asm/mipsregs.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+#include <asm/mach-ralink/mt7620.h>
|
||||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+/* does the board have sdram or ddram */
|
||||
+static int dram_type;
|
||||
+
|
||||
+/* the pll dividers */
|
||||
+static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
|
||||
+
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = MT7620_GPIO_MODE_I2C,
|
||||
+ .gpio_first = 1,
|
||||
+ .gpio_last = 2,
|
||||
+ }, {
|
||||
+ .name = "spi",
|
||||
+ .mask = MT7620_GPIO_MODE_SPI,
|
||||
+ .gpio_first = 3,
|
||||
+ .gpio_last = 6,
|
||||
+ }, {
|
||||
+ .name = "uartlite",
|
||||
+ .mask = MT7620_GPIO_MODE_UART1,
|
||||
+ .gpio_first = 15,
|
||||
+ .gpio_last = 16,
|
||||
+ }, {
|
||||
+ .name = "wdt",
|
||||
+ .mask = MT7620_GPIO_MODE_WDT,
|
||||
+ .gpio_first = 17,
|
||||
+ .gpio_last = 17,
|
||||
+ }, {
|
||||
+ .name = "mdio",
|
||||
+ .mask = MT7620_GPIO_MODE_MDIO,
|
||||
+ .gpio_first = 22,
|
||||
+ .gpio_last = 23,
|
||||
+ }, {
|
||||
+ .name = "rgmii1",
|
||||
+ .mask = MT7620_GPIO_MODE_RGMII1,
|
||||
+ .gpio_first = 24,
|
||||
+ .gpio_last = 35,
|
||||
+ }, {
|
||||
+ .name = "spi refclk",
|
||||
+ .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
|
||||
+ .gpio_first = 37,
|
||||
+ .gpio_last = 39,
|
||||
+ }, {
|
||||
+ .name = "jtag",
|
||||
+ .mask = MT7620_GPIO_MODE_JTAG,
|
||||
+ .gpio_first = 40,
|
||||
+ .gpio_last = 44,
|
||||
+ }, {
|
||||
+ /* shared lines with jtag */
|
||||
+ .name = "ephy",
|
||||
+ .mask = MT7620_GPIO_MODE_EPHY,
|
||||
+ .gpio_first = 40,
|
||||
+ .gpio_last = 44,
|
||||
+ }, {
|
||||
+ .name = "nand",
|
||||
+ .mask = MT7620_GPIO_MODE_JTAG,
|
||||
+ .gpio_first = 45,
|
||||
+ .gpio_last = 59,
|
||||
+ }, {
|
||||
+ .name = "rgmii2",
|
||||
+ .mask = MT7620_GPIO_MODE_RGMII2,
|
||||
+ .gpio_first = 60,
|
||||
+ .gpio_last = 71,
|
||||
+ }, {
|
||||
+ .name = "wled",
|
||||
+ .mask = MT7620_GPIO_MODE_WLED,
|
||||
+ .gpio_first = 72,
|
||||
+ .gpio_last = 72,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
+ {
|
||||
+ .name = "uartf",
|
||||
+ .mask = MT7620_GPIO_MODE_UARTF,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "pcm uartf",
|
||||
+ .mask = MT7620_GPIO_MODE_PCM_UARTF,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "pcm i2s",
|
||||
+ .mask = MT7620_GPIO_MODE_PCM_I2S,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "i2s uartf",
|
||||
+ .mask = MT7620_GPIO_MODE_I2S_UARTF,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "pcm gpio",
|
||||
+ .mask = MT7620_GPIO_MODE_PCM_GPIO,
|
||||
+ .gpio_first = 11,
|
||||
+ .gpio_last = 14,
|
||||
+ }, {
|
||||
+ .name = "gpio uartf",
|
||||
+ .mask = MT7620_GPIO_MODE_GPIO_UARTF,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 10,
|
||||
+ }, {
|
||||
+ .name = "gpio i2s",
|
||||
+ .mask = MT7620_GPIO_MODE_GPIO_I2S,
|
||||
+ .gpio_first = 7,
|
||||
+ .gpio_last = 10,
|
||||
+ }, {
|
||||
+ .name = "gpio",
|
||||
+ .mask = MT7620_GPIO_MODE_GPIO,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .uart = uart_mux,
|
||||
+ .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = MT7620_GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
||||
+{
|
||||
+ unsigned long cpu_rate, sys_rate;
|
||||
+ u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
|
||||
+ u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
|
||||
+ u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
|
||||
+ u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
|
||||
+
|
||||
+ if (cpu_clk) {
|
||||
+ cpu_rate = 480000000;
|
||||
+ } else if (!swconfig) {
|
||||
+ cpu_rate = 600000000;
|
||||
+ } else {
|
||||
+ u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
|
||||
+ u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
|
||||
+
|
||||
+ cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
|
||||
+ }
|
||||
+
|
||||
+ if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
|
||||
+ sys_rate = cpu_rate / 4;
|
||||
+ else
|
||||
+ sys_rate = cpu_rate / 3;
|
||||
+
|
||||
+ ralink_clk_add("cpu", cpu_rate);
|
||||
+ ralink_clk_add("10000100.timer", 40000000);
|
||||
+ ralink_clk_add("10000500.uart", 40000000);
|
||||
+ ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
+}
|
||||
+
|
||||
+void __init ralink_of_remap(void)
|
||||
+{
|
||||
+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
|
||||
+ rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
|
||||
+
|
||||
+ if (!rt_sysc_membase || !rt_memc_membase)
|
||||
+ panic("Failed to remap core resources");
|
||||
+}
|
||||
+
|
||||
+void prom_soc_init(struct ralink_soc_info *soc_info)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
|
||||
+ unsigned char *name = NULL;
|
||||
+ u32 n0;
|
||||
+ u32 n1;
|
||||
+ u32 rev;
|
||||
+ u32 cfg0;
|
||||
+
|
||||
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||||
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||||
+
|
||||
+ if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
|
||||
+ name = "MT7620N";
|
||||
+ soc_info->compatible = "ralink,mt7620n-soc";
|
||||
+ } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
|
||||
+ name = "MT7620A";
|
||||
+ soc_info->compatible = "ralink,mt7620a-soc";
|
||||
+ } else {
|
||||
+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
|
||||
+ }
|
||||
+
|
||||
+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
|
||||
+
|
||||
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
|
||||
+ "Ralink %s ver:%u eco:%u",
|
||||
+ name,
|
||||
+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
|
||||
+ (rev & CHIP_REV_ECO_MASK));
|
||||
+
|
||||
+ cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
|
||||
+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
|
||||
+}
|
||||
|
|
@ -1,218 +0,0 @@
|
|||
From f5d5b8b69f5b11fdd810a1a56eff91077ad5ba84 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 10 Apr 2013 09:19:07 +0200
|
||||
Subject: [PATCH 114/164] MIPS: ralink: add cpu-feature-overrides.h
|
||||
|
||||
Add cpu-feature-overrides.h for RT288x, RT305x and RT3883.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5175/
|
||||
---
|
||||
.../asm/mach-ralink/rt288x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
.../asm/mach-ralink/rt305x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
.../asm/mach-ralink/rt3883/cpu-feature-overrides.h | 55 +++++++++++++++++++
|
||||
arch/mips/ralink/Platform | 3 ++
|
||||
4 files changed, 170 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT288x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 0
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 16
|
||||
+#define cpu_icache_line_size() 16
|
||||
+
|
||||
+#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT305x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -8,16 +8,19 @@ cflags-$(CONFIG_RALINK) += -I$(srctree)
|
||||
# Ralink RT288x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
|
||||
+cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
|
||||
|
||||
#
|
||||
# Ralink RT305x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
|
||||
|
||||
#
|
||||
# Ralink RT3883
|
||||
#
|
||||
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
|
||||
|
||||
#
|
||||
# Ralink MT7620
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
From 94299fd468be1bcac63eb159a7f280f3bc0351ec Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 10:11:51 +0200
|
||||
Subject: [PATCH 115/164] DT: add vendor prefixes for Ralink
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
---
|
||||
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
|
||||
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
|
||||
@@ -41,6 +41,7 @@ onnn ON Semiconductor Corp.
|
||||
picochip Picochip Ltd
|
||||
powervr PowerVR (deprecated, use img)
|
||||
qcom Qualcomm, Inc.
|
||||
+ralink Mediatek/Ralink Technology Corp.
|
||||
ramtron Ramtron International
|
||||
realtek Realtek Semiconductor Corp.
|
||||
renesas Renesas Electronics Corporation
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
From f8ad9ce9fceec8ffa986ac44c52ead3f6adade1e Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 09:02:40 +0200
|
||||
Subject: [PATCH 116/164] DT: add documentation for the Ralink MIPS SoCs
|
||||
|
||||
This patch adds binding documentation for the
|
||||
compatible values of the Ralink MIPS SoCs.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5187/
|
||||
---
|
||||
Documentation/devicetree/bindings/mips/ralink.txt | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/mips/ralink.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
|
||||
@@ -0,0 +1,18 @@
|
||||
+Ralink MIPS SoC device tree bindings
|
||||
+
|
||||
+1. SoCs
|
||||
+
|
||||
+Each device tree must specify a compatible value for the Ralink SoC
|
||||
+it uses in the compatible property of the root node. The compatible
|
||||
+value must be one of the following values:
|
||||
+
|
||||
+ ralink,rt2880-soc
|
||||
+ ralink,rt3050-soc
|
||||
+ ralink,rt3052-soc
|
||||
+ ralink,rt3350-soc
|
||||
+ ralink,rt3352-soc
|
||||
+ ralink,rt3883-soc
|
||||
+ ralink,rt5350-soc
|
||||
+ ralink,mt7620a-soc
|
||||
+ ralink,mt7620n-soc
|
||||
+
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
From 0f26ec753f34e16e00d25c576a190765aedd62c9 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:47:07 +0100
|
||||
Subject: [PATCH 117/164] DT: MIPS: ralink: clean up RT3050 dtsi and dts file
|
||||
|
||||
* remove nodes for cores whose drivers are not upstream yet
|
||||
* add compat string for an additional soc
|
||||
* fix a whitespace error
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5186/
|
||||
---
|
||||
arch/mips/ralink/dts/rt3050.dtsi | 52 ++--------------------------------
|
||||
arch/mips/ralink/dts/rt3052_eval.dts | 10 ++-----
|
||||
2 files changed, 4 insertions(+), 58 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/dts/rt3050.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt3050.dtsi
|
||||
@@ -1,7 +1,7 @@
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
|
||||
+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
@@ -9,10 +9,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- chosen {
|
||||
- bootargs = "console=ttyS0,57600 init=/init";
|
||||
- };
|
||||
-
|
||||
cpuintc: cpuintc@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
@@ -23,7 +19,7 @@
|
||||
palmbus@10000000 {
|
||||
compatible = "palmbus";
|
||||
reg = <0x10000000 0x200000>;
|
||||
- ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -33,11 +29,6 @@
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
- timer@100 {
|
||||
- compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
|
||||
- reg = <0x100 0x100>;
|
||||
- };
|
||||
-
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
@@ -54,45 +45,6 @@
|
||||
reg = <0x300 0x100>;
|
||||
};
|
||||
|
||||
- gpio0: gpio@600 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x600 0x34>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <24>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 20 24 28 2c
|
||||
- 30 34 ];
|
||||
- };
|
||||
-
|
||||
- gpio1: gpio@638 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x638 0x24>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <16>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 10 14 18 1c
|
||||
- 20 24 ];
|
||||
- };
|
||||
-
|
||||
- gpio2: gpio@660 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x660 0x24>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <12>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 10 14 18 1c
|
||||
- 20 24 ];
|
||||
- };
|
||||
-
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
--- a/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
@@ -3,8 +3,6 @@
|
||||
/include/ "rt3050.dtsi"
|
||||
|
||||
/ {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
|
||||
model = "Ralink RT3052 evaluation board";
|
||||
|
||||
@@ -12,12 +10,8 @@
|
||||
reg = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
- palmbus@10000000 {
|
||||
- sysc@0 {
|
||||
- ralink,pinmmux = "uartlite", "spi";
|
||||
- ralink,uartmux = "gpio";
|
||||
- ralink,wdtmux = <0>;
|
||||
- };
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
};
|
||||
|
||||
cfi@1f000000 {
|
||||
|
|
@ -1,147 +0,0 @@
|
|||
From f88ca014e92cf209c0e5b6f68b45e3ca0ada6c45 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:37 +0000
|
||||
Subject: [PATCH 118/164] DT: MIPS: ralink: add RT2880 dts files
|
||||
|
||||
Add a dtsi file for RT2880 SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5188/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt2880.dtsi | 58 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt2880_eval.dts | 46 +++++++++++++++++++++++++++
|
||||
4 files changed, 109 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -34,6 +34,10 @@ choice
|
||||
config DTB_RT_NONE
|
||||
bool "None"
|
||||
|
||||
+ config DTB_RT2880_EVAL
|
||||
+ bool "RT2880 eval kit"
|
||||
+ depends on SOC_RT288X
|
||||
+
|
||||
config DTB_RT305X_EVAL
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1 +1,2 @@
|
||||
+obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt2880-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips4KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@300000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x300000 0x200000>;
|
||||
+ ranges = <0x0 0x300000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt2880-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt2880-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <8>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
|
||||
@@ -0,0 +1,46 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt2880.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
|
||||
+ model = "Ralink RT2880 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x8000000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+
|
||||
+ cfi@1f000000 {
|
||||
+ compatible = "cfi-flash";
|
||||
+ reg = <0x1f000000 0x400000>;
|
||||
+
|
||||
+ bank-width = <2>;
|
||||
+ device-width = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@30000 {
|
||||
+ label = "uboot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@40000 {
|
||||
+ label = "calibration";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@50000 {
|
||||
+ label = "linux";
|
||||
+ reg = <0x50000 0x3b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
From 20c94bd844c5743d58ad8d8df81460e049f9df4b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:39 +0000
|
||||
Subject: [PATCH 119/164] DT: MIPS: ralink: add RT3883 dts files
|
||||
|
||||
Add a dtsi file for RT3883 SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5189/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt3883.dtsi | 58 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt3883_eval.dts | 16 ++++++++++
|
||||
4 files changed, 79 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -42,6 +42,10 @@ choice
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
|
||||
+ config DTB_RT3883_EVAL
|
||||
+ bool "RT3883 eval kit"
|
||||
+ depends on SOC_RT3883
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt3883-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips74Kc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt3883.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
|
||||
+ model = "Ralink RT3883 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
From 248c7a2b678eee7da39363b1f097ea7eedceb435 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:41 +0000
|
||||
Subject: [PATCH 120/164] DT: MIPS: ralink: add MT7620A dts files
|
||||
|
||||
Add a dtsi file for MT7620A SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5190/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/mt7620a.dtsi | 58 +++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/mt7620a_eval.dts | 16 +++++++++
|
||||
4 files changed, 79 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620a.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -46,6 +46,10 @@ choice
|
||||
bool "RT3883 eval kit"
|
||||
depends on SOC_RT3883
|
||||
|
||||
+ config DTB_MT7620A_EVAL
|
||||
+ bool "MT7620A eval kit"
|
||||
+ depends on SOC_MT7620
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,3 +1,4 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,mtk7620a-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,mt7620a-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "mt7620a.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
|
||||
+ model = "Ralink MT7620A evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
From 2ccca2ac0b54eb21890412c888cf5a5bda656bba Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 13:15:47 +0200
|
||||
Subject: [PATCH 121/164] MIPS: add detect_memory_region()
|
||||
|
||||
Add a generic way of detecting the available RAM. This function is based on the
|
||||
implementation already used by ath79.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5178/
|
||||
---
|
||||
arch/mips/include/asm/bootinfo.h | 1 +
|
||||
arch/mips/kernel/setup.c | 20 ++++++++++++++++++++
|
||||
2 files changed, 21 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/bootinfo.h
|
||||
+++ b/arch/mips/include/asm/bootinfo.h
|
||||
@@ -104,6 +104,7 @@ struct boot_mem_map {
|
||||
extern struct boot_mem_map boot_mem_map;
|
||||
|
||||
extern void add_memory_region(phys_t start, phys_t size, long type);
|
||||
+extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max);
|
||||
|
||||
extern void prom_init(void);
|
||||
extern void prom_free_prom_memory(void);
|
||||
--- a/arch/mips/kernel/setup.c
|
||||
+++ b/arch/mips/kernel/setup.c
|
||||
@@ -23,6 +23,7 @@
|
||||
#include <linux/pfn.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/kexec.h>
|
||||
+#include <linux/sizes.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
@@ -122,6 +123,25 @@ void __init add_memory_region(phys_t sta
|
||||
boot_mem_map.nr_map++;
|
||||
}
|
||||
|
||||
+void __init detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max)
|
||||
+{
|
||||
+ phys_t size;
|
||||
+
|
||||
+ for (size = sz_min; size < sz_max; size <<= 1) {
|
||||
+ if (!memcmp(detect_memory_region,
|
||||
+ detect_memory_region + size, 1024))
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
|
||||
+ ((unsigned long long) size) / SZ_1M,
|
||||
+ (unsigned long long) start,
|
||||
+ ((unsigned long long) sz_min) / SZ_1M,
|
||||
+ ((unsigned long long) sz_max) / SZ_1M);
|
||||
+
|
||||
+ add_memory_region(start, size, BOOT_MEM_RAM);
|
||||
+}
|
||||
+
|
||||
static void __init print_memory_map(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
From 438579e0fd477cec8584bdf012ea51cf4ad8e05c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:10:14 +0200
|
||||
Subject: [PATCH 122/164] MIPS: ralink: add memory definition to struct
|
||||
ralink_soc_info
|
||||
|
||||
Depending on the actual SoC we have a different base address as well as minimum
|
||||
and maximum size for RAM. Add these fields to the per SoC structure.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5179/
|
||||
---
|
||||
arch/mips/ralink/common.h | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -33,6 +33,11 @@ extern struct ralink_pinmux rt_gpio_pinm
|
||||
struct ralink_soc_info {
|
||||
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
|
||||
unsigned char *compatible;
|
||||
+
|
||||
+ unsigned long mem_base;
|
||||
+ unsigned long mem_size;
|
||||
+ unsigned long mem_size_min;
|
||||
+ unsigned long mem_size_max;
|
||||
};
|
||||
extern struct ralink_soc_info soc_info;
|
||||
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
From 1a255c5e67baad1735f985ad818d2b970fcc6808 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:13:40 +0200
|
||||
Subject: [PATCH 123/164] MIPS: ralink: add memory definition for RT305x
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
As memory detection fails on RT5350 we read the amount of available memory
|
||||
from the system controller.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5180/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt305x.h | 6 ++++
|
||||
arch/mips/ralink/rt305x.c | 45 ++++++++++++++++++++++++++++
|
||||
2 files changed, 51 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
|
||||
@@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
|
||||
#define RT3352_RSTCTRL_UDEV BIT(25)
|
||||
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
|
||||
|
||||
+#define RT305X_SDRAM_BASE 0x00000000
|
||||
+#define RT305X_MEM_SIZE_MIN 2
|
||||
+#define RT305X_MEM_SIZE_MAX 64
|
||||
+#define RT3352_MEM_SIZE_MIN 2
|
||||
+#define RT3352_MEM_SIZE_MAX 256
|
||||
+
|
||||
#endif
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.wdt_reset = rt305x_wdt_reset,
|
||||
};
|
||||
|
||||
+static unsigned long rt5350_get_mem_size(void)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
|
||||
+ unsigned long ret;
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
|
||||
+ t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
|
||||
+ RT5350_SYSCFG0_DRAM_SIZE_MASK;
|
||||
+
|
||||
+ switch (t) {
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_2M:
|
||||
+ ret = 2;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_8M:
|
||||
+ ret = 8;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_16M:
|
||||
+ ret = 16;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_32M:
|
||||
+ ret = 32;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_64M:
|
||||
+ ret = 64;
|
||||
+ break;
|
||||
+ default:
|
||||
+ panic("rt5350: invalid DRAM size: %u", t);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
void __init ralink_clk_init(void)
|
||||
{
|
||||
unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
|
||||
@@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
|
||||
(id & CHIP_ID_REV_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT305X_SDRAM_BASE;
|
||||
+ if (soc_is_rt5350()) {
|
||||
+ soc_info->mem_size = rt5350_get_mem_size();
|
||||
+ } else if (soc_is_rt305x() || soc_is_rt3350()) {
|
||||
+ soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
|
||||
+ } else if (soc_is_rt3352()) {
|
||||
+ soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
|
||||
+ }
|
||||
}
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
From 45529406ea5b481da5986e0a14ae26a8c103691b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:37:37 +0200
|
||||
Subject: [PATCH 124/164] MIPS: ralink: add memory definition for RT2880
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5181/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt288x.h | 4 ++++
|
||||
arch/mips/ralink/rt288x.c | 4 ++++
|
||||
2 files changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
@@ -46,4 +46,8 @@
|
||||
|
||||
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
|
||||
|
||||
+#define RT2880_SDRAM_BASE 0x08000000
|
||||
+#define RT2880_MEM_SIZE_MIN 2
|
||||
+#define RT2880_MEM_SIZE_MAX 128
|
||||
+
|
||||
#endif
|
||||
--- a/arch/mips/ralink/rt288x.c
|
||||
+++ b/arch/mips/ralink/rt288x.c
|
||||
@@ -136,4 +136,8 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
|
||||
(id & CHIP_ID_REV_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT2880_SDRAM_BASE;
|
||||
+ soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
|
||||
}
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
From d771f446558ef408ca97c391887ae843dd23c358 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 20:23:19 +0200
|
||||
Subject: [PATCH 125/164] MIPS: ralink: add memory definition for RT3883
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5182/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt3883.h | 5 +++++
|
||||
arch/mips/ralink/rt3883.c | 4 ++++
|
||||
2 files changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
@@ -152,6 +152,7 @@
|
||||
#define RT3883_GPIO_SPI_MISO 6
|
||||
#define RT3883_GPIO_7 7
|
||||
#define RT3883_GPIO_10 10
|
||||
+#define RT3883_GPIO_11 11
|
||||
#define RT3883_GPIO_14 14
|
||||
#define RT3883_GPIO_UART1_TXD 15
|
||||
#define RT3883_GPIO_UART1_RXD 16
|
||||
@@ -244,4 +245,8 @@
|
||||
#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
|
||||
#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
|
||||
|
||||
+#define RT3883_SDRAM_BASE 0x00000000
|
||||
+#define RT3883_MEM_SIZE_MIN 2
|
||||
+#define RT3883_MEM_SIZE_MAX 256
|
||||
+
|
||||
#endif /* _RT3883_REGS_H_ */
|
||||
--- a/arch/mips/ralink/rt3883.c
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -239,4 +239,8 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
|
||||
(id & RT3883_REVID_ECO_ID_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT3883_SDRAM_BASE;
|
||||
+ soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
|
||||
}
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
From 0c6c7304e33f3decff3293739076f29314ce535e Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 14 Apr 2013 09:55:29 +0200
|
||||
Subject: [PATCH 126/164] MIPS: ralink: add memory definition for MT7620
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5183/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 8 ++++++++
|
||||
arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++
|
||||
2 files changed, 28 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -50,6 +50,14 @@
|
||||
#define SYSCFG0_DRAM_TYPE_DDR1 1
|
||||
#define SYSCFG0_DRAM_TYPE_DDR2 2
|
||||
|
||||
+#define MT7620_DRAM_BASE 0x0
|
||||
+#define MT7620_SDRAM_SIZE_MIN 2
|
||||
+#define MT7620_SDRAM_SIZE_MAX 64
|
||||
+#define MT7620_DDR1_SIZE_MIN 32
|
||||
+#define MT7620_DDR1_SIZE_MAX 128
|
||||
+#define MT7620_DDR2_SIZE_MIN 32
|
||||
+#define MT7620_DDR2_SIZE_MAX 256
|
||||
+
|
||||
#define MT7620_GPIO_MODE_I2C BIT(0)
|
||||
#define MT7620_GPIO_MODE_UART0_SHIFT 2
|
||||
#define MT7620_GPIO_MODE_UART0_MASK 0x7
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
|
||||
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
|
||||
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
|
||||
+
|
||||
+ switch (dram_type) {
|
||||
+ case SYSCFG0_DRAM_TYPE_SDRAM:
|
||||
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
||||
+ break;
|
||||
+
|
||||
+ case SYSCFG0_DRAM_TYPE_DDR1:
|
||||
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
||||
+ break;
|
||||
+
|
||||
+ case SYSCFG0_DRAM_TYPE_DDR2:
|
||||
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
||||
+ break;
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+ soc_info->mem_base = MT7620_DRAM_BASE;
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
From 550797902b0285736caceaf3c01506077d5440ea Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:15:51 +0200
|
||||
Subject: [PATCH 127/164] MIPS: ralink: make use of the new memory detection
|
||||
code
|
||||
|
||||
Call detect_memory_region() from plat_mem_setup() unless the size was already
|
||||
read from the system controller.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5184/
|
||||
---
|
||||
arch/mips/ralink/of.c | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/sizes.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bootmem.h>
|
||||
@@ -85,6 +86,14 @@ void __init plat_mem_setup(void)
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
__dt_setup_arch(&__dtb_start);
|
||||
+
|
||||
+ if (soc_info.mem_size)
|
||||
+ add_memory_region(soc_info.mem_base, soc_info.mem_size,
|
||||
+ BOOT_MEM_RAM);
|
||||
+ else
|
||||
+ detect_memory_region(soc_info.mem_base,
|
||||
+ soc_info.mem_size_min * SZ_1M,
|
||||
+ soc_info.mem_size_max * SZ_1M);
|
||||
}
|
||||
|
||||
static int __init plat_of_setup(void)
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
From b3c76fc6b7be5aa2514a268e405e9b6e1c3ebcf0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 30 May 2013 16:16:13 +0200
|
||||
Subject: [PATCH 128/164] MIPS: ralink: upstream v3.10
|
||||
|
||||
patches prior to this were sent upstream and accepted for v3.10
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
dummy | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
create mode 100644 dummy
|
||||
|
||||
--- /dev/null
|
||||
+++ b/dummy
|
||||
@@ -0,0 +1 @@
|
||||
+dummy
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
From 596c13f9c14edfe1ed71fe64274825c1978c964c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 22 Apr 2013 23:11:42 +0200
|
||||
Subject: [PATCH 129/164] MIPS: ralink: add pinmux driver
|
||||
|
||||
Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
|
||||
for this functionality with simple on/off bits. Building a full featured pinctrl
|
||||
driver would be overkill.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/common.h | 2 ++
|
||||
arch/mips/ralink/of.c | 2 ++
|
||||
arch/mips/ralink/pinmux.c | 77 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
4 files changed, 82 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/ralink/pinmux.c
|
||||
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -6,7 +6,7 @@
|
||||
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
|
||||
-obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -50,4 +50,6 @@ extern void prom_soc_init(struct ralink_
|
||||
|
||||
__iomem void *plat_of_remap_node(const char *node);
|
||||
|
||||
+void ralink_pinmux(void);
|
||||
+
|
||||
#endif /* _RALINK_COMMON_H__ */
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -110,6 +110,8 @@ static int __init plat_of_setup(void)
|
||||
if (of_platform_populate(NULL, of_ids, NULL, NULL))
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
+ ralink_pinmux();
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/pinmux.c
|
||||
@@ -0,0 +1,77 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/of.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+#define SYSC_REG_GPIO_MODE 0x60
|
||||
+
|
||||
+static int ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps, u32* mask)
|
||||
+{
|
||||
+ for (; grps && grps->name; grps++)
|
||||
+ if (!strcmp(grps->name, name)) {
|
||||
+ *mask = grps->mask;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+void ralink_pinmux(void)
|
||||
+{
|
||||
+ const __be32 *wdt;
|
||||
+ struct device_node *np;
|
||||
+ struct property *prop;
|
||||
+ const char *uart, *pin;
|
||||
+ u32 mode = 0;
|
||||
+ int m;
|
||||
+
|
||||
+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
|
||||
+ if (!np)
|
||||
+ return;
|
||||
+
|
||||
+ of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
|
||||
+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
|
||||
+ mode |= m;
|
||||
+ pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
|
||||
+ } else {
|
||||
+ pr_err("pinmux: failed to load \"%s\"\n", pin);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
|
||||
+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
|
||||
+ mode &= ~m;
|
||||
+ pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
|
||||
+ } else {
|
||||
+ pr_err("pinmux: failed to load group \"%s\"\n", pin);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ of_property_read_string(np, "ralink,uartmux", &uart);
|
||||
+ if (uart) {
|
||||
+ mode &= ~(rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift);
|
||||
+ if (ralink_mux_mask(uart, rt_gpio_pinmux.uart, &m)) {
|
||||
+ pr_err("pinmux: failed to load uartmux \"%s\"\n", uart);
|
||||
+ mode |= rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift;
|
||||
+ } else {
|
||||
+ mode |= m << rt_gpio_pinmux.uart_shift;
|
||||
+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ wdt = of_get_property(np, "ralink,wdtmux", NULL);
|
||||
+ if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
|
||||
+ rt_gpio_pinmux.wdt_reset();
|
||||
+
|
||||
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
|
||||
+}
|
||||
|
|
@ -1,220 +0,0 @@
|
|||
From f8496dd6c8fbcfd159390c31791fe2a86e48acb9 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 23 Mar 2013 19:44:41 +0100
|
||||
Subject: [PATCH 130/164] MIPS: ralink: add support for periodic timer irq
|
||||
|
||||
Adds a driver for the periodic timer found on Ralink SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/timer.c | 192 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 193 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/ralink/timer.c
|
||||
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -6,7 +6,7 @@
|
||||
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
|
||||
-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
|
||||
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/timer.c
|
||||
@@ -0,0 +1,192 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+*/
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/timer.h>
|
||||
+#include <linux/of_gpio.h>
|
||||
+#include <linux/clk.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define TIMER_REG_TMRSTAT 0x00
|
||||
+#define TIMER_REG_TMR0LOAD 0x10
|
||||
+#define TIMER_REG_TMR0CTL 0x18
|
||||
+
|
||||
+#define TMRSTAT_TMR0INT BIT(0)
|
||||
+
|
||||
+#define TMR0CTL_ENABLE BIT(7)
|
||||
+#define TMR0CTL_MODE_PERIODIC BIT(4)
|
||||
+#define TMR0CTL_PRESCALER 1
|
||||
+#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
|
||||
+#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
|
||||
+
|
||||
+struct rt_timer {
|
||||
+ struct device *dev;
|
||||
+ void __iomem *membase;
|
||||
+ int irq;
|
||||
+ unsigned long timer_freq;
|
||||
+ unsigned long timer_div;
|
||||
+};
|
||||
+
|
||||
+static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
|
||||
+{
|
||||
+ __raw_writel(val, rt->membase + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
|
||||
+{
|
||||
+ return __raw_readl(rt->membase + reg);
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t rt_timer_irq(int irq, void *_rt)
|
||||
+{
|
||||
+ struct rt_timer *rt = (struct rt_timer *) _rt;
|
||||
+
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int rt_timer_request(struct rt_timer *rt)
|
||||
+{
|
||||
+ int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
|
||||
+ dev_name(rt->dev), rt);
|
||||
+ if (err) {
|
||||
+ dev_err(rt->dev, "failed to request irq\n");
|
||||
+ } else {
|
||||
+ u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
|
||||
+ }
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static void rt_timer_free(struct rt_timer *rt)
|
||||
+{
|
||||
+ free_irq(rt->irq, rt);
|
||||
+}
|
||||
+
|
||||
+static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
|
||||
+{
|
||||
+ if (rt->timer_freq < divisor)
|
||||
+ rt->timer_div = rt->timer_freq;
|
||||
+ else
|
||||
+ rt->timer_div = divisor;
|
||||
+
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt_timer_enable(struct rt_timer *rt)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
|
||||
+
|
||||
+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
|
||||
+ t |= TMR0CTL_ENABLE;
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rt_timer_disable(struct rt_timer *rt)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
|
||||
+ t &= ~TMR0CTL_ENABLE;
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
|
||||
+}
|
||||
+
|
||||
+static int rt_timer_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ struct rt_timer *rt;
|
||||
+ struct clk *clk;
|
||||
+
|
||||
+ if (!res) {
|
||||
+ dev_err(&pdev->dev, "no memory resource found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
|
||||
+ if (!rt) {
|
||||
+ dev_err(&pdev->dev, "failed to allocate memory\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ rt->irq = platform_get_irq(pdev, 0);
|
||||
+ if (!rt->irq) {
|
||||
+ dev_err(&pdev->dev, "failed to load irq\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+ rt->membase = devm_request_and_ioremap(&pdev->dev, res);
|
||||
+ if (!rt->membase) {
|
||||
+ dev_err(&pdev->dev, "failed to ioremap\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ dev_err(&pdev->dev, "failed get clock rate\n");
|
||||
+ return PTR_ERR(clk);
|
||||
+ }
|
||||
+
|
||||
+ rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
|
||||
+ if (!rt->timer_freq)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ rt->dev = &pdev->dev;
|
||||
+ platform_set_drvdata(pdev, rt);
|
||||
+
|
||||
+ rt_timer_request(rt);
|
||||
+ rt_timer_config(rt, 2);
|
||||
+ rt_timer_enable(rt);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt_timer_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct rt_timer *rt = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ rt_timer_disable(rt);
|
||||
+ rt_timer_free(rt);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt_timer_match[] = {
|
||||
+ { .compatible = "ralink,rt2880-timer" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt_timer_match);
|
||||
+
|
||||
+static struct platform_driver rt_timer_driver = {
|
||||
+ .probe = rt_timer_probe,
|
||||
+ .remove = rt_timer_remove,
|
||||
+ .driver = {
|
||||
+ .name = "rt-timer",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = rt_timer_match
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(rt_timer_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Ralink RT2880 timer");
|
||||
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
|
||||
+MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From d685ede166d4ab4f098c2a334e0d03854522f507 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 19 May 2013 00:42:23 +0200
|
||||
Subject: [PATCH 131/164] MIPS: ralink: add rt_sysc_m32 helper
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/ralink_regs.h | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
|
||||
@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r
|
||||
return __raw_readl(rt_sysc_membase + reg);
|
||||
}
|
||||
|
||||
+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
|
||||
+{
|
||||
+ u32 val = rt_sysc_r32(reg) & ~clr;
|
||||
+
|
||||
+ __raw_writel(val | set, rt_sysc_membase + reg);
|
||||
+}
|
||||
+
|
||||
static inline void rt_memc_w32(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt_memc_membase + reg);
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
From eb6f94f9d53a0eecf0ff8edd5318ee2dd5403a01 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 20 May 2013 20:30:11 +0200
|
||||
Subject: [PATCH 132/164] MIPS: ralink: make mt7620 ram detect verbose
|
||||
|
||||
Make the code print which of SDRAM, DDR1 or DDR2 was detected.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/mt7620.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
|
||||
switch (dram_type) {
|
||||
case SYSCFG0_DRAM_TYPE_SDRAM:
|
||||
+ pr_info("Board has SDRAM\n");
|
||||
soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
||||
soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
||||
break;
|
||||
|
||||
case SYSCFG0_DRAM_TYPE_DDR1:
|
||||
+ pr_info("Board has DDR1\n");
|
||||
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
||||
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
||||
break;
|
||||
|
||||
case SYSCFG0_DRAM_TYPE_DDR2:
|
||||
+ pr_info("Board has DDR2\n");
|
||||
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
||||
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
||||
break;
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
From c7150f86dfb0fe2613af3c5bd1c0c587130b9460 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 20 May 2013 20:57:09 +0200
|
||||
Subject: [PATCH 133/164] MIPS: ralink: add verbose pmu info
|
||||
|
||||
Print the PMU and LDO settings on boot.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -20,6 +20,22 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
+/* analog */
|
||||
+#define PMU0_CFG 0x88
|
||||
+#define PMU_SW_SET BIT(28)
|
||||
+#define A_DCDC_EN BIT(24)
|
||||
+#define A_SSC_PERI BIT(19)
|
||||
+#define A_SSC_GEN BIT(18)
|
||||
+#define A_SSC_M 0x3
|
||||
+#define A_SSC_S 16
|
||||
+#define A_DLY_M 0x7
|
||||
+#define A_DLY_S 8
|
||||
+#define A_VTUNE_M 0xff
|
||||
+
|
||||
+/* digital */
|
||||
+#define PMU1_CFG 0x8C
|
||||
+#define DIG_SW_SEL BIT(25)
|
||||
+
|
||||
/* does the board have sdram or ddram */
|
||||
static int dram_type;
|
||||
|
||||
@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
u32 n1;
|
||||
u32 rev;
|
||||
u32 cfg0;
|
||||
+ u32 pmu0;
|
||||
+ u32 pmu1;
|
||||
|
||||
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||||
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||||
@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
BUG();
|
||||
}
|
||||
soc_info->mem_base = MT7620_DRAM_BASE;
|
||||
+
|
||||
+ pmu0 = __raw_readl(sysc + PMU0_CFG);
|
||||
+ pmu1 = __raw_readl(sysc + PMU1_CFG);
|
||||
+
|
||||
+ pr_info("Analog PMU set to %s control\n",
|
||||
+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
|
||||
+ pr_info("Digital PMU set to %s control\n",
|
||||
+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
|
||||
}
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
From 9dc3dba1bd621fe0e502d1d6efdfd64a0259a342 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 21 May 2013 15:50:31 +0200
|
||||
Subject: [PATCH 134/164] MIPS: ralink: adds a bootrom dumper module
|
||||
|
||||
This patch adds a trivial driver that allows userland to extract the bootrom of
|
||||
a SoC via debugfs.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Makefile | 2 ++
|
||||
arch/mips/ralink/bootrom.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 50 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/bootrom.c
|
||||
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -15,4 +15,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
|
||||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
+obj-$(CONFIG_DEBUG_FS) += bootrom.o
|
||||
+
|
||||
obj-y += dts/
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/bootrom.c
|
||||
@@ -0,0 +1,48 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/debugfs.h>
|
||||
+#include <linux/seq_file.h>
|
||||
+
|
||||
+#define BOOTROM_OFFSET 0x10118000
|
||||
+#define BOOTROM_SIZE 0x8000
|
||||
+
|
||||
+static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
|
||||
+
|
||||
+static int bootrom_show(struct seq_file *s, void *unused)
|
||||
+{
|
||||
+ seq_write(s, membase, BOOTROM_SIZE);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int bootrom_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ return single_open(file, bootrom_show, NULL);
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations bootrom_file_ops = {
|
||||
+ .open = bootrom_open,
|
||||
+ .read = seq_read,
|
||||
+ .llseek = seq_lseek,
|
||||
+ .release = single_release,
|
||||
+};
|
||||
+
|
||||
+static int bootrom_setup(void)
|
||||
+{
|
||||
+ if (!debugfs_create_file("bootrom", 0444,
|
||||
+ NULL, NULL, &bootrom_file_ops)) {
|
||||
+ pr_err("Failed to create bootrom debugfs file\n");
|
||||
+
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+postcore_initcall(bootrom_setup);
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
From 4a8fcf59741a8b71f97823c31d461fa6d9089cb0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 21 May 2013 17:15:54 +0200
|
||||
Subject: [PATCH 135/164] MIPS: ralink: add missing SZ_1M multiplier
|
||||
|
||||
On RT5350 the memory size is set to Bytes and not MegaBytes due to a missing
|
||||
multiplier.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/of.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -88,7 +88,7 @@ void __init plat_mem_setup(void)
|
||||
__dt_setup_arch(&__dtb_start);
|
||||
|
||||
if (soc_info.mem_size)
|
||||
- add_memory_region(soc_info.mem_base, soc_info.mem_size,
|
||||
+ add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
|
||||
BOOT_MEM_RAM);
|
||||
else
|
||||
detect_memory_region(soc_info.mem_base,
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
From 4977695198a8daf06746cb6c499d754040b6d0ac Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 3 May 2013 00:04:58 +0200
|
||||
Subject: [PATCH 136/164] MIPS: use set_mode() to enable/disable the cevt-r4k
|
||||
irq
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/kernel/cevt-r4k.c | 39 ++++++++++++++++++++++++++-------------
|
||||
1 file changed, 26 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/arch/mips/kernel/cevt-r4k.c
|
||||
+++ b/arch/mips/kernel/cevt-r4k.c
|
||||
@@ -39,12 +39,6 @@ static int mips_next_event(unsigned long
|
||||
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
||||
-void mips_set_clock_mode(enum clock_event_mode mode,
|
||||
- struct clock_event_device *evt)
|
||||
-{
|
||||
- /* Nothing to do ... */
|
||||
-}
|
||||
-
|
||||
DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
|
||||
int cp0_timer_irq_installed;
|
||||
|
||||
@@ -89,6 +83,32 @@ struct irqaction c0_compare_irqaction =
|
||||
.name = "timer",
|
||||
};
|
||||
|
||||
+void mips_set_clock_mode(enum clock_event_mode mode,
|
||||
+ struct clock_event_device *evt)
|
||||
+{
|
||||
+ switch (mode) {
|
||||
+ case CLOCK_EVT_MODE_ONESHOT:
|
||||
+ if (cp0_timer_irq_installed)
|
||||
+ break;
|
||||
+
|
||||
+ cp0_timer_irq_installed = 1;
|
||||
+
|
||||
+ setup_irq(evt->irq, &c0_compare_irqaction);
|
||||
+ break;
|
||||
+
|
||||
+ case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
+ if (!cp0_timer_irq_installed)
|
||||
+ break;
|
||||
+
|
||||
+ cp0_timer_irq_installed = 0;
|
||||
+ free_irq(evt->irq, &c0_compare_irqaction);
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ pr_err("Unhandeled mips clock_mode\n");
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
|
||||
void mips_event_handler(struct clock_event_device *dev)
|
||||
{
|
||||
@@ -208,13 +228,6 @@ int __cpuinit r4k_clockevent_init(void)
|
||||
|
||||
clockevents_register_device(cd);
|
||||
|
||||
- if (cp0_timer_irq_installed)
|
||||
- return 0;
|
||||
-
|
||||
- cp0_timer_irq_installed = 1;
|
||||
-
|
||||
- setup_irq(irq, &c0_compare_irqaction);
|
||||
-
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,117 +0,0 @@
|
|||
From 0402961539c5a98f3e9eac439e03f89498d110a1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 16 May 2013 23:28:23 +0200
|
||||
Subject: [PATCH 137/164] MIPS: ralink: add illegal access driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/ill_acc.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 88 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/ralink/ill_acc.c
|
||||
|
||||
Index: linux-3.9.10/arch/mips/ralink/Makefile
|
||||
===================================================================
|
||||
--- linux-3.9.10.orig/arch/mips/ralink/Makefile 2013-07-14 10:54:04.242545881 +0200
|
||||
+++ linux-3.9.10/arch/mips/ralink/Makefile 2013-07-14 11:42:58.726615805 +0200
|
||||
@@ -8,6 +8,8 @@
|
||||
|
||||
obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
|
||||
|
||||
+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
|
||||
+
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
obj-$(CONFIG_SOC_RT3883) += rt3883.o
|
||||
Index: linux-3.9.10/arch/mips/ralink/ill_acc.c
|
||||
===================================================================
|
||||
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||
+++ linux-3.9.10/arch/mips/ralink/ill_acc.c 2013-07-14 10:54:04.318545882 +0200
|
||||
@@ -0,0 +1,87 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define REG_ILL_ACC_ADDR 0x10
|
||||
+#define REG_ILL_ACC_TYPE 0x14
|
||||
+
|
||||
+#define ILL_INT_STATUS BIT(31)
|
||||
+#define ILL_ACC_WRITE BIT(30)
|
||||
+#define ILL_ACC_LEN_M 0xff
|
||||
+#define ILL_ACC_OFF_M 0xf
|
||||
+#define ILL_ACC_OFF_S 16
|
||||
+#define ILL_ACC_ID_M 0x7
|
||||
+#define ILL_ACC_ID_S 8
|
||||
+
|
||||
+#define DRV_NAME "ill_acc"
|
||||
+
|
||||
+static const char *ill_acc_ids[] = {
|
||||
+ "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
|
||||
+};
|
||||
+
|
||||
+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
|
||||
+{
|
||||
+ struct device *dev = (struct device *) _priv;
|
||||
+ u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
|
||||
+ u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
|
||||
+
|
||||
+ dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
|
||||
+ (type & ILL_ACC_WRITE) ? ("write") : ("read"),
|
||||
+ ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
|
||||
+ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
|
||||
+ type & ILL_ACC_LEN_M);
|
||||
+
|
||||
+ rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static int __init ill_acc_of_setup(void)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ struct device_node *np;
|
||||
+ int irq;
|
||||
+
|
||||
+ /* somehow this driver breaks on RT5350 */
|
||||
+ if (of_machine_is_compatible("ralink,rt5350-soc"))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
|
||||
+ if (!np)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ pdev = of_find_device_by_node(np);
|
||||
+ if (!pdev) {
|
||||
+ pr_err("%s: failed to lookup pdev\n", np->name);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ irq = irq_of_parse_and_map(np, 0);
|
||||
+ if (!irq) {
|
||||
+ dev_err(&pdev->dev, "failed to get irq\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
|
||||
+ dev_err(&pdev->dev, "failed to request irq\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "irq registered\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+arch_initcall(ill_acc_of_setup);
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
From bcffa7a81e00b8f67c459a2f5526edc0a5077794 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 23 May 2013 18:50:56 +0200
|
||||
Subject: [PATCH 138/164] MIPS: ralink: workaround DTB memory issue
|
||||
|
||||
If the DTB is too big a bug happens on boot when init ram is freed.
|
||||
This is a temporary fix until the real cause is found.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/of.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -74,7 +74,7 @@ void __init device_tree_init(void)
|
||||
unflatten_device_tree();
|
||||
|
||||
/* free the space reserved for the dt blob */
|
||||
- free_bootmem(base, size);
|
||||
+ //free_bootmem(base, size);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
From 17d26ed75f0981cdc497f9062aec5f66d3c44d88 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 23 May 2013 18:46:25 +0200
|
||||
Subject: [PATCH 139/164] MIPS: ralink: add spi clock definition to mt7620a
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/mt7620.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
|
||||
ralink_clk_add("cpu", cpu_rate);
|
||||
ralink_clk_add("10000100.timer", 40000000);
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
+ ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
}
|
||||
|
||||
|
|
@ -1,978 +0,0 @@
|
|||
From cee339922876e924295c27e274923d1b381f5057 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 30 Apr 2013 17:27:46 +0200
|
||||
Subject: [PATCH 140/164] MIPS: ralink DTS file updates
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 8 +
|
||||
arch/mips/ralink/dts/Makefile | 2 +
|
||||
arch/mips/ralink/dts/mt7620a.dtsi | 238 ++++++++++++++++++++++++-
|
||||
arch/mips/ralink/dts/mt7620a_eval.dts | 111 ++++++++++++
|
||||
arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts | 99 ++++++++++
|
||||
arch/mips/ralink/dts/rt2880.dtsi | 17 ++
|
||||
arch/mips/ralink/dts/rt2880_eval.dts | 6 +
|
||||
arch/mips/ralink/dts/rt3050.dtsi | 31 +++-
|
||||
arch/mips/ralink/dts/rt3052_eval.dts | 19 +-
|
||||
arch/mips/ralink/dts/rt5350.dtsi | 227 +++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt5350_eval.dts | 69 +++++++
|
||||
11 files changed, 824 insertions(+), 3 deletions(-)
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts
|
||||
create mode 100644 arch/mips/ralink/dts/rt5350.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt5350_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -42,6 +42,10 @@ choice
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
|
||||
+ config DTB_RT5350_EVAL
|
||||
+ bool "RT5350 eval kit"
|
||||
+ depends on SOC_RT305X
|
||||
+
|
||||
config DTB_RT3883_EVAL
|
||||
bool "RT3883 eval kit"
|
||||
depends on SOC_RT3883
|
||||
@@ -50,6 +54,10 @@ choice
|
||||
bool "MT7620A eval kit"
|
||||
depends on SOC_MT7620
|
||||
|
||||
+ config DTB_MT7620A_MT7610E_EVAL
|
||||
+ bool "MT7620A + MT7610E eval kit"
|
||||
+ depends on SOC_MT7620
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,4 +1,6 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_RT5350_EVAL) := rt5350_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_MT7620A_MT7610E_EVAL) := mt7620a_mt7610e_eval.dtb.o
|
||||
--- a/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
@@ -25,14 +25,36 @@
|
||||
#size-cells = <1>;
|
||||
|
||||
sysc@0 {
|
||||
- compatible = "ralink,mt7620a-sysc";
|
||||
+ compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 8>;
|
||||
+ reset-names = "wdt";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -43,16 +65,230 @@
|
||||
memc@300 {
|
||||
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
||||
reg = <0x300 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 20>;
|
||||
+ reset-names = "mc";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <3>;
|
||||
+ };
|
||||
+
|
||||
+ uart@500 {
|
||||
+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x500 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 12>;
|
||||
+ reset-names = "uart";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ resets = <&rstctrl 13>;
|
||||
+ reset-names = "pio";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <0>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <24>;
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <40>;
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ i2c@900 {
|
||||
+ compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
|
||||
+ reg = <0x900 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 16>;
|
||||
+ reset-names = "i2c";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 18>;
|
||||
+ reset-names = "spi";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "uartl";
|
||||
+
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <12>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
+
|
||||
+ systick@d00 {
|
||||
+ compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
|
||||
+ reg = <0xd00 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 28>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <7>;
|
||||
+ };
|
||||
+
|
||||
+ gdma@2800 {
|
||||
+ compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
|
||||
+ reg = <0x2800 0x800>;
|
||||
+
|
||||
+ resets = <&rstctrl 14>;
|
||||
+ reset-names = "dma";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <7>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rstctrl: rstctrl {
|
||||
+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ ubsphy {
|
||||
+ compatible = "ralink,mt7620a-usbphy";
|
||||
+
|
||||
+ resets = <&rstctrl 22 &rstctrl 25>;
|
||||
+ reset-names = "host", "device";
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,mt7620a-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio-bus {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gsw@10110000 {
|
||||
+ compatible = "ralink,mt7620a-gsw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sdhci@10130000 {
|
||||
+ compatible = "ralink,mt7620a-sdhci";
|
||||
+ reg = <0x10130000 4000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <14>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ehci@101c0000 {
|
||||
+ compatible = "ralink,rt3xxx-ehci";
|
||||
+ reg = <0x101c0000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+ };
|
||||
+
|
||||
+ ohci@101c1000 {
|
||||
+ compatible = "ralink,rt3xxx-ohci";
|
||||
+ reg = <0x101c1000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+ };
|
||||
+
|
||||
+ pcie@10140000 {
|
||||
+ compatible = "ralink,mt7620a-pci";
|
||||
+ reg = <0x10140000 0x100
|
||||
+ 0x10142000 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 26>;
|
||||
+ reset-names = "pcie0";
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <4>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
+++ b/arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
@@ -13,4 +13,115 @@
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,57600";
|
||||
};
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
|
||||
+ ralink,gpiomux = "i2c", "jtag";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <1>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ m25p80@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "en25q64";
|
||||
+ reg = <0 0>;
|
||||
+ linux,modalias = "m25p80", "en25q64";
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@30000 {
|
||||
+ label = "u-boot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ factory: partition@40000 {
|
||||
+ label = "factory";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@50000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x50000 0x7b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ port@4 {
|
||||
+ compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
|
||||
+ reg = <4>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-handle = <&phy4>;
|
||||
+ };
|
||||
+
|
||||
+ port@5 {
|
||||
+ compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
|
||||
+ reg = <5>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-handle = <&phy5>;
|
||||
+ };
|
||||
+
|
||||
+ mdio-bus {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ phy4: ethernet-phy@4 {
|
||||
+ reg = <4>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ };
|
||||
+
|
||||
+ phy5: ethernet-phy@5 {
|
||||
+ reg = <5>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gsw@10110000 {
|
||||
+ status = "okay";
|
||||
+ ralink,port4 = "gmac";
|
||||
+ };
|
||||
+
|
||||
+ sdhci@10130000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ pcie@10140000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys-polled {
|
||||
+ compatible = "gpio-keys";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ poll-interval = <20>;
|
||||
+ s2 {
|
||||
+ label = "S2";
|
||||
+ gpios = <&gpio0 1 1>;
|
||||
+ linux,code = <0x100>;
|
||||
+ };
|
||||
+ s3 {
|
||||
+ label = "S3";
|
||||
+ gpios = <&gpio0 2 1>;
|
||||
+ linux,code = <0x101>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts
|
||||
@@ -0,0 +1,99 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "mt7620a.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
|
||||
+ model = "Ralink MT7620A evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
|
||||
+ ralink,gpiomux = "i2c", "jtag";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <1>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ m25p80@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "en25q64";
|
||||
+ reg = <0 0>;
|
||||
+ linux,modalias = "m25p80", "en25q64";
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@30000 {
|
||||
+ label = "u-boot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ factory: partition@40000 {
|
||||
+ label = "factory";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@50000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x50000 0x7b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ gsw@10110000 {
|
||||
+ status = "okay";
|
||||
+ ralink,port4 = "ephy";
|
||||
+ };
|
||||
+
|
||||
+ sdhci@10130000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ pcie@10140000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys-polled {
|
||||
+ compatible = "gpio-keys";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ poll-interval = <20>;
|
||||
+ wps {
|
||||
+ label = "wps";
|
||||
+ gpios = <&gpio0 12 1>;
|
||||
+ linux,code = <0x100>;
|
||||
+ };
|
||||
+ reset {
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 13 1>;
|
||||
+ linux,code = <0x101>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/mips/ralink/dts/rt2880.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt2880.dtsi
|
||||
@@ -55,4 +55,21 @@
|
||||
reg-shift = <2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ ethernet@400000 {
|
||||
+ compatible = "ralink,rt2880-eth";
|
||||
+ reg = <0x00400000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio-bus {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/rt2880_eval.dts
|
||||
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
|
||||
@@ -43,4 +43,10 @@
|
||||
reg = <0x50000 0x3b0000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ ethernet@400000 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ ralink,fixed-link = <1000 1 1 1>;
|
||||
+ };
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/rt3050.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt3050.dtsi
|
||||
@@ -1,7 +1,7 @@
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
|
||||
+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
@@ -45,6 +45,15 @@
|
||||
reg = <0x300 0x100>;
|
||||
};
|
||||
|
||||
+ i2c@900 {
|
||||
+ compatible = "link,rt3052-i2c", "ralink,rt2880-i2c";
|
||||
+ reg = <0x900 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
@@ -55,4 +64,24 @@
|
||||
reg-shift = <2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt3050-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ compatible = "ralink,rt3050-esw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
--- a/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
@@ -3,7 +3,7 @@
|
||||
/include/ "rt3050.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
|
||||
+ compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc", "ralink,rt5350-soc";
|
||||
model = "Ralink RT3052 evaluation board";
|
||||
|
||||
memory@0 {
|
||||
@@ -14,6 +14,14 @@
|
||||
bootargs = "console=ttyS0,57600";
|
||||
};
|
||||
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "i2c", "spi", "uartlite", "jtag", "mdio", "sdram", "rgmii";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
cfi@1f000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x1f000000 0x800000>;
|
||||
@@ -43,4 +51,13 @@
|
||||
reg = <0x50000 0x7b0000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ status = "okay";
|
||||
+ ralink,portmap = <0x2f>;
|
||||
+ };
|
||||
};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt5350.dtsi
|
||||
@@ -0,0 +1,227 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt5350-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,rt5350-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+
|
||||
+ resets = <&rstctrl 8>;
|
||||
+ reset-names = "wdt";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "intc";
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 20>;
|
||||
+ reset-names = "mc";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <3>;
|
||||
+ };
|
||||
+
|
||||
+ uart@500 {
|
||||
+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x500 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 12>;
|
||||
+ reset-names = "uart";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ resets = <&rstctrl 13>;
|
||||
+ reset-names = "pio";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <0>;
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,gpio-base = <24>;
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ i2c@900 {
|
||||
+ compatible = "link,rt5350-i2c", "ralink,rt2880-i2c";
|
||||
+ reg = <0x900 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 16>;
|
||||
+ reset-names = "i2c";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 18>;
|
||||
+ reset-names = "spi";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ resets = <&rstctrl 19>;
|
||||
+ reset-names = "uartl";
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+
|
||||
+ systick@d00 {
|
||||
+ compatible = "ralink,rt5350-systick", "ralink,cevt-systick";
|
||||
+ reg = <0xd00 0x10>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <7>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rstctrl: rstctrl {
|
||||
+ compatible = "ralink,rt5350-reset", "ralink,rt2880-reset";
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ ubsphy {
|
||||
+ compatible = "ralink,rt3xxx-usbphy";
|
||||
+
|
||||
+ resets = <&rstctrl 22 &rstctrl 25>;
|
||||
+ reset-names = "host", "device";
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt5350-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ compatible = "ralink,rt3050-esw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ehci@101c0000 {
|
||||
+ compatible = "ralink,rt3xxx-ehci";
|
||||
+ reg = <0x101c0000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+ };
|
||||
+
|
||||
+ ohci@101c1000 {
|
||||
+ compatible = "ralink,rt3xxx-ohci";
|
||||
+ reg = <0x101c1000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt5350_eval.dts
|
||||
@@ -0,0 +1,69 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt5350.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,rt5350-eval-board", "ralink,rt5350-soc";
|
||||
+ model = "Ralink RT5350 evaluation board";
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "i2c", "spi", "uartlite", "jtag", "mdio", "sdram", "rgmii";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <1>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ m25p80@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "en25q64";
|
||||
+ reg = <0 0>;
|
||||
+ linux,modalias = "m25p80", "mx25l3205d";
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@30000 {
|
||||
+ label = "u-boot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ factory: partition@40000 {
|
||||
+ label = "factory";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@50000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x50000 0x3b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ status = "okay";
|
||||
+ ralink,portmap = <0x2f>;
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
From ec2ed8cdbe8b3d24261f0d88eb039e9d71e5d588 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 23 May 2013 16:58:12 +0200
|
||||
Subject: [PATCH 141/164] clocksource: make clocksource_of_init() pass a
|
||||
device_node pointer
|
||||
|
||||
If we look at the clocksources that are OF enabled we will notice, that they
|
||||
all do a of_find_matching_node() when being called. This patch changes
|
||||
clocksource_of_init() to always pass the struct device_node pointer to the
|
||||
init function.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/clocksource/bcm2835_timer.c | 12 +-----------
|
||||
drivers/clocksource/clksrc-of.c | 4 ++--
|
||||
drivers/clocksource/tegra20_timer.c | 14 +-------------
|
||||
drivers/clocksource/vt8500_timer.c | 14 +-------------
|
||||
4 files changed, 5 insertions(+), 39 deletions(-)
|
||||
|
||||
--- a/drivers/clocksource/bcm2835_timer.c
|
||||
+++ b/drivers/clocksource/bcm2835_timer.c
|
||||
@@ -95,23 +95,13 @@ static irqreturn_t bcm2835_time_interrup
|
||||
}
|
||||
}
|
||||
|
||||
-static struct of_device_id bcm2835_time_match[] __initconst = {
|
||||
- { .compatible = "brcm,bcm2835-system-timer" },
|
||||
- {}
|
||||
-};
|
||||
-
|
||||
-static void __init bcm2835_timer_init(void)
|
||||
+static void __init bcm2835_timer_init(struct device_node *node)
|
||||
{
|
||||
- struct device_node *node;
|
||||
void __iomem *base;
|
||||
u32 freq;
|
||||
int irq;
|
||||
struct bcm2835_timer *timer;
|
||||
|
||||
- node = of_find_matching_node(NULL, bcm2835_time_match);
|
||||
- if (!node)
|
||||
- panic("No bcm2835 timer node");
|
||||
-
|
||||
base = of_iomap(node, 0);
|
||||
if (!base)
|
||||
panic("Can't remap registers");
|
||||
--- a/drivers/clocksource/clksrc-of.c
|
||||
+++ b/drivers/clocksource/clksrc-of.c
|
||||
@@ -26,10 +26,10 @@ void __init clocksource_of_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct of_device_id *match;
|
||||
- void (*init_func)(void);
|
||||
+ void (*init_func)(struct device_node *);
|
||||
|
||||
for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
|
||||
init_func = match->data;
|
||||
- init_func();
|
||||
+ init_func(np);
|
||||
}
|
||||
}
|
||||
--- a/drivers/clocksource/tegra20_timer.c
|
||||
+++ b/drivers/clocksource/tegra20_timer.c
|
||||
@@ -154,29 +154,17 @@ static struct irqaction tegra_timer_irq
|
||||
.dev_id = &tegra_clockevent,
|
||||
};
|
||||
|
||||
-static const struct of_device_id timer_match[] __initconst = {
|
||||
- { .compatible = "nvidia,tegra20-timer" },
|
||||
- {}
|
||||
-};
|
||||
-
|
||||
static const struct of_device_id rtc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-rtc" },
|
||||
{}
|
||||
};
|
||||
|
||||
-static void __init tegra20_init_timer(void)
|
||||
+static void __init tegra20_init_timer(struct device_node *np)
|
||||
{
|
||||
- struct device_node *np;
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
- np = of_find_matching_node(NULL, timer_match);
|
||||
- if (!np) {
|
||||
- pr_err("Failed to find timer DT node\n");
|
||||
- BUG();
|
||||
- }
|
||||
-
|
||||
timer_reg_base = of_iomap(np, 0);
|
||||
if (!timer_reg_base) {
|
||||
pr_err("Can't map timer registers\n");
|
||||
--- a/drivers/clocksource/vt8500_timer.c
|
||||
+++ b/drivers/clocksource/vt8500_timer.c
|
||||
@@ -129,22 +129,10 @@ static struct irqaction irq = {
|
||||
.dev_id = &clockevent,
|
||||
};
|
||||
|
||||
-static struct of_device_id vt8500_timer_ids[] = {
|
||||
- { .compatible = "via,vt8500-timer" },
|
||||
- { }
|
||||
-};
|
||||
-
|
||||
-static void __init vt8500_timer_init(void)
|
||||
+static void __init vt8500_timer_init(struct device_node *np)
|
||||
{
|
||||
- struct device_node *np;
|
||||
int timer_irq;
|
||||
|
||||
- np = of_find_matching_node(NULL, vt8500_timer_ids);
|
||||
- if (!np) {
|
||||
- pr_err("%s: Timer description missing from Device Tree\n",
|
||||
- __func__);
|
||||
- return;
|
||||
- }
|
||||
regbase = of_iomap(np, 0);
|
||||
if (!regbase) {
|
||||
pr_err("%s: Missing iobase description in Device Tree\n",
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
From bc350a91da176ae8573c0755c66f5ee1911495bc Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 30 Apr 2013 12:35:50 +0200
|
||||
Subject: [PATCH 142/164] clocksource: MIPS: ralink: add support for systick
|
||||
timer found on newer ralink SoC
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 2 +
|
||||
arch/mips/ralink/clk.c | 1 +
|
||||
drivers/clocksource/Kconfig | 6 ++
|
||||
drivers/clocksource/Makefile | 1 +
|
||||
drivers/clocksource/cevt-rt3352.c | 162 +++++++++++++++++++++++++++++++++++++
|
||||
include/linux/clocksource.h | 1 +
|
||||
6 files changed, 173 insertions(+)
|
||||
create mode 100644 drivers/clocksource/cevt-rt3352.c
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -14,6 +14,7 @@ choice
|
||||
select USB_ARCH_HAS_HCD
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
+ select CLKEVT_RT3352
|
||||
|
||||
config SOC_RT3883
|
||||
bool "RT3883"
|
||||
@@ -22,6 +23,7 @@ choice
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
+ select CLKEVT_RT3352
|
||||
|
||||
endchoice
|
||||
|
||||
--- a/arch/mips/ralink/clk.c
|
||||
+++ b/arch/mips/ralink/clk.c
|
||||
@@ -69,4 +69,5 @@ void __init plat_time_init(void)
|
||||
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
clk_put(clk);
|
||||
+ clocksource_of_init();
|
||||
}
|
||||
--- a/drivers/clocksource/Kconfig
|
||||
+++ b/drivers/clocksource/Kconfig
|
||||
@@ -7,6 +7,12 @@ config CLKSRC_I8253
|
||||
config CLKEVT_I8253
|
||||
bool
|
||||
|
||||
+config CLKEVT_RT3352
|
||||
+ bool
|
||||
+ depends on MIPS && RALINK
|
||||
+ select CLKSRC_OF
|
||||
+ select CLKSRC_MMIO
|
||||
+
|
||||
config I8253_LOCK
|
||||
bool
|
||||
|
||||
--- a/drivers/clocksource/Makefile
|
||||
+++ b/drivers/clocksource/Makefile
|
||||
@@ -10,6 +10,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
|
||||
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
|
||||
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
|
||||
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
|
||||
+obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
|
||||
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
|
||||
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
|
||||
obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clocksource/cevt-rt3352.c
|
||||
@@ -0,0 +1,162 @@
|
||||
+/*
|
||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||
+ * License. See the file "COPYING" in the main directory of this archive
|
||||
+ * for more details.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 by John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clockchips.h>
|
||||
+#include <linux/clocksource.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_address.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+#include <asm/time.h>
|
||||
+
|
||||
+#define SYSTICK_FREQ (50 * 1000)
|
||||
+
|
||||
+#define SYSTICK_CONFIG 0x00
|
||||
+#define SYSTICK_COMPARE 0x04
|
||||
+#define SYSTICK_COUNT 0x08
|
||||
+
|
||||
+/* route systick irq to mips irq 7 instead of the r4k-timer */
|
||||
+#define CFG_EXT_STK_EN 0x2
|
||||
+/* enable the counter */
|
||||
+#define CFG_CNT_EN 0x1
|
||||
+
|
||||
+struct systick_device {
|
||||
+ void __iomem *membase;
|
||||
+ struct clock_event_device dev;
|
||||
+ int irq_requested;
|
||||
+ int freq_scale;
|
||||
+};
|
||||
+
|
||||
+static void systick_set_clock_mode(enum clock_event_mode mode,
|
||||
+ struct clock_event_device *evt);
|
||||
+
|
||||
+static int systick_next_event(unsigned long delta,
|
||||
+ struct clock_event_device *evt)
|
||||
+{
|
||||
+ struct systick_device *sdev = container_of(evt, struct systick_device, dev);
|
||||
+ u32 count;
|
||||
+
|
||||
+ count = ioread32(sdev->membase + SYSTICK_COUNT);
|
||||
+ count = (count + delta) % SYSTICK_FREQ;
|
||||
+ iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void systick_event_handler(struct clock_event_device *dev)
|
||||
+{
|
||||
+ /* noting to do here */
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t systick_interrupt(int irq, void *dev_id)
|
||||
+{
|
||||
+ struct clock_event_device *dev = (struct clock_event_device *) dev_id;
|
||||
+
|
||||
+ dev->event_handler(dev);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static struct systick_device systick = {
|
||||
+ .dev = {
|
||||
+ /* cevt-r4k uses 300, make sure systick gets used if available */
|
||||
+ .rating = 310,
|
||||
+ .features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
+ .set_next_event = systick_next_event,
|
||||
+ .set_mode = systick_set_clock_mode,
|
||||
+ .event_handler = systick_event_handler,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct irqaction systick_irqaction = {
|
||||
+ .handler = systick_interrupt,
|
||||
+ .flags = IRQF_PERCPU | IRQF_TIMER,
|
||||
+ .dev_id = &systick.dev,
|
||||
+};
|
||||
+
|
||||
+/* ugly hack */
|
||||
+#ifdef CONFIG_SOC_MT7620
|
||||
+
|
||||
+#define CLK_LUT_CFG 0x40
|
||||
+#define SLEEP_EN BIT(31)
|
||||
+
|
||||
+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
|
||||
+{
|
||||
+ if (sdev->freq_scale == status)
|
||||
+ return;
|
||||
+
|
||||
+ sdev->freq_scale = status;
|
||||
+
|
||||
+ pr_info("%s: %s autosleep mode\n", systick.dev.name, (status) ? ("enable") : ("disable"));
|
||||
+ if (status)
|
||||
+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
|
||||
+ else
|
||||
+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
|
||||
+}
|
||||
+#else
|
||||
+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) {}
|
||||
+#endif
|
||||
+
|
||||
+static void systick_set_clock_mode(enum clock_event_mode mode,
|
||||
+ struct clock_event_device *evt)
|
||||
+{
|
||||
+ struct systick_device *sdev = container_of(evt, struct systick_device, dev);
|
||||
+
|
||||
+ switch (mode) {
|
||||
+ case CLOCK_EVT_MODE_ONESHOT:
|
||||
+ if (!sdev->irq_requested)
|
||||
+ setup_irq(systick.dev.irq, &systick_irqaction);
|
||||
+ mt7620_freq_scaling(sdev, 1);
|
||||
+ sdev->irq_requested = 1;
|
||||
+ iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
|
||||
+ break;
|
||||
+
|
||||
+ case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
+ if (sdev->irq_requested)
|
||||
+ free_irq(systick.dev.irq, &systick_irqaction);
|
||||
+ mt7620_freq_scaling(sdev, 0);
|
||||
+ sdev->irq_requested = 0;
|
||||
+ iowrite32(0, systick.membase + SYSTICK_CONFIG);
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name);
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void __init ralink_systick_init(struct device_node *np)
|
||||
+{
|
||||
+ systick.membase = of_iomap(np, 0);
|
||||
+ if (!systick.membase) {
|
||||
+ pr_err("%s: of_iomap failed", np->name);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
|
||||
+ SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
|
||||
+
|
||||
+ systick_irqaction.name = np->name;
|
||||
+ systick.dev.name = np->name;
|
||||
+ clockevent_set_clock(&systick.dev, SYSTICK_FREQ);
|
||||
+ systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
|
||||
+ systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
|
||||
+ systick.dev.irq = irq_of_parse_and_map(np, 0);
|
||||
+ if (!systick.dev.irq)
|
||||
+ panic("%s: request_irq failed", np->name);
|
||||
+
|
||||
+ clockevents_register_device(&systick.dev);
|
||||
+
|
||||
+ pr_info("%s: runing - mult: %d, shift: %d\n", np->name, systick.dev.mult, systick.dev.shift);
|
||||
+}
|
||||
+
|
||||
+CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
|
||||
--- a/include/linux/clocksource.h
|
||||
+++ b/include/linux/clocksource.h
|
||||
@@ -340,6 +340,7 @@ extern void clocksource_of_init(void);
|
||||
__used __section(__clksrc_of_table) \
|
||||
= { .compatible = compat, .data = fn };
|
||||
#else
|
||||
+static inline void clocksource_of_init(void) {}
|
||||
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn)
|
||||
#endif
|
||||
|
||||
|
|
@ -1,410 +0,0 @@
|
|||
From 82a24aa01752a87c571e47323f0e141c818e531b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Jan 2013 18:24:34 +0100
|
||||
Subject: [PATCH 143/164] GPIO: MIPS: ralink: adds ralink gpio support
|
||||
|
||||
Add gpio driver for Ralink SoC. This driver makes the gpio core on
|
||||
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/Kconfig | 1 +
|
||||
arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
|
||||
drivers/gpio/Kconfig | 6 +
|
||||
drivers/gpio/Makefile | 1 +
|
||||
drivers/gpio/gpio-ralink.c | 326 ++++++++++++++++++++++++++++++
|
||||
5 files changed, 358 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
|
||||
create mode 100644 drivers/gpio/gpio-ralink.c
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -443,6 +443,7 @@ config RALINK
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select HAVE_MACH_CLKDEV
|
||||
select CLKDEV_LOOKUP
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
config SGI_IP22
|
||||
bool "SGI IP22 (Indy/Indigo2)"
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/gpio.h
|
||||
@@ -0,0 +1,24 @@
|
||||
+/*
|
||||
+ * Ralink SoC GPIO API support
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#ifndef __ASM_MACH_RALINK_GPIO_H
|
||||
+#define __ASM_MACH_RALINK_GPIO_H
|
||||
+
|
||||
+#define ARCH_NR_GPIOS 128
|
||||
+#include <asm-generic/gpio.h>
|
||||
+
|
||||
+#define gpio_get_value __gpio_get_value
|
||||
+#define gpio_set_value __gpio_set_value
|
||||
+#define gpio_cansleep __gpio_cansleep
|
||||
+#define gpio_to_irq __gpio_to_irq
|
||||
+
|
||||
+#endif /* __ASM_MACH_RALINK_GPIO_H */
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -204,6 +204,12 @@ config GPIO_PXA
|
||||
help
|
||||
Say yes here to support the PXA GPIO device
|
||||
|
||||
+config GPIO_RALINK
|
||||
+ bool "Ralink GPIO Support"
|
||||
+ depends on RALINK
|
||||
+ help
|
||||
+ Say yes here to support the Ralink SoC GPIO device
|
||||
+
|
||||
config GPIO_SPEAR_SPICS
|
||||
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
|
||||
depends on PLAT_SPEAR
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
|
||||
obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
|
||||
obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
|
||||
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
|
||||
+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
|
||||
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
|
||||
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
|
||||
obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpio/gpio-ralink.c
|
||||
@@ -0,0 +1,326 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/gpio.h>
|
||||
+#include <linux/spinlock.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+
|
||||
+enum ralink_gpio_reg {
|
||||
+ GPIO_REG_INT = 0,
|
||||
+ GPIO_REG_EDGE,
|
||||
+ GPIO_REG_RENA,
|
||||
+ GPIO_REG_FENA,
|
||||
+ GPIO_REG_DATA,
|
||||
+ GPIO_REG_DIR,
|
||||
+ GPIO_REG_POL,
|
||||
+ GPIO_REG_SET,
|
||||
+ GPIO_REG_RESET,
|
||||
+ GPIO_REG_TOGGLE,
|
||||
+ GPIO_REG_MAX
|
||||
+};
|
||||
+
|
||||
+struct ralink_gpio_chip {
|
||||
+ struct gpio_chip chip;
|
||||
+ u8 regs[GPIO_REG_MAX];
|
||||
+
|
||||
+ spinlock_t lock;
|
||||
+ void __iomem *membase;
|
||||
+ struct irq_domain *domain;
|
||||
+ int irq;
|
||||
+
|
||||
+ u32 rising;
|
||||
+ u32 falling;
|
||||
+};
|
||||
+
|
||||
+#define MAP_MAX 4
|
||||
+static struct irq_domain *irq_map[MAP_MAX];
|
||||
+static int irq_map_count;
|
||||
+static atomic_t irq_refcount = ATOMIC_INIT(0);
|
||||
+
|
||||
+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg;
|
||||
+
|
||||
+ rg = container_of(chip, struct ralink_gpio_chip, chip);
|
||||
+
|
||||
+ return rg;
|
||||
+}
|
||||
+
|
||||
+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
|
||||
+{
|
||||
+ iowrite32(val, rg->membase + rg->regs[reg]);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
|
||||
+{
|
||||
+ return ioread32(rg->membase + rg->regs[reg]);
|
||||
+}
|
||||
+
|
||||
+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
|
||||
+
|
||||
+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
|
||||
+
|
||||
+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
|
||||
+ unsigned long flags;
|
||||
+ u32 t;
|
||||
+
|
||||
+ spin_lock_irqsave(&rg->lock, flags);
|
||||
+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
|
||||
+ t &= ~BIT(offset);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
|
||||
+ spin_unlock_irqrestore(&rg->lock, flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_direction_output(struct gpio_chip *chip,
|
||||
+ unsigned offset, int value)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
|
||||
+ unsigned long flags;
|
||||
+ u32 t;
|
||||
+
|
||||
+ spin_lock_irqsave(&rg->lock, flags);
|
||||
+ ralink_gpio_set(chip, offset, value);
|
||||
+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
|
||||
+ t |= BIT(offset);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
|
||||
+ spin_unlock_irqrestore(&rg->lock, flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
|
||||
+
|
||||
+ if (rg->irq < 1)
|
||||
+ return -1;
|
||||
+
|
||||
+ ralink_gpio_direction_input(chip, pin);
|
||||
+
|
||||
+ return irq_create_mapping(rg->domain, pin);
|
||||
+}
|
||||
+
|
||||
+static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < irq_map_count; i++) {
|
||||
+ struct irq_domain *domain = irq_map[i];
|
||||
+ struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
|
||||
+ unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
|
||||
+ int bit;
|
||||
+
|
||||
+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
|
||||
+ u32 map = irq_find_mapping(domain, bit);
|
||||
+ generic_handle_irq(map);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void ralink_gpio_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
|
||||
+ u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ spin_lock_irqsave(&rg->lock, flags);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
|
||||
+ rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
|
||||
+ spin_unlock_irqrestore(&rg->lock, flags);
|
||||
+}
|
||||
+
|
||||
+static void ralink_gpio_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
|
||||
+ u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ spin_lock_irqsave(&rg->lock, flags);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
|
||||
+ rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
|
||||
+ spin_unlock_irqrestore(&rg->lock, flags);
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
+{
|
||||
+ struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
|
||||
+ u32 mask = BIT(d->hwirq);
|
||||
+
|
||||
+ if (type == IRQ_TYPE_PROBE) {
|
||||
+ if ((rg->rising | rg->falling) & mask)
|
||||
+ return 0;
|
||||
+
|
||||
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
|
||||
+ }
|
||||
+
|
||||
+ if (type & IRQ_TYPE_EDGE_RISING)
|
||||
+ rg->rising |= mask;
|
||||
+ else
|
||||
+ rg->rising &= mask;
|
||||
+
|
||||
+ if (type & IRQ_TYPE_EDGE_RISING)
|
||||
+ rg->falling |= mask;
|
||||
+ else
|
||||
+ rg->falling &= mask;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip ralink_gpio_irq_chip = {
|
||||
+ .name = "GPIO",
|
||||
+ .irq_unmask = ralink_gpio_irq_unmask,
|
||||
+ .irq_mask = ralink_gpio_irq_mask,
|
||||
+ .irq_mask_ack = ralink_gpio_irq_mask,
|
||||
+ .irq_set_type = ralink_gpio_irq_type,
|
||||
+};
|
||||
+
|
||||
+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
|
||||
+ irq_set_handler_data(irq, d);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops irq_domain_ops = {
|
||||
+ .xlate = irq_domain_xlate_onecell,
|
||||
+ .map = gpio_map,
|
||||
+};
|
||||
+
|
||||
+static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
|
||||
+{
|
||||
+ if (irq_map_count >= MAP_MAX)
|
||||
+ return;
|
||||
+
|
||||
+ rg->irq = irq_of_parse_and_map(np, 0);
|
||||
+ if (!rg->irq)
|
||||
+ return;
|
||||
+
|
||||
+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
|
||||
+ if (!rg->domain) {
|
||||
+ dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ irq_map[irq_map_count++] = rg->domain;
|
||||
+
|
||||
+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
|
||||
+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
|
||||
+
|
||||
+ if (!atomic_read(&irq_refcount))
|
||||
+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
|
||||
+ atomic_inc(&irq_refcount);
|
||||
+
|
||||
+ dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
|
||||
+}
|
||||
+
|
||||
+static int ralink_gpio_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ struct ralink_gpio_chip *rg;
|
||||
+ const __be32 *ngpio, *gpiobase;
|
||||
+
|
||||
+ if (!res) {
|
||||
+ dev_err(&pdev->dev, "failed to find resource\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ rg = devm_kzalloc(&pdev->dev,
|
||||
+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
|
||||
+ if (!rg)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ rg->membase = devm_request_and_ioremap(&pdev->dev, res);
|
||||
+ if (!rg->membase) {
|
||||
+ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ if (of_property_read_u8_array(np, "ralink,register-map",
|
||||
+ rg->regs, GPIO_REG_MAX)) {
|
||||
+ dev_err(&pdev->dev, "failed to read register definition\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
|
||||
+ if (!ngpio) {
|
||||
+ dev_err(&pdev->dev, "failed to read number of pins\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
|
||||
+ if (gpiobase)
|
||||
+ rg->chip.base = be32_to_cpu(*gpiobase);
|
||||
+ else
|
||||
+ rg->chip.base = -1;
|
||||
+
|
||||
+ spin_lock_init(&rg->lock);
|
||||
+
|
||||
+ rg->chip.dev = &pdev->dev;
|
||||
+ rg->chip.label = dev_name(&pdev->dev);
|
||||
+ rg->chip.of_node = np;
|
||||
+ rg->chip.ngpio = be32_to_cpu(*ngpio);
|
||||
+ rg->chip.direction_input = ralink_gpio_direction_input;
|
||||
+ rg->chip.direction_output = ralink_gpio_direction_output;
|
||||
+ rg->chip.get = ralink_gpio_get;
|
||||
+ rg->chip.set = ralink_gpio_set;
|
||||
+ rg->chip.to_irq = ralink_gpio_to_irq;
|
||||
+
|
||||
+ /* set polarity to low for all lines */
|
||||
+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
|
||||
+
|
||||
+ ralink_gpio_irq_init(np, rg);
|
||||
+
|
||||
+ return gpiochip_add(&rg->chip);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id ralink_gpio_match[] = {
|
||||
+ { .compatible = "ralink,rt2880-gpio" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
|
||||
+
|
||||
+static struct platform_driver ralink_gpio_driver = {
|
||||
+ .probe = ralink_gpio_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rt2880_gpio",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ralink_gpio_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init ralink_gpio_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ralink_gpio_driver);
|
||||
+}
|
||||
+
|
||||
+subsys_initcall(ralink_gpio_init);
|
||||
|
|
@ -1,518 +0,0 @@
|
|||
From 14620ea8ee17ba9642fbe42d73ff8ebfb42d6cf7 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 22 Apr 2013 23:16:18 +0200
|
||||
Subject: [PATCH 144/164] SPI: ralink: add Ralink SoC spi driver
|
||||
|
||||
Add the driver needed to make SPI work on Ralink SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/spi/Kconfig | 6 +
|
||||
drivers/spi/Makefile | 1 +
|
||||
drivers/spi/spi-ralink.c | 475 ++++++++++++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 482 insertions(+)
|
||||
create mode 100644 drivers/spi/spi-ralink.c
|
||||
|
||||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -336,6 +336,12 @@ config SPI_RSPI
|
||||
help
|
||||
SPI driver for Renesas RSPI blocks.
|
||||
|
||||
+config SPI_RALINK
|
||||
+ tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
|
||||
+ depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
|
||||
+ help
|
||||
+ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
|
||||
+
|
||||
config SPI_S3C24XX
|
||||
tristate "Samsung S3C24XX series SPI"
|
||||
depends on ARCH_S3C24XX
|
||||
--- a/drivers/spi/Makefile
|
||||
+++ b/drivers/spi/Makefile
|
||||
@@ -54,6 +54,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_
|
||||
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
|
||||
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
|
||||
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
|
||||
+obj-$(CONFIG_SPI_RALINK) += spi-ralink.o
|
||||
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
|
||||
spi-s3c24xx-hw-y := spi-s3c24xx.o
|
||||
spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/spi/spi-ralink.c
|
||||
@@ -0,0 +1,475 @@
|
||||
+/*
|
||||
+ * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
|
||||
+ *
|
||||
+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Some parts are based on spi-orion.c:
|
||||
+ * Author: Shadi Ammouri <shadi@marvell.com>
|
||||
+ * Copyright (C) 2007-2008 Marvell Ltd.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/spi/spi.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#define DRIVER_NAME "spi-ralink"
|
||||
+#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/
|
||||
+#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
|
||||
+
|
||||
+#define RAMIPS_SPI_STAT 0x00
|
||||
+#define RAMIPS_SPI_CFG 0x10
|
||||
+#define RAMIPS_SPI_CTL 0x14
|
||||
+#define RAMIPS_SPI_DATA 0x20
|
||||
+
|
||||
+/* SPISTAT register bit field */
|
||||
+#define SPISTAT_BUSY BIT(0)
|
||||
+
|
||||
+/* SPICFG register bit field */
|
||||
+#define SPICFG_LSBFIRST 0
|
||||
+#define SPICFG_MSBFIRST BIT(8)
|
||||
+#define SPICFG_SPICLKPOL BIT(6)
|
||||
+#define SPICFG_RXCLKEDGE_FALLING BIT(5)
|
||||
+#define SPICFG_TXCLKEDGE_FALLING BIT(4)
|
||||
+#define SPICFG_SPICLK_PRESCALE_MASK 0x7
|
||||
+#define SPICFG_SPICLK_DIV2 0
|
||||
+#define SPICFG_SPICLK_DIV4 1
|
||||
+#define SPICFG_SPICLK_DIV8 2
|
||||
+#define SPICFG_SPICLK_DIV16 3
|
||||
+#define SPICFG_SPICLK_DIV32 4
|
||||
+#define SPICFG_SPICLK_DIV64 5
|
||||
+#define SPICFG_SPICLK_DIV128 6
|
||||
+#define SPICFG_SPICLK_DISABLE 7
|
||||
+
|
||||
+/* SPICTL register bit field */
|
||||
+#define SPICTL_HIZSDO BIT(3)
|
||||
+#define SPICTL_STARTWR BIT(2)
|
||||
+#define SPICTL_STARTRD BIT(1)
|
||||
+#define SPICTL_SPIENA BIT(0)
|
||||
+
|
||||
+#ifdef DEBUG
|
||||
+#define spi_debug(args...) printk(args)
|
||||
+#else
|
||||
+#define spi_debug(args...)
|
||||
+#endif
|
||||
+
|
||||
+struct ralink_spi {
|
||||
+ struct spi_master *master;
|
||||
+ void __iomem *base;
|
||||
+ unsigned int sys_freq;
|
||||
+ unsigned int speed;
|
||||
+ struct clk *clk;
|
||||
+};
|
||||
+
|
||||
+static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
|
||||
+{
|
||||
+ return spi_master_get_devdata(spi->master);
|
||||
+}
|
||||
+
|
||||
+static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
|
||||
+{
|
||||
+ return ioread32(rs->base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
|
||||
+{
|
||||
+ iowrite32(val, rs->base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
|
||||
+{
|
||||
+ void __iomem *addr = rs->base + reg;
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = ioread32(addr);
|
||||
+ val |= mask;
|
||||
+ iowrite32(val, addr);
|
||||
+}
|
||||
+
|
||||
+static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
|
||||
+{
|
||||
+ void __iomem *addr = rs->base + reg;
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = ioread32(addr);
|
||||
+ val &= ~mask;
|
||||
+ iowrite32(val, addr);
|
||||
+}
|
||||
+
|
||||
+static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
|
||||
+{
|
||||
+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
|
||||
+ u32 rate;
|
||||
+ u32 prescale;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ spi_debug("%s: speed:%u\n", __func__, speed);
|
||||
+
|
||||
+ /*
|
||||
+ * the supported rates are: 2, 4, 8, ... 128
|
||||
+ * round up as we look for equal or less speed
|
||||
+ */
|
||||
+ rate = DIV_ROUND_UP(rs->sys_freq, speed);
|
||||
+ spi_debug("%s: rate-1:%u\n", __func__, rate);
|
||||
+ rate = roundup_pow_of_two(rate);
|
||||
+ spi_debug("%s: rate-2:%u\n", __func__, rate);
|
||||
+
|
||||
+ /* check if requested speed is too small */
|
||||
+ if (rate > 128)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (rate < 2)
|
||||
+ rate = 2;
|
||||
+
|
||||
+ /* Convert the rate to SPI clock divisor value. */
|
||||
+ prescale = ilog2(rate/2);
|
||||
+ spi_debug("%s: prescale:%u\n", __func__, prescale);
|
||||
+
|
||||
+ reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
|
||||
+ reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
|
||||
+ ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
|
||||
+ rs->speed = speed;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * called only when no transfer is active on the bus
|
||||
+ */
|
||||
+static int
|
||||
+ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
|
||||
+ unsigned int speed = spi->max_speed_hz;
|
||||
+ int rc;
|
||||
+ unsigned int bits_per_word = 8;
|
||||
+
|
||||
+ if ((t != NULL) && t->speed_hz)
|
||||
+ speed = t->speed_hz;
|
||||
+
|
||||
+ if ((t != NULL) && t->bits_per_word)
|
||||
+ bits_per_word = t->bits_per_word;
|
||||
+
|
||||
+ if (rs->speed != speed) {
|
||||
+ spi_debug("%s: speed_hz:%u\n", __func__, speed);
|
||||
+ rc = ralink_spi_baudrate_set(spi, speed);
|
||||
+ if (rc)
|
||||
+ return rc;
|
||||
+ }
|
||||
+
|
||||
+ if (bits_per_word != 8) {
|
||||
+ spi_debug("%s: bad bits_per_word: %u\n", __func__,
|
||||
+ bits_per_word);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
|
||||
+{
|
||||
+ if (enable)
|
||||
+ ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
|
||||
+ else
|
||||
+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
|
||||
+}
|
||||
+
|
||||
+static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
|
||||
+ if ((status & SPISTAT_BUSY) == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+
|
||||
+ return -ETIMEDOUT;
|
||||
+}
|
||||
+
|
||||
+static unsigned int
|
||||
+ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
|
||||
+{
|
||||
+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
|
||||
+ unsigned count = 0;
|
||||
+ u8 *rx = xfer->rx_buf;
|
||||
+ const u8 *tx = xfer->tx_buf;
|
||||
+ int err;
|
||||
+
|
||||
+ spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
|
||||
+ (tx != NULL) ? "tx" : " ",
|
||||
+ (rx != NULL) ? "rx" : " ");
|
||||
+
|
||||
+ if (tx) {
|
||||
+ for (count = 0; count < xfer->len; count++) {
|
||||
+ ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
|
||||
+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
|
||||
+ err = ralink_spi_wait_till_ready(rs);
|
||||
+ if (err) {
|
||||
+ dev_err(&spi->dev, "TX failed, err=%d\n", err);
|
||||
+ goto out;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (rx) {
|
||||
+ for (count = 0; count < xfer->len; count++) {
|
||||
+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
|
||||
+ err = ralink_spi_wait_till_ready(rs);
|
||||
+ if (err) {
|
||||
+ dev_err(&spi->dev, "RX failed, err=%d\n", err);
|
||||
+ goto out;
|
||||
+ }
|
||||
+ rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+out:
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+static int ralink_spi_transfer_one_message(struct spi_master *master,
|
||||
+ struct spi_message *m)
|
||||
+{
|
||||
+ struct ralink_spi *rs = spi_master_get_devdata(master);
|
||||
+ struct spi_device *spi = m->spi;
|
||||
+ struct spi_transfer *t = NULL;
|
||||
+ int par_override = 0;
|
||||
+ int status = 0;
|
||||
+ int cs_active = 0;
|
||||
+
|
||||
+ /* Load defaults */
|
||||
+ status = ralink_spi_setup_transfer(spi, NULL);
|
||||
+ if (status < 0)
|
||||
+ goto msg_done;
|
||||
+
|
||||
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
+ unsigned int bits_per_word = spi->bits_per_word;
|
||||
+
|
||||
+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
|
||||
+ dev_err(&spi->dev,
|
||||
+ "message rejected: invalid transfer data buffers\n");
|
||||
+ status = -EIO;
|
||||
+ goto msg_done;
|
||||
+ }
|
||||
+
|
||||
+ if (t->bits_per_word)
|
||||
+ bits_per_word = t->bits_per_word;
|
||||
+
|
||||
+ if (bits_per_word != 8) {
|
||||
+ dev_err(&spi->dev,
|
||||
+ "message rejected: invalid transfer bits_per_word (%d bits)\n",
|
||||
+ bits_per_word);
|
||||
+ status = -EIO;
|
||||
+ goto msg_done;
|
||||
+ }
|
||||
+
|
||||
+ if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
|
||||
+ dev_err(&spi->dev,
|
||||
+ "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
|
||||
+ (rs->sys_freq / 128), t->speed_hz);
|
||||
+ status = -EIO;
|
||||
+ goto msg_done;
|
||||
+ }
|
||||
+
|
||||
+ if (par_override || t->speed_hz || t->bits_per_word) {
|
||||
+ par_override = 1;
|
||||
+ status = ralink_spi_setup_transfer(spi, t);
|
||||
+ if (status < 0)
|
||||
+ goto msg_done;
|
||||
+ if (!t->speed_hz && !t->bits_per_word)
|
||||
+ par_override = 0;
|
||||
+ }
|
||||
+
|
||||
+ if (!cs_active) {
|
||||
+ ralink_spi_set_cs(rs, 1);
|
||||
+ cs_active = 1;
|
||||
+ }
|
||||
+
|
||||
+ if (t->len)
|
||||
+ m->actual_length += ralink_spi_write_read(spi, t);
|
||||
+
|
||||
+ if (t->delay_usecs)
|
||||
+ udelay(t->delay_usecs);
|
||||
+
|
||||
+ if (t->cs_change) {
|
||||
+ ralink_spi_set_cs(rs, 0);
|
||||
+ cs_active = 0;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+msg_done:
|
||||
+ if (cs_active)
|
||||
+ ralink_spi_set_cs(rs, 0);
|
||||
+
|
||||
+ m->status = status;
|
||||
+ spi_finalize_current_message(master);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_spi_setup(struct spi_device *spi)
|
||||
+{
|
||||
+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
|
||||
+
|
||||
+ if ((spi->max_speed_hz == 0) ||
|
||||
+ (spi->max_speed_hz > (rs->sys_freq / 2)))
|
||||
+ spi->max_speed_hz = (rs->sys_freq / 2);
|
||||
+
|
||||
+ if (spi->max_speed_hz < (rs->sys_freq / 128)) {
|
||||
+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
|
||||
+ spi->max_speed_hz);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
|
||||
+ dev_err(&spi->dev,
|
||||
+ "setup: requested bits per words - os wrong %d bpw\n",
|
||||
+ spi->bits_per_word);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (spi->bits_per_word == 0)
|
||||
+ spi->bits_per_word = 8;
|
||||
+
|
||||
+ /*
|
||||
+ * baudrate & width will be set ralink_spi_setup_transfer
|
||||
+ */
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void ralink_spi_reset(struct ralink_spi *rs)
|
||||
+{
|
||||
+ ralink_spi_write(rs, RAMIPS_SPI_CFG,
|
||||
+ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
|
||||
+ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
|
||||
+ ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
|
||||
+}
|
||||
+
|
||||
+static int ralink_spi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spi_master *master;
|
||||
+ struct ralink_spi *rs;
|
||||
+ struct resource *r;
|
||||
+ int status = 0;
|
||||
+
|
||||
+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
|
||||
+ if (master == NULL) {
|
||||
+ dev_dbg(&pdev->dev, "master allocation failed\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ //if (pdev->id != -1)
|
||||
+ master->bus_num = 0;
|
||||
+
|
||||
+ /* we support only mode 0, and no options */
|
||||
+ master->mode_bits = 0;
|
||||
+
|
||||
+ master->setup = ralink_spi_setup;
|
||||
+ master->transfer_one_message = ralink_spi_transfer_one_message;
|
||||
+ master->num_chipselect = RALINK_NUM_CHIPSELECTS;
|
||||
+ master->dev.of_node = pdev->dev.of_node;
|
||||
+
|
||||
+ dev_set_drvdata(&pdev->dev, master);
|
||||
+
|
||||
+ rs = spi_master_get_devdata(master);
|
||||
+ rs->master = master;
|
||||
+
|
||||
+ rs->clk = clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(rs->clk)) {
|
||||
+ status = PTR_ERR(rs->clk);
|
||||
+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
|
||||
+ status);
|
||||
+ goto out_put_master;
|
||||
+ }
|
||||
+
|
||||
+ status = clk_enable(rs->clk);
|
||||
+ if (status)
|
||||
+ goto out_put_clk;
|
||||
+
|
||||
+ rs->sys_freq = clk_get_rate(rs->clk);
|
||||
+ spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
|
||||
+
|
||||
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (r == NULL) {
|
||||
+ status = -ENODEV;
|
||||
+ goto out_disable_clk;
|
||||
+ }
|
||||
+
|
||||
+ rs->base = devm_request_and_ioremap(&pdev->dev, r);
|
||||
+ if (!rs->base) {
|
||||
+ status = -EADDRNOTAVAIL;
|
||||
+ goto out_disable_clk;
|
||||
+ }
|
||||
+
|
||||
+ device_reset(&pdev->dev);
|
||||
+
|
||||
+ ralink_spi_reset(rs);
|
||||
+
|
||||
+ status = spi_register_master(master);
|
||||
+ if (status)
|
||||
+ goto out_disable_clk;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+out_disable_clk:
|
||||
+ clk_disable(rs->clk);
|
||||
+out_put_clk:
|
||||
+ clk_put(rs->clk);
|
||||
+out_put_master:
|
||||
+ spi_master_put(master);
|
||||
+ return status;
|
||||
+}
|
||||
+
|
||||
+static int ralink_spi_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spi_master *master;
|
||||
+ struct ralink_spi *rs;
|
||||
+
|
||||
+ master = dev_get_drvdata(&pdev->dev);
|
||||
+ rs = spi_master_get_devdata(master);
|
||||
+
|
||||
+ clk_disable(rs->clk);
|
||||
+ clk_put(rs->clk);
|
||||
+ spi_unregister_master(master);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
+
|
||||
+static const struct of_device_id ralink_spi_match[] = {
|
||||
+ { .compatible = "ralink,rt2880-spi" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ralink_spi_match);
|
||||
+
|
||||
+static struct platform_driver ralink_spi_driver = {
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ralink_spi_match,
|
||||
+ },
|
||||
+ .probe = ralink_spi_probe,
|
||||
+ .remove = ralink_spi_remove,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ralink_spi_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Ralink SPI driver");
|
||||
+MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
|
||||
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From cf52f453acdd9599a1be0fcf0e941bad62046cd4 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Jan 2013 16:01:07 +0100
|
||||
Subject: [PATCH 145/164] serial: of: allow au1x00 and rt288x to load from OF
|
||||
|
||||
In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
|
||||
to default the iotype to UPIO_AU.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/tty/serial/of_serial.c | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/tty/serial/of_serial.c
|
||||
+++ b/drivers/tty/serial/of_serial.c
|
||||
@@ -98,7 +98,10 @@ static int of_platform_serial_setup(stru
|
||||
port->regshift = prop;
|
||||
|
||||
port->irq = irq_of_parse_and_map(np, 0);
|
||||
- port->iotype = UPIO_MEM;
|
||||
+ if (of_device_is_compatible(np, "ralink,rt2880-uart"))
|
||||
+ port->iotype = UPIO_AU;
|
||||
+ else
|
||||
+ port->iotype = UPIO_MEM;
|
||||
if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
|
||||
switch (prop) {
|
||||
case 1:
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
From 070a93b895d420757fd66215f0dba81f4b7b36c0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 15 Mar 2013 18:16:01 +0100
|
||||
Subject: [PATCH 146/164] serial: ralink: adds mt7620 serial
|
||||
|
||||
Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/tty/serial/8250/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/tty/serial/8250/Kconfig
|
||||
+++ b/drivers/tty/serial/8250/Kconfig
|
||||
@@ -296,7 +296,7 @@ config SERIAL_8250_EM
|
||||
|
||||
config SERIAL_8250_RT288X
|
||||
bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support"
|
||||
- depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883)
|
||||
+ depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
|
||||
help
|
||||
If you have a Ralink RT288x/RT305x SoC based board and want to use the
|
||||
serial port, say Y to this option. The driver can handle up to 2 serial
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,328 +0,0 @@
|
|||
From 27eef043b05fb8d9d3178fd3352c530f71901dd4 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 23 May 2013 18:45:29 +0200
|
||||
Subject: [PATCH 148/164] DMA: MIPS: ralink: add dmaengine driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/dma/Kconfig | 7 ++
|
||||
drivers/dma/Makefile | 1 +
|
||||
drivers/dma/ralink_gdma.c | 229 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
drivers/dma/ralink_gdma.h | 55 +++++++++++
|
||||
4 files changed, 292 insertions(+)
|
||||
create mode 100644 drivers/dma/ralink_gdma.c
|
||||
create mode 100644 drivers/dma/ralink_gdma.h
|
||||
|
||||
--- a/drivers/dma/Kconfig
|
||||
+++ b/drivers/dma/Kconfig
|
||||
@@ -322,6 +322,13 @@ config MMP_PDMA
|
||||
help
|
||||
Support the MMP PDMA engine for PXA and MMP platfrom.
|
||||
|
||||
+config RALINK_GDMA
|
||||
+ bool "Ralink Generic DMA support"
|
||||
+ depends on RALINK
|
||||
+ select DMA_ENGINE
|
||||
+ help
|
||||
+ Support the GDMA engine for MIPS based Ralink SoC.
|
||||
+
|
||||
config DMA_ENGINE
|
||||
bool
|
||||
|
||||
--- a/drivers/dma/Makefile
|
||||
+++ b/drivers/dma/Makefile
|
||||
@@ -37,3 +37,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
|
||||
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
|
||||
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
|
||||
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
|
||||
+obj-$(CONFIG_RALINK_GDMA) += ralink_gdma.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/dma/ralink_gdma.c
|
||||
@@ -0,0 +1,229 @@
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/spinlock.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/memory.h>
|
||||
+
|
||||
+#include "ralink_gdma.h"
|
||||
+
|
||||
+#define SURFBOARDINT_DMA 10
|
||||
+#define MEMCPY_DMA_CH 8
|
||||
+#define to_rt2880_dma_chan(chan) \
|
||||
+ container_of(chan, struct rt2880_dma_chan, common)
|
||||
+
|
||||
+static dma_cookie_t rt2880_dma_tx_submit(struct dma_async_tx_descriptor *tx)
|
||||
+{
|
||||
+ dma_cookie_t cookie;
|
||||
+
|
||||
+ cookie = tx->chan->cookie;
|
||||
+
|
||||
+ return cookie;
|
||||
+}
|
||||
+
|
||||
+#define MIN_RTDMA_PKT_LEN 128
|
||||
+static struct dma_async_tx_descriptor *
|
||||
+rt2880_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
||||
+ size_t len, unsigned long flags)
|
||||
+{
|
||||
+ struct rt2880_dma_chan *rt_chan = to_rt2880_dma_chan(chan);
|
||||
+ unsigned long mid_offset;
|
||||
+
|
||||
+ spin_lock_bh(&rt_chan->lock);
|
||||
+
|
||||
+ if(len < MIN_RTDMA_PKT_LEN) {
|
||||
+ memcpy(phys_to_virt(dest), phys_to_virt(src), len);
|
||||
+ } else {
|
||||
+ mid_offset = len/2;
|
||||
+
|
||||
+ /* Lower parts are transferred by GDMA.
|
||||
+ * Upper parts are transferred by CPU.
|
||||
+ */
|
||||
+ RT_DMA_WRITE_REG(RT_DMA_SRC_REG(MEMCPY_DMA_CH), src);
|
||||
+ RT_DMA_WRITE_REG(RT_DMA_DST_REG(MEMCPY_DMA_CH), dest);
|
||||
+ RT_DMA_WRITE_REG(RT_DMA_CTRL_REG(MEMCPY_DMA_CH), (mid_offset << 16) | (3 << 3) | (3 << 0));
|
||||
+
|
||||
+ memcpy(phys_to_virt(dest)+mid_offset, phys_to_virt(src)+mid_offset, len-mid_offset);
|
||||
+
|
||||
+ dma_async_tx_descriptor_init(&rt_chan->txd, chan);
|
||||
+
|
||||
+ while((RT_DMA_READ_REG(RT_DMA_DONEINT) & (0x1<<MEMCPY_DMA_CH))==0);
|
||||
+ RT_DMA_WRITE_REG(RT_DMA_DONEINT, (1<<MEMCPY_DMA_CH));
|
||||
+ }
|
||||
+
|
||||
+ spin_unlock_bh(&rt_chan->lock);
|
||||
+
|
||||
+ return &rt_chan->txd;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * rt2880_dma_status - poll the status of an XOR transaction
|
||||
+ * @chan: XOR channel handle
|
||||
+ * @cookie: XOR transaction identifier
|
||||
+ * @txstate: XOR transactions state holder (or NULL)
|
||||
+ */
|
||||
+static enum dma_status rt2880_dma_status(struct dma_chan *chan,
|
||||
+ dma_cookie_t cookie,
|
||||
+ struct dma_tx_state *txstate)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t rt2880_dma_interrupt_handler(int irq, void *data)
|
||||
+{
|
||||
+
|
||||
+ printk("%s\n",__FUNCTION__);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static void rt2880_dma_issue_pending(struct dma_chan *chan)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
+static int rt2880_dma_alloc_chan_resources(struct dma_chan *chan)
|
||||
+{
|
||||
+// printk("%s\n",__FUNCTION__);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rt2880_dma_free_chan_resources(struct dma_chan *chan)
|
||||
+{
|
||||
+// printk("%s\n",__FUNCTION__);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int rt2880_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
|
||||
+{
|
||||
+ switch (cmd) {
|
||||
+ case DMA_TERMINATE_ALL:
|
||||
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
|
||||
+ break;
|
||||
+ case DMA_SLAVE_CONFIG:
|
||||
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt2880_dma_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ __iomem void *membase;
|
||||
+ struct dma_device *dma_dev;
|
||||
+ struct rt2880_dma_chan *rt_chan;
|
||||
+ int err;
|
||||
+ int ret;
|
||||
+ int reg;
|
||||
+ int irq;
|
||||
+
|
||||
+ membase = devm_request_and_ioremap(&pdev->dev, res);
|
||||
+ if (IS_ERR(membase))
|
||||
+ return PTR_ERR(membase);
|
||||
+
|
||||
+ dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
|
||||
+ if (!dma_dev)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ irq = platform_get_irq(pdev, 0);
|
||||
+ if (!irq) {
|
||||
+ dev_err(&pdev->dev, "failed to load irq\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+
|
||||
+ INIT_LIST_HEAD(&dma_dev->channels);
|
||||
+ dma_cap_zero(dma_dev->cap_mask);
|
||||
+ dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
||||
+ dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
||||
+ dma_dev->device_alloc_chan_resources = rt2880_dma_alloc_chan_resources;
|
||||
+ dma_dev->device_free_chan_resources = rt2880_dma_free_chan_resources;
|
||||
+ dma_dev->device_tx_status = rt2880_dma_status;
|
||||
+ dma_dev->device_issue_pending = rt2880_dma_issue_pending;
|
||||
+ dma_dev->device_prep_dma_memcpy = rt2880_dma_prep_dma_memcpy;
|
||||
+ dma_dev->device_control = rt2880_dma_control;
|
||||
+ dma_dev->dev = &pdev->dev;
|
||||
+
|
||||
+ rt_chan = devm_kzalloc(&pdev->dev, sizeof(*rt_chan), GFP_KERNEL);
|
||||
+ if (!rt_chan) {
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ spin_lock_init(&rt_chan->lock);
|
||||
+ INIT_LIST_HEAD(&rt_chan->chain);
|
||||
+ INIT_LIST_HEAD(&rt_chan->completed_slots);
|
||||
+ INIT_LIST_HEAD(&rt_chan->all_slots);
|
||||
+ rt_chan->common.device = dma_dev;
|
||||
+ rt_chan->txd.tx_submit = rt2880_dma_tx_submit;
|
||||
+
|
||||
+ list_add_tail(&rt_chan->common.device_node, &dma_dev->channels);
|
||||
+
|
||||
+ err = dma_async_device_register(dma_dev);
|
||||
+ if (0 != err) {
|
||||
+ pr_err("ERR_MDMA:device_register failed: %d\n", err);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ ret = request_irq(irq, rt2880_dma_interrupt_handler, 0, dev_name(&pdev->dev), NULL);
|
||||
+ if(ret){
|
||||
+ pr_err("IRQ %d is not free.\n", SURFBOARDINT_DMA);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ //set GDMA register in advance.
|
||||
+ reg = (32 << 16) | (32 << 8) | (MEMCPY_DMA_CH << 3);
|
||||
+ RT_DMA_WRITE_REG(RT_DMA_CTRL_REG1(MEMCPY_DMA_CH), reg);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "running\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt2880_dma_remove(struct platform_device *dev)
|
||||
+{
|
||||
+ struct dma_device *dma_dev = platform_get_drvdata(dev);
|
||||
+
|
||||
+ printk("%s\n",__FUNCTION__);
|
||||
+
|
||||
+ dma_async_device_unregister(dma_dev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt2880_dma_match[] = {
|
||||
+ { .compatible = "ralink,rt2880-gdma" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt2880_wdt_match);
|
||||
+
|
||||
+static struct platform_driver rt2880_dma_driver = {
|
||||
+ .probe = rt2880_dma_probe,
|
||||
+ .remove = rt2880_dma_remove,
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = RT_DMA_NAME,
|
||||
+ .of_match_table = rt2880_dma_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init rt2880_dma_init(void)
|
||||
+{
|
||||
+ int rc;
|
||||
+
|
||||
+ rc = platform_driver_register(&rt2880_dma_driver);
|
||||
+ return rc;
|
||||
+}
|
||||
+module_init(rt2880_dma_init);
|
||||
+
|
||||
+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
|
||||
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
+MODULE_DESCRIPTION("DMA engine driver for Ralink DMA engine");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/drivers/dma/ralink_gdma.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2007, 2008, Marvell International Ltd.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms and conditions of the GNU General Public License,
|
||||
+ * version 2, as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope it will be useful, but WITHOUT
|
||||
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
+ * for more details.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program; if not, write to the Free Software Foundation,
|
||||
+ * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
+ */
|
||||
+
|
||||
+#ifndef RT_DMA_H
|
||||
+#define RT_DMA_H
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/dmaengine.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+
|
||||
+#define RT_DMA_NAME "rt2880_dma"
|
||||
+
|
||||
+#define RALINK_GDMA_BASE 0xB0002800
|
||||
+
|
||||
+struct rt2880_dma_chan {
|
||||
+ int pending;
|
||||
+ dma_cookie_t completed_cookie;
|
||||
+ spinlock_t lock; /* protects the descriptor slot pool */
|
||||
+ void __iomem *mmr_base;
|
||||
+ unsigned int idx;
|
||||
+ enum dma_transaction_type current_type;
|
||||
+ struct dma_async_tx_descriptor txd;
|
||||
+ struct list_head chain;
|
||||
+ struct list_head completed_slots;
|
||||
+ struct dma_chan common;
|
||||
+ struct list_head all_slots;
|
||||
+ int slots_allocated;
|
||||
+ struct tasklet_struct irq_tasklet;
|
||||
+};
|
||||
+
|
||||
+#define RT_DMA_READ_REG(addr) le32_to_cpu(*(volatile u32 *)(addr))
|
||||
+#define RT_DMA_WRITE_REG(addr, val) *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
|
||||
+
|
||||
+#define RT_DMA_SRC_REG(ch) (RALINK_GDMA_BASE + ch*16)
|
||||
+#define RT_DMA_DST_REG(ch) (RT_DMA_SRC_REG(ch) + 4)
|
||||
+#define RT_DMA_CTRL_REG(ch) (RT_DMA_DST_REG(ch) + 4)
|
||||
+#define RT_DMA_CTRL_REG1(ch) (RT_DMA_CTRL_REG(ch) + 4)
|
||||
+#define RT_DMA_DONEINT (RALINK_GDMA_BASE + 0x204)
|
||||
+
|
||||
+#endif
|
||||
|
|
@ -1,319 +0,0 @@
|
|||
From 7cc89e7fc028a8e23b5dc226be5cf94b33764885 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 18:27:29 +0100
|
||||
Subject: [PATCH 149/164] PCI: MIPS: adds rt2880 pci support
|
||||
|
||||
Add support for the pci found on the rt2880 SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/pci/Makefile | 1 +
|
||||
arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
3 files changed, 283 insertions(+)
|
||||
create mode 100644 arch/mips/pci/pci-rt2880.c
|
||||
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
|
||||
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
|
||||
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
|
||||
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
|
||||
+obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
|
||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/pci/pci-rt2880.c
|
||||
@@ -0,0 +1,281 @@
|
||||
+/*
|
||||
+ * Ralink RT288x SoC PCI register definitions
|
||||
+ *
|
||||
+ * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
|
||||
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/rt288x.h>
|
||||
+
|
||||
+#define RT2880_PCI_BASE 0x00440000
|
||||
+#define RT288X_CPU_IRQ_PCI 4
|
||||
+
|
||||
+#define RT2880_PCI_MEM_BASE 0x20000000
|
||||
+#define RT2880_PCI_MEM_SIZE 0x10000000
|
||||
+#define RT2880_PCI_IO_BASE 0x00460000
|
||||
+#define RT2880_PCI_IO_SIZE 0x00010000
|
||||
+
|
||||
+#define RT2880_PCI_REG_PCICFG_ADDR 0x00
|
||||
+#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
|
||||
+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
|
||||
+#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
|
||||
+#define RT2880_PCI_REG_CONFIG_ADDR 0x20
|
||||
+#define RT2880_PCI_REG_CONFIG_DATA 0x24
|
||||
+#define RT2880_PCI_REG_MEMBASE 0x28
|
||||
+#define RT2880_PCI_REG_IOBASE 0x2c
|
||||
+#define RT2880_PCI_REG_ID 0x30
|
||||
+#define RT2880_PCI_REG_CLASS 0x34
|
||||
+#define RT2880_PCI_REG_SUBID 0x38
|
||||
+#define RT2880_PCI_REG_ARBCTL 0x80
|
||||
+
|
||||
+static void __iomem *rt2880_pci_base;
|
||||
+static DEFINE_SPINLOCK(rt2880_pci_lock);
|
||||
+
|
||||
+static u32 rt2880_pci_reg_read(u32 reg)
|
||||
+{
|
||||
+ return readl(rt2880_pci_base + reg);
|
||||
+}
|
||||
+
|
||||
+static void rt2880_pci_reg_write(u32 val, u32 reg)
|
||||
+{
|
||||
+ writel(val, rt2880_pci_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
+ unsigned int func, unsigned int where)
|
||||
+{
|
||||
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
|
||||
+ 0x80000000);
|
||||
+}
|
||||
+
|
||||
+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
|
||||
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
|
||||
+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ *val = data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
|
||||
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
|
||||
+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ data = val;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops rt2880_pci_ops = {
|
||||
+ .read = rt2880_pci_config_read,
|
||||
+ .write = rt2880_pci_config_write,
|
||||
+};
|
||||
+
|
||||
+static struct resource rt2880_pci_mem_resource = {
|
||||
+ .name = "PCI MEM space",
|
||||
+ .start = RT2880_PCI_MEM_BASE,
|
||||
+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct resource rt2880_pci_io_resource = {
|
||||
+ .name = "PCI IO space",
|
||||
+ .start = RT2880_PCI_IO_BASE,
|
||||
+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
|
||||
+ .flags = IORESOURCE_IO,
|
||||
+};
|
||||
+
|
||||
+static struct pci_controller rt2880_pci_controller = {
|
||||
+ .pci_ops = &rt2880_pci_ops,
|
||||
+ .mem_resource = &rt2880_pci_mem_resource,
|
||||
+ .io_resource = &rt2880_pci_io_resource,
|
||||
+};
|
||||
+
|
||||
+static inline u32 rt2880_pci_read_u32(unsigned long reg)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 ret;
|
||||
+
|
||||
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
|
||||
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
|
||||
+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+
|
||||
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
|
||||
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
|
||||
+ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
|
||||
+}
|
||||
+
|
||||
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ u16 cmd;
|
||||
+ int irq = -1;
|
||||
+
|
||||
+ if (dev->bus->number != 0)
|
||||
+ return irq;
|
||||
+
|
||||
+ switch (PCI_SLOT(dev->devfn)) {
|
||||
+ case 0x00:
|
||||
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
|
||||
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
|
||||
+ break;
|
||||
+ case 0x11:
|
||||
+ irq = RT288X_CPU_IRQ_PCI;
|
||||
+ break;
|
||||
+ default:
|
||||
+ printk("%s:%s[%d] trying to alloc unknown pci irq\n",
|
||||
+ __FILE__, __func__, __LINE__);
|
||||
+ BUG();
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
|
||||
+ pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
|
||||
+ pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
|
||||
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||||
+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
|
||||
+ PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
|
||||
+ pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
|
||||
+ pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
|
||||
+ dev->irq);
|
||||
+ return irq;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_pci_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ void __iomem *io_map_base;
|
||||
+ int i;
|
||||
+
|
||||
+ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
|
||||
+
|
||||
+ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
|
||||
+ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
|
||||
+ set_io_port_base((unsigned long) io_map_base);
|
||||
+
|
||||
+ ioport_resource.start = RT2880_PCI_IO_BASE;
|
||||
+ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
|
||||
+
|
||||
+ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
|
||||
+ for(i = 0; i < 0xfffff; i++) {}
|
||||
+
|
||||
+ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
|
||||
+ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
|
||||
+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
|
||||
+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
|
||||
+ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
|
||||
+ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
|
||||
+ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
|
||||
+ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
|
||||
+ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
|
||||
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
|
||||
+
|
||||
+ register_pci_controller(&rt2880_pci_controller);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt288x_pci_match[] = {
|
||||
+ { .compatible = "ralink,rt288x-pci" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt288x_pci_match);
|
||||
+
|
||||
+static struct platform_driver rt288x_pci_driver = {
|
||||
+ .probe = rt288x_pci_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rt288x-pci",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = rt288x_pci_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init pcibios_init(void)
|
||||
+{
|
||||
+ int ret = platform_driver_register(&rt288x_pci_driver);
|
||||
+ if (ret)
|
||||
+ pr_info("rt288x-pci: Error registering platform driver!");
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+arch_initcall(pcibios_init);
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -8,6 +8,7 @@ choice
|
||||
|
||||
config SOC_RT288X
|
||||
bool "RT288x"
|
||||
+ select HW_HAS_PCI
|
||||
|
||||
config SOC_RT305X
|
||||
bool "RT305x"
|
||||
|
|
@ -1,678 +0,0 @@
|
|||
From 9e3707ddded9895aa47e11b42125a94f04f8bd9d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:34:08 +0100
|
||||
Subject: [PATCH 150/164] PCI: MIPS: adds rt3883 pci support
|
||||
|
||||
Add support for the pcie found on the rt3883 SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/pci/Makefile | 1 +
|
||||
arch/mips/pci/pci-rt3883.c | 640 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
3 files changed, 642 insertions(+)
|
||||
create mode 100644 arch/mips/pci/pci-rt3883.c
|
||||
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
|
||||
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
|
||||
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
|
||||
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
|
||||
+obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
|
||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/pci/pci-rt3883.c
|
||||
@@ -0,0 +1,640 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 SoC PCI support
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/rt3883.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define RT3883_MEMORY_BASE 0x00000000
|
||||
+#define RT3883_MEMORY_SIZE 0x02000000
|
||||
+
|
||||
+#define RT3883_PCI_REG_PCICFG 0x00
|
||||
+#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
|
||||
+#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
|
||||
+#define RT3883_PCICFG_PCIRST BIT(1)
|
||||
+#define RT3883_PCI_REG_PCIRAW 0x04
|
||||
+#define RT3883_PCI_REG_PCIINT 0x08
|
||||
+#define RT3883_PCI_REG_PCIENA 0x0c
|
||||
+
|
||||
+#define RT3883_PCI_REG_CFGADDR 0x20
|
||||
+#define RT3883_PCI_REG_CFGDATA 0x24
|
||||
+#define RT3883_PCI_REG_MEMBASE 0x28
|
||||
+#define RT3883_PCI_REG_IOBASE 0x2c
|
||||
+#define RT3883_PCI_REG_ARBCTL 0x80
|
||||
+
|
||||
+#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
|
||||
+#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
|
||||
+#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
|
||||
+#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
|
||||
+#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
|
||||
+#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
|
||||
+#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
|
||||
+
|
||||
+#define RT3883_PCI_MODE_NONE 0
|
||||
+#define RT3883_PCI_MODE_PCI BIT(0)
|
||||
+#define RT3883_PCI_MODE_PCIE BIT(1)
|
||||
+#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
|
||||
+
|
||||
+#define RT3883_PCI_IRQ_COUNT 32
|
||||
+
|
||||
+#define RT3883_P2P_BR_DEVNUM 1
|
||||
+
|
||||
+struct rt3883_pci_controller {
|
||||
+ void __iomem *base;
|
||||
+ spinlock_t lock;
|
||||
+
|
||||
+ struct irq_domain *irq_domain;
|
||||
+
|
||||
+ struct pci_controller pci_controller;
|
||||
+ struct resource io_res;
|
||||
+ struct resource mem_res;
|
||||
+
|
||||
+ bool pcie_ready;
|
||||
+ unsigned char p2p_devnum;
|
||||
+};
|
||||
+
|
||||
+static inline struct rt3883_pci_controller *
|
||||
+pci_bus_to_rt3883_controller(struct pci_bus *bus)
|
||||
+{
|
||||
+ struct pci_controller *hose;
|
||||
+
|
||||
+ hose = (struct pci_controller *) bus->sysdata;
|
||||
+ return container_of(hose, struct rt3883_pci_controller, pci_controller);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
|
||||
+ unsigned reg)
|
||||
+{
|
||||
+ return ioread32(rpc->base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
|
||||
+ u32 val, unsigned reg)
|
||||
+{
|
||||
+ iowrite32(val, rpc->base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
+ unsigned int func, unsigned int where)
|
||||
+{
|
||||
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
|
||||
+ 0x80000000);
|
||||
+}
|
||||
+
|
||||
+static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
|
||||
+ unsigned bus, unsigned slot,
|
||||
+ unsigned func, unsigned reg)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 ret;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
|
||||
+ unsigned bus, unsigned slot,
|
||||
+ unsigned func, unsigned reg, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ u32 pending;
|
||||
+
|
||||
+ rpc = irq_get_handler_data(irq);
|
||||
+
|
||||
+ pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+
|
||||
+ if (!pending) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ while (pending) {
|
||||
+ unsigned bit = __ffs(pending);
|
||||
+
|
||||
+ irq = irq_find_mapping(rpc->irq_domain, bit);
|
||||
+ generic_handle_irq(irq);
|
||||
+
|
||||
+ pending &= ~BIT(bit);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ u32 t;
|
||||
+
|
||||
+ rpc = irq_data_get_irq_chip_data(d);
|
||||
+
|
||||
+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+ rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ u32 t;
|
||||
+
|
||||
+ rpc = irq_data_get_irq_chip_data(d);
|
||||
+
|
||||
+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+ rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip rt3883_pci_irq_chip = {
|
||||
+ .name = "RT3883 PCI",
|
||||
+ .irq_mask = rt3883_pci_irq_mask,
|
||||
+ .irq_unmask = rt3883_pci_irq_unmask,
|
||||
+ .irq_mask_ack = rt3883_pci_irq_mask,
|
||||
+};
|
||||
+
|
||||
+static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
|
||||
+ irq_hw_number_t hw)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, d->host_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
|
||||
+ .map = rt3883_pci_irq_map,
|
||||
+ .xlate = irq_domain_xlate_onecell,
|
||||
+};
|
||||
+
|
||||
+static int rt3883_pci_irq_init(struct device *dev,
|
||||
+ struct rt3883_pci_controller *rpc)
|
||||
+{
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct device_node *intc_np;
|
||||
+ int irq;
|
||||
+ int err;
|
||||
+
|
||||
+ intc_np = of_get_child_by_name(np, "interrupt-controller");
|
||||
+ if (!intc_np) {
|
||||
+ dev_err(dev, "no %s child node found", "interrupt-controller");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ irq = irq_of_parse_and_map(intc_np, 0);
|
||||
+ if (irq == 0) {
|
||||
+ dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
|
||||
+ err = -EINVAL;
|
||||
+ goto err_put_intc;
|
||||
+ }
|
||||
+
|
||||
+ /* disable all interrupts */
|
||||
+ rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
|
||||
+
|
||||
+ rpc->irq_domain =
|
||||
+ irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
|
||||
+ &rt3883_pci_irq_domain_ops,
|
||||
+ rpc);
|
||||
+ if (!rpc->irq_domain) {
|
||||
+ dev_err(dev, "unable to add IRQ domain\n");
|
||||
+ err = -ENODEV;
|
||||
+ goto err_put_intc;
|
||||
+ }
|
||||
+
|
||||
+ irq_set_handler_data(irq, rpc);
|
||||
+ irq_set_chained_handler(irq, rt3883_pci_irq_handler);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_put_intc:
|
||||
+ of_node_put(intc_np);
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(bus);
|
||||
+
|
||||
+ if (!rpc->pcie_ready && bus->number == 1)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ *val = data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(bus);
|
||||
+
|
||||
+ if (!rpc->pcie_ready && bus->number == 1)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ data = val;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops rt3883_pci_ops = {
|
||||
+ .read = rt3883_pci_config_read,
|
||||
+ .write = rt3883_pci_config_write,
|
||||
+};
|
||||
+
|
||||
+static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
|
||||
+{
|
||||
+ u32 syscfg1;
|
||||
+ u32 rstctrl;
|
||||
+ u32 clkcfg1;
|
||||
+ u32 t;
|
||||
+
|
||||
+ rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
+ syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
|
||||
+ clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ rstctrl |= RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
+
|
||||
+ /* setup PCI PAD drive mode */
|
||||
+ syscfg1 &= ~(0x30);
|
||||
+ syscfg1 |= (2 << 4);
|
||||
+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ t &= ~BIT(31);
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+ t &= 0x80ffffff;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+ t |= 0xa << 24;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ t |= BIT(31);
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+
|
||||
+ msleep(50);
|
||||
+
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
+ }
|
||||
+
|
||||
+ syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
|
||||
+
|
||||
+ clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCI) {
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCI;
|
||||
+ }
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ }
|
||||
+
|
||||
+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
+ rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ /*
|
||||
+ * setup the device number of the P2P bridge
|
||||
+ * and de-assert the reset line
|
||||
+ */
|
||||
+ t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
|
||||
+ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
|
||||
+
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
|
||||
+ msleep(500);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ msleep(500);
|
||||
+
|
||||
+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
|
||||
+
|
||||
+ rpc->pcie_ready = t & BIT(0);
|
||||
+
|
||||
+ if (!rpc->pcie_ready) {
|
||||
+ /* reset the PCIe block */
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
+ t |= RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
|
||||
+ t &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
|
||||
+
|
||||
+ /* turn off PCIe clock */
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
|
||||
+ t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ t &= ~0xf000c080;
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* enable PCI arbiter */
|
||||
+ rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
|
||||
+}
|
||||
+
|
||||
+static inline void
|
||||
+rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
|
||||
+ int bus, int slot)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < 16; i++) {
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
|
||||
+ pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
|
||||
+ bus, slot, i << 2, val);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res;
|
||||
+ struct device_node *child;
|
||||
+ u32 val;
|
||||
+ int err;
|
||||
+ int mode;
|
||||
+
|
||||
+ rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
|
||||
+ if (!rpc)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ rpc->base = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(rpc->base))
|
||||
+ return PTR_ERR(rpc->base);
|
||||
+
|
||||
+ rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
|
||||
+ if (!rpc->pci_controller.of_node) {
|
||||
+ dev_err(dev, "no %s child node found", "host-bridge");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ mode = RT3883_PCI_MODE_NONE;
|
||||
+ for_each_child_of_node(rpc->pci_controller.of_node, child) {
|
||||
+ u32 slot;
|
||||
+
|
||||
+ if (!of_device_is_available(child))
|
||||
+ continue;
|
||||
+
|
||||
+ if (of_property_read_u32(child, "ralink,pci-slot",
|
||||
+ &slot)) {
|
||||
+ dev_err(dev, "no '%s' property found for %s\n",
|
||||
+ "ralink,pci-slot",
|
||||
+ of_node_full_name(child));
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ switch (slot) {
|
||||
+ case 1:
|
||||
+ mode |= RT3883_PCI_MODE_PCIE;
|
||||
+ break;
|
||||
+
|
||||
+ case 17:
|
||||
+ case 18:
|
||||
+ mode |= RT3883_PCI_MODE_PCI;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (mode == RT3883_PCI_MODE_NONE) {
|
||||
+ dev_err(dev, "unable to determine PCI mode\n");
|
||||
+ err = -EINVAL;
|
||||
+ goto err_put_hb_node;
|
||||
+ }
|
||||
+
|
||||
+ dev_info(dev, "mode:%s%s\n",
|
||||
+ (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
|
||||
+ (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
|
||||
+
|
||||
+ rt3883_pci_preinit(rpc, mode);
|
||||
+
|
||||
+ rpc->pci_controller.pci_ops = &rt3883_pci_ops;
|
||||
+ rpc->pci_controller.io_resource = &rpc->io_res;
|
||||
+ rpc->pci_controller.mem_resource = &rpc->mem_res;
|
||||
+
|
||||
+ /* Load PCI I/O and memory resources from DT */
|
||||
+ pci_load_of_ranges(&rpc->pci_controller,
|
||||
+ rpc->pci_controller.of_node);
|
||||
+
|
||||
+ rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
|
||||
+ rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
|
||||
+
|
||||
+ ioport_resource.start = rpc->io_res.start;
|
||||
+ ioport_resource.end = rpc->io_res.end;
|
||||
+
|
||||
+ /* PCI */
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
|
||||
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
|
||||
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
|
||||
+ rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
|
||||
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
|
||||
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
|
||||
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
|
||||
+ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
|
||||
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
|
||||
+
|
||||
+ err = rt3883_pci_irq_init(dev, rpc);
|
||||
+ if (err)
|
||||
+ goto err_put_hb_node;
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
|
||||
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ /* PCI */
|
||||
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
|
||||
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ if (mode == RT3883_PCI_MODE_PCIE) {
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
|
||||
+
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
+ PCI_BASE_ADDRESS_0,
|
||||
+ RT3883_MEMORY_BASE);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
+ PCI_BASE_ADDRESS_0);
|
||||
+ } else {
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
+ PCI_IO_BASE, 0x00000101);
|
||||
+ }
|
||||
+
|
||||
+ register_pci_controller(&rpc->pci_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_put_hb_node:
|
||||
+ of_node_put(rpc->pci_controller.of_node);
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ struct of_irq dev_irq;
|
||||
+ int err;
|
||||
+ int irq;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(dev->bus);
|
||||
+ err = of_irq_map_pci(dev, &dev_irq);
|
||||
+ if (err) {
|
||||
+ pr_err("pci %s: unable to get irq map, err=%d\n",
|
||||
+ pci_name((struct pci_dev *) dev), err);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ irq = irq_create_of_mapping(dev_irq.controller,
|
||||
+ dev_irq.specifier,
|
||||
+ dev_irq.size);
|
||||
+
|
||||
+ if (irq == 0)
|
||||
+ pr_crit("pci %s: no irq found for pin %u\n",
|
||||
+ pci_name((struct pci_dev *) dev), pin);
|
||||
+ else
|
||||
+ pr_info("pci %s: using irq %d for pin %u\n",
|
||||
+ pci_name((struct pci_dev *) dev), irq, pin);
|
||||
+
|
||||
+ return irq;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt3883_pci_ids[] = {
|
||||
+ { .compatible = "ralink,rt3883-pci" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
|
||||
+
|
||||
+static struct platform_driver rt3883_pci_driver = {
|
||||
+ .probe = rt3883_pci_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rt3883-pci",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = of_match_ptr(rt3883_pci_ids),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init rt3883_pci_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&rt3883_pci_driver);
|
||||
+}
|
||||
+
|
||||
+postcore_initcall(rt3883_pci_init);
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -21,6 +21,7 @@ choice
|
||||
bool "RT3883"
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
+ select HW_HAS_PCI
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
|
|
@ -1,399 +0,0 @@
|
|||
From 06276ceb7de13d19c74cff597c5c62fe1f9fb556 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 18 May 2013 22:06:15 +0200
|
||||
Subject: [PATCH 151/164] PCI: MIPS: adds mt7620a pcie driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/pci/Makefile | 1 +
|
||||
arch/mips/pci/pci-mt7620a.c | 363 +++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
3 files changed, 365 insertions(+)
|
||||
create mode 100644 arch/mips/pci/pci-mt7620a.c
|
||||
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -43,6 +43,7 @@ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
|
||||
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
|
||||
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
|
||||
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
|
||||
+obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
|
||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/pci/pci-mt7620a.c
|
||||
@@ -0,0 +1,363 @@
|
||||
+/*
|
||||
+ * Ralink MT7620A SoC PCI support
|
||||
+ *
|
||||
+ * Copyright (C) 2007-2013 Bruce Chang
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define RALINK_PCI_MM_MAP_BASE 0x20000000
|
||||
+#define RALINK_PCI_IO_MAP_BASE 0x10160000
|
||||
+
|
||||
+#define RALINK_INT_PCIE0 4
|
||||
+#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000
|
||||
+#define RALINK_SYSCFG1 0x14
|
||||
+#define RALINK_CLKCFG1 0x30
|
||||
+#define RALINK_GPIOMODE 0x60
|
||||
+#define RALINK_PCIE_CLK_GEN 0x7c
|
||||
+#define RALINK_PCIE_CLK_GEN1 0x80
|
||||
+#define PCIEPHY0_CFG 0x90
|
||||
+#define PPLL_CFG1 0x9c
|
||||
+#define PPLL_DRV 0xa0
|
||||
+#define RALINK_PCI_HOST_MODE_EN (1<<7)
|
||||
+#define RALINK_PCIE_RC_MODE_EN (1<<8)
|
||||
+#define RALINK_PCIE_RST (1<<23)
|
||||
+#define RALINK_PCI_RST (1<<24)
|
||||
+#define RALINK_PCI_CLK_EN (1<<19)
|
||||
+#define RALINK_PCIE_CLK_EN (1<<21)
|
||||
+#define PCI_SLOTx2 (1<<11)
|
||||
+#define PCI_SLOTx1 (2<<11)
|
||||
+#define PDRV_SW_SET (1<<31)
|
||||
+#define LC_CKDRVPD_ (1<<19)
|
||||
+
|
||||
+#define RALINK_PCI_CONFIG_ADDR 0x20
|
||||
+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
|
||||
+#define MEMORY_BASE 0x0
|
||||
+#define RALINK_PCIE0_RST (1<<26)
|
||||
+#define RALINK_PCI_BASE 0xB0140000
|
||||
+#define RALINK_PCI_MEMBASE 0x28
|
||||
+#define RALINK_PCI_IOBASE 0x2C
|
||||
+
|
||||
+#define RT6855_PCIE0_OFFSET 0x2000
|
||||
+
|
||||
+#define RALINK_PCI_PCICFG_ADDR 0x00
|
||||
+#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
|
||||
+#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
|
||||
+#define RALINK_PCI0_ID 0x30
|
||||
+#define RALINK_PCI0_CLASS 0x34
|
||||
+#define RALINK_PCI0_SUBID 0x38
|
||||
+#define RALINK_PCI0_STATUS 0x50
|
||||
+#define RALINK_PCI_PCIMSK_ADDR 0x0C
|
||||
+
|
||||
+#define RALINK_PCIE0_CLK_EN (1 << 26)
|
||||
+
|
||||
+#define BUSY 0x80000000
|
||||
+#define WAITRETRY_MAX 10
|
||||
+#define WRITE_MODE (1UL << 23)
|
||||
+#define DATA_SHIFT 0
|
||||
+#define ADDR_SHIFT 8
|
||||
+
|
||||
+
|
||||
+static void __iomem *bridge_base;
|
||||
+static void __iomem *pcie_base;
|
||||
+
|
||||
+static struct reset_control *rstpcie0;
|
||||
+
|
||||
+static inline void bridge_w32(u32 val, unsigned reg)
|
||||
+{
|
||||
+ iowrite32(val, bridge_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 bridge_r32(unsigned reg)
|
||||
+{
|
||||
+ return ioread32(bridge_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void pcie_w32(u32 val, unsigned reg)
|
||||
+{
|
||||
+ iowrite32(val, pcie_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 pcie_r32(unsigned reg)
|
||||
+{
|
||||
+ return ioread32(pcie_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
|
||||
+{
|
||||
+ u32 val = pcie_r32(reg);
|
||||
+ val &= ~clr;
|
||||
+ val |= set;
|
||||
+ pcie_w32(val, reg);
|
||||
+}
|
||||
+
|
||||
+int wait_pciephy_busy(void)
|
||||
+{
|
||||
+ unsigned long reg_value = 0x0, retry = 0;
|
||||
+
|
||||
+ while (1) {
|
||||
+ //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
|
||||
+ reg_value = pcie_r32(PCIEPHY0_CFG);
|
||||
+
|
||||
+ if (reg_value & BUSY)
|
||||
+ mdelay(100);
|
||||
+ else
|
||||
+ break;
|
||||
+ if (retry++ > WAITRETRY_MAX){
|
||||
+ printk("PCIE-PHY retry failed.\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void pcie_phy(unsigned long addr, unsigned long val)
|
||||
+{
|
||||
+ wait_pciephy_busy();
|
||||
+ pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
|
||||
+ mdelay(1);
|
||||
+ wait_pciephy_busy();
|
||||
+}
|
||||
+
|
||||
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
|
||||
+{
|
||||
+ unsigned int slot = PCI_SLOT(devfn);
|
||||
+ u8 func = PCI_FUNC(devfn);
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
|
||||
+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
|
||||
+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ *val = data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
|
||||
+{
|
||||
+ unsigned int slot = PCI_SLOT(devfn);
|
||||
+ u8 func = PCI_FUNC(devfn);
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
|
||||
+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
|
||||
+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ data = val;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+struct pci_ops mt7620a_pci_ops= {
|
||||
+ .read = pci_config_read,
|
||||
+ .write = pci_config_write,
|
||||
+};
|
||||
+
|
||||
+static struct resource mt7620a_res_pci_mem1 = {
|
||||
+ .name = "pci memory",
|
||||
+ .start = RALINK_PCI_MM_MAP_BASE,
|
||||
+ .end = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+static struct resource mt7620a_res_pci_io1 = {
|
||||
+ .name = "pci io",
|
||||
+ .start = RALINK_PCI_IO_MAP_BASE,
|
||||
+ .end = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
|
||||
+ .flags = IORESOURCE_IO,
|
||||
+};
|
||||
+
|
||||
+struct pci_controller mt7620a_controller = {
|
||||
+ .pci_ops = &mt7620a_pci_ops,
|
||||
+ .mem_resource = &mt7620a_res_pci_mem1,
|
||||
+ .io_resource = &mt7620a_res_pci_io1,
|
||||
+ .mem_offset = 0x00000000UL,
|
||||
+ .io_offset = 0x00000000UL,
|
||||
+ .io_map_base = 0xa0000000,
|
||||
+};
|
||||
+
|
||||
+static int mt7620a_pci_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
+
|
||||
+ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
|
||||
+ if (IS_ERR(rstpcie0))
|
||||
+ return PTR_ERR(rstpcie0);
|
||||
+
|
||||
+ bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
|
||||
+ if (!bridge_base)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
|
||||
+ if (!pcie_base)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ iomem_resource.start = 0;
|
||||
+ iomem_resource.end= ~0;
|
||||
+ ioport_resource.start= 0;
|
||||
+ ioport_resource.end = ~0;
|
||||
+
|
||||
+ /* PCIE: bypass PCIe DLL */
|
||||
+ pcie_phy(0x0, 0x80);
|
||||
+ pcie_phy(0x1, 0x04);
|
||||
+ /* PCIE: Elastic buffer control */
|
||||
+ pcie_phy(0x68, 0xB4);
|
||||
+
|
||||
+ reset_control_assert(rstpcie0);
|
||||
+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
|
||||
+ rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
|
||||
+ rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
|
||||
+
|
||||
+ reset_control_deassert(rstpcie0);
|
||||
+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
|
||||
+ printk("MT7620 PPLL unlock\n");
|
||||
+ reset_control_assert(rstpcie0);
|
||||
+ rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
|
||||
+ return 0;
|
||||
+ }
|
||||
+ rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
|
||||
+
|
||||
+ mdelay(100);
|
||||
+ reset_control_assert(rstpcie0);
|
||||
+ rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
|
||||
+
|
||||
+ rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
|
||||
+ rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
|
||||
+
|
||||
+ mdelay(50);
|
||||
+ reset_control_deassert(rstpcie0);
|
||||
+ pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
|
||||
+ reset_control_assert(rstpcie0);
|
||||
+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
|
||||
+ rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
|
||||
+ printk("PCIE0 no card, disable it(RST&CLK)\n");
|
||||
+ }
|
||||
+
|
||||
+ bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
|
||||
+ bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
|
||||
+
|
||||
+ pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
|
||||
+ pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
|
||||
+ pcie_w32(0x08021814, RALINK_PCI0_ID);
|
||||
+ pcie_w32(0x06040001, RALINK_PCI0_CLASS);
|
||||
+ pcie_w32(0x28801814, RALINK_PCI0_SUBID);
|
||||
+ pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
|
||||
+
|
||||
+ register_pci_controller(&mt7620a_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ const struct resource *res;
|
||||
+ u16 cmd;
|
||||
+ u32 val;
|
||||
+ int i, irq = 0;
|
||||
+
|
||||
+ if ((dev->bus->number == 0) && (slot == 0)) {
|
||||
+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
|
||||
+ pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
|
||||
+ pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
|
||||
+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
|
||||
+ irq = RALINK_INT_PCIE0;
|
||||
+ } else {
|
||||
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < 6; i++) {
|
||||
+ res = &dev->resource[i];
|
||||
+ }
|
||||
+
|
||||
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
|
||||
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
|
||||
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
||||
+
|
||||
+ // FIXME
|
||||
+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
|
||||
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
|
||||
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
|
||||
+ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
|
||||
+
|
||||
+ return irq;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id mt7620a_pci_ids[] = {
|
||||
+ { .compatible = "ralink,mt7620a-pci" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
|
||||
+
|
||||
+static struct platform_driver mt7620a_pci_driver = {
|
||||
+ .probe = mt7620a_pci_probe,
|
||||
+ .driver = {
|
||||
+ .name = "mt7620a-pci",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = of_match_ptr(mt7620a_pci_ids),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init mt7620a_pci_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&mt7620a_pci_driver);
|
||||
+}
|
||||
+
|
||||
+arch_initcall(mt7620a_pci_init);
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -26,6 +26,7 @@ choice
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
select CLKEVT_RT3352
|
||||
+ select HW_HAS_PCI
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
From 307ae4eb2504dcc9663a0452a42c38669b8ba815 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 22 Apr 2013 23:23:07 +0200
|
||||
Subject: [PATCH 152/164] watchdog: adds ralink wdt
|
||||
|
||||
Adds the watchdog driver for ralink SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/mt7620.c | 1 +
|
||||
drivers/watchdog/Kconfig | 7 ++
|
||||
drivers/watchdog/Makefile | 1 +
|
||||
drivers/watchdog/rt2880_wdt.c | 208 +++++++++++++++++++++++++++++++++++++++++
|
||||
4 files changed, 217 insertions(+)
|
||||
create mode 100644 drivers/watchdog/rt2880_wdt.c
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
|
||||
|
||||
ralink_clk_add("cpu", cpu_rate);
|
||||
ralink_clk_add("10000100.timer", 40000000);
|
||||
+ ralink_clk_add("10000120.watchdog", 40000000);
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
--- a/drivers/watchdog/Kconfig
|
||||
+++ b/drivers/watchdog/Kconfig
|
||||
@@ -1104,6 +1104,13 @@ config LANTIQ_WDT
|
||||
help
|
||||
Hardware driver for the Lantiq SoC Watchdog Timer.
|
||||
|
||||
+config RALINK_WDT
|
||||
+ tristate "Ralink SoC watchdog"
|
||||
+ select WATCHDOG_CORE
|
||||
+ depends on RALINK
|
||||
+ help
|
||||
+ Hardware driver for the Ralink SoC Watchdog Timer.
|
||||
+
|
||||
# PARISC Architecture
|
||||
|
||||
# POWERPC Architecture
|
||||
--- a/drivers/watchdog/Makefile
|
||||
+++ b/drivers/watchdog/Makefile
|
||||
@@ -134,6 +134,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
|
||||
obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
|
||||
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
|
||||
obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
|
||||
+obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
|
||||
|
||||
# PARISC Architecture
|
||||
|
||||
--- /dev/null
|
||||
+++ b/drivers/watchdog/rt2880_wdt.c
|
||||
@@ -0,0 +1,207 @@
|
||||
+/*
|
||||
+ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
|
||||
+ *
|
||||
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ *
|
||||
+ * This driver was based on: drivers/watchdog/softdog.c
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/watchdog.h>
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <linux/moduleparam.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define SYSC_RSTSTAT 0x38
|
||||
+#define WDT_RST_CAUSE BIT(1)
|
||||
+
|
||||
+#define RALINK_WDT_TIMEOUT 30
|
||||
+#define RALINK_WDT_PRESCALE 65536
|
||||
+
|
||||
+#define TIMER_REG_TMR1LOAD 0x00
|
||||
+#define TIMER_REG_TMR1CTL 0x08
|
||||
+
|
||||
+#define TMRSTAT_TMR1RST BIT(5)
|
||||
+
|
||||
+#define TMR1CTL_ENABLE BIT(7)
|
||||
+#define TMR1CTL_MODE_SHIFT 4
|
||||
+#define TMR1CTL_MODE_MASK 0x3
|
||||
+#define TMR1CTL_MODE_FREE_RUNNING 0x0
|
||||
+#define TMR1CTL_MODE_PERIODIC 0x1
|
||||
+#define TMR1CTL_MODE_TIMEOUT 0x2
|
||||
+#define TMR1CTL_MODE_WDT 0x3
|
||||
+#define TMR1CTL_PRESCALE_MASK 0xf
|
||||
+#define TMR1CTL_PRESCALE_65536 0xf
|
||||
+
|
||||
+static struct clk *rt288x_wdt_clk;
|
||||
+static unsigned long rt288x_wdt_freq;
|
||||
+static void __iomem *rt288x_wdt_base;
|
||||
+
|
||||
+static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||
+module_param(nowayout, bool, 0);
|
||||
+MODULE_PARM_DESC(nowayout,
|
||||
+ "Watchdog cannot be stopped once started (default="
|
||||
+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
|
||||
+
|
||||
+static inline void rt_wdt_w32(unsigned reg, u32 val)
|
||||
+{
|
||||
+ iowrite32(val, rt288x_wdt_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt_wdt_r32(unsigned reg)
|
||||
+{
|
||||
+ return ioread32(rt288x_wdt_base + reg);
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_ping(struct watchdog_device *w)
|
||||
+{
|
||||
+ rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_start(struct watchdog_device *w)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
|
||||
+ t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
|
||||
+ TMR1CTL_PRESCALE_MASK);
|
||||
+ t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
|
||||
+ TMR1CTL_PRESCALE_65536);
|
||||
+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
|
||||
+
|
||||
+ rt288x_wdt_ping(w);
|
||||
+
|
||||
+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
|
||||
+ t |= TMR1CTL_ENABLE;
|
||||
+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_stop(struct watchdog_device *w)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ rt288x_wdt_ping(w);
|
||||
+
|
||||
+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
|
||||
+ t &= ~TMR1CTL_ENABLE;
|
||||
+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
|
||||
+{
|
||||
+ w->timeout = t;
|
||||
+ rt288x_wdt_ping(w);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_bootcause(void)
|
||||
+{
|
||||
+ if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
|
||||
+ return WDIOF_CARDRESET;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct watchdog_info rt288x_wdt_info = {
|
||||
+ .identity = "Ralink Watchdog",
|
||||
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
|
||||
+};
|
||||
+
|
||||
+static struct watchdog_ops rt288x_wdt_ops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .start = rt288x_wdt_start,
|
||||
+ .stop = rt288x_wdt_stop,
|
||||
+ .ping = rt288x_wdt_ping,
|
||||
+ .set_timeout = rt288x_wdt_set_timeout,
|
||||
+};
|
||||
+
|
||||
+static struct watchdog_device rt288x_wdt_dev = {
|
||||
+ .info = &rt288x_wdt_info,
|
||||
+ .ops = &rt288x_wdt_ops,
|
||||
+ .min_timeout = 1,
|
||||
+};
|
||||
+
|
||||
+static int rt288x_wdt_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
|
||||
+ if (IS_ERR(rt288x_wdt_base))
|
||||
+ return PTR_ERR(rt288x_wdt_base);
|
||||
+
|
||||
+ rt288x_wdt_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(rt288x_wdt_clk))
|
||||
+ return PTR_ERR(rt288x_wdt_clk);
|
||||
+
|
||||
+ device_reset(&pdev->dev);
|
||||
+
|
||||
+ rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
|
||||
+
|
||||
+ rt288x_wdt_dev.dev = &pdev->dev;
|
||||
+ rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
|
||||
+
|
||||
+ rt288x_wdt_dev.timeout = rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
|
||||
+
|
||||
+ watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
|
||||
+
|
||||
+ ret = watchdog_register_device(&rt288x_wdt_dev);
|
||||
+ if (!ret)
|
||||
+ dev_info(&pdev->dev, "Initialized\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt288x_wdt_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ watchdog_unregister_device(&rt288x_wdt_dev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rt288x_wdt_shutdown(struct platform_device *pdev)
|
||||
+{
|
||||
+ rt288x_wdt_stop(&rt288x_wdt_dev);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt288x_wdt_match[] = {
|
||||
+ { .compatible = "ralink,rt2880-wdt" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
|
||||
+
|
||||
+static struct platform_driver rt288x_wdt_driver = {
|
||||
+ .probe = rt288x_wdt_probe,
|
||||
+ .remove = rt288x_wdt_remove,
|
||||
+ .shutdown = rt288x_wdt_shutdown,
|
||||
+ .driver = {
|
||||
+ .name = KBUILD_MODNAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = rt288x_wdt_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(rt288x_wdt_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
|
||||
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
|
|
@ -1,353 +0,0 @@
|
|||
From e5a800fb1dc440ee1e4ca656b2ed3f6e2debecca Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 29 Apr 2013 14:40:43 +0200
|
||||
Subject: [PATCH 153/164] i2c: MIPS: adds ralink I2C driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
.../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
|
||||
drivers/i2c/busses/Kconfig | 4 +
|
||||
drivers/i2c/busses/Makefile | 1 +
|
||||
drivers/i2c/busses/i2c-ralink.c | 274 ++++++++++++++++++++
|
||||
4 files changed, 306 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
|
||||
create mode 100644 drivers/i2c/busses/i2c-ralink.c
|
||||
|
||||
Index: linux-3.9.8/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
|
||||
===================================================================
|
||||
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||
+++ linux-3.9.8/Documentation/devicetree/bindings/i2c/i2c-ralink.txt 2013-07-02 11:36:42.944155612 +0200
|
||||
@@ -0,0 +1,27 @@
|
||||
+I2C for Ralink platforms
|
||||
+
|
||||
+Required properties :
|
||||
+- compatible : Must be "link,rt3052-i2c"
|
||||
+- reg: physical base address of the controller and length of memory mapped
|
||||
+ region.
|
||||
+- #address-cells = <1>;
|
||||
+- #size-cells = <0>;
|
||||
+
|
||||
+Optional properties:
|
||||
+- Child nodes conforming to i2c bus binding
|
||||
+
|
||||
+Example :
|
||||
+
|
||||
+palmbus@10000000 {
|
||||
+ i2c@900 {
|
||||
+ compatible = "link,rt3052-i2c";
|
||||
+ reg = <0x900 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hwmon@4b {
|
||||
+ compatible = "national,lm92";
|
||||
+ reg = <0x4b>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
Index: linux-3.9.8/drivers/i2c/busses/Kconfig
|
||||
===================================================================
|
||||
--- linux-3.9.8.orig/drivers/i2c/busses/Kconfig 2013-06-27 19:41:32.000000000 +0200
|
||||
+++ linux-3.9.8/drivers/i2c/busses/Kconfig 2013-07-02 11:36:42.944155612 +0200
|
||||
@@ -628,6 +628,10 @@
|
||||
is necessary for systems where the PXA may be a target on the
|
||||
I2C bus.
|
||||
|
||||
+config I2C_RALINK
|
||||
+ tristate "Ralink I2C Controller"
|
||||
+ select OF_I2C
|
||||
+
|
||||
config HAVE_S3C2410_I2C
|
||||
bool
|
||||
help
|
||||
Index: linux-3.9.8/drivers/i2c/busses/Makefile
|
||||
===================================================================
|
||||
--- linux-3.9.8.orig/drivers/i2c/busses/Makefile 2013-06-27 19:41:32.000000000 +0200
|
||||
+++ linux-3.9.8/drivers/i2c/busses/Makefile 2013-07-02 11:36:42.944155612 +0200
|
||||
@@ -62,6 +62,7 @@
|
||||
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
|
||||
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
|
||||
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
|
||||
+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
|
||||
obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
|
||||
obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
|
||||
obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
|
||||
Index: linux-3.9.8/drivers/i2c/busses/i2c-ralink.c
|
||||
===================================================================
|
||||
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||
+++ linux-3.9.8/drivers/i2c/busses/i2c-ralink.c 2013-07-08 10:56:00.068287905 +0200
|
||||
@@ -0,0 +1,274 @@
|
||||
+/*
|
||||
+ * drivers/i2c/busses/i2c-ralink.c
|
||||
+ *
|
||||
+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
|
||||
+ *
|
||||
+ * This software is licensed under the terms of the GNU General Public
|
||||
+ * License version 2, as published by the Free Software Foundation, and
|
||||
+ * may be copied, distributed, and modified under those terms.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/errno.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/i2c.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of_i2c.h>
|
||||
+#include <linux/err.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define REG_CONFIG_REG 0x00
|
||||
+#define REG_CLKDIV_REG 0x04
|
||||
+#define REG_DEVADDR_REG 0x08
|
||||
+#define REG_ADDR_REG 0x0C
|
||||
+#define REG_DATAOUT_REG 0x10
|
||||
+#define REG_DATAIN_REG 0x14
|
||||
+#define REG_STATUS_REG 0x18
|
||||
+#define REG_STARTXFR_REG 0x1C
|
||||
+#define REG_BYTECNT_REG 0x20
|
||||
+
|
||||
+#define I2C_STARTERR BIT(4)
|
||||
+#define I2C_ACKERR BIT(3)
|
||||
+#define I2C_DATARDY BIT(2)
|
||||
+#define I2C_SDOEMPTY BIT(1)
|
||||
+#define I2C_BUSY BIT(0)
|
||||
+
|
||||
+#define I2C_DEVADLEN_7 (6 << 2)
|
||||
+#define I2C_ADDRDIS BIT(1)
|
||||
+
|
||||
+#define I2C_RETRY 0x400
|
||||
+
|
||||
+#define CLKDIV_VALUE 200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
|
||||
+//#define CLKDIV_VALUE 50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
|
||||
+
|
||||
+#define READ_CMD 0x01
|
||||
+#define WRITE_CMD 0x00
|
||||
+#define READ_BLOCK 64
|
||||
+
|
||||
+static void __iomem *membase;
|
||||
+static struct i2c_adapter *adapter;
|
||||
+
|
||||
+static void rt_i2c_w32(u32 val, unsigned reg)
|
||||
+{
|
||||
+ iowrite32(val, membase + reg);
|
||||
+}
|
||||
+
|
||||
+static u32 rt_i2c_r32(unsigned reg)
|
||||
+{
|
||||
+ return ioread32(membase + reg);
|
||||
+}
|
||||
+
|
||||
+static inline int rt_i2c_wait_rx_done(void)
|
||||
+{
|
||||
+ int retries = I2C_RETRY;
|
||||
+
|
||||
+ do {
|
||||
+ if (!retries--)
|
||||
+ break;
|
||||
+ } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
|
||||
+
|
||||
+ return (retries < 0);
|
||||
+}
|
||||
+
|
||||
+static inline int rt_i2c_wait_idle(void)
|
||||
+{
|
||||
+ int retries = I2C_RETRY;
|
||||
+
|
||||
+ do {
|
||||
+ if (!retries--)
|
||||
+ break;
|
||||
+ } while(rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
|
||||
+
|
||||
+ return (retries < 0);
|
||||
+}
|
||||
+
|
||||
+static inline int rt_i2c_wait_tx_done(void)
|
||||
+{
|
||||
+ int retries = I2C_RETRY;
|
||||
+
|
||||
+ do {
|
||||
+ if (!retries--)
|
||||
+ break;
|
||||
+ } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
|
||||
+
|
||||
+ return (retries < 0);
|
||||
+}
|
||||
+
|
||||
+static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
|
||||
+{
|
||||
+ int i = 0, j = 0, pos = 0;
|
||||
+ int nblock = msg->len / READ_BLOCK;
|
||||
+ int rem = msg->len % READ_BLOCK;
|
||||
+
|
||||
+ if (msg->flags & I2C_M_TEN) {
|
||||
+ printk("10 bits addr not supported\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (msg->flags & I2C_M_RD) {
|
||||
+ for (i = 0; i < nblock; i++) {
|
||||
+ rt_i2c_wait_idle();
|
||||
+ rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
|
||||
+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
|
||||
+ for (j = 0; j < READ_BLOCK; j++) {
|
||||
+ if (rt_i2c_wait_rx_done())
|
||||
+ return -1;
|
||||
+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ rt_i2c_wait_idle();
|
||||
+ rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
|
||||
+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
|
||||
+ for (i = 0; i < rem; i++) {
|
||||
+ if (rt_i2c_wait_rx_done())
|
||||
+ return -1;
|
||||
+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
|
||||
+ }
|
||||
+ } else {
|
||||
+ rt_i2c_wait_idle();
|
||||
+ rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
|
||||
+ for (i = 0; i < msg->len; i++) {
|
||||
+ rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
|
||||
+ rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
|
||||
+ if (rt_i2c_wait_tx_done())
|
||||
+ return -1;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
|
||||
+{
|
||||
+ int i = 0;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (rt_i2c_wait_idle()) {
|
||||
+ printk("i2c transfer failed\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ device_reset(a->dev.parent);
|
||||
+
|
||||
+ rt_i2c_w32(m->addr, REG_DEVADDR_REG);
|
||||
+ rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
|
||||
+ rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
|
||||
+
|
||||
+ for (i = 0; i < n && !ret; i++)
|
||||
+ ret = rt_i2c_handle_msg(a, &m[i]);
|
||||
+
|
||||
+ if (ret) {
|
||||
+ printk("i2c transfer failed\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ return n;
|
||||
+}
|
||||
+
|
||||
+static u32 rt_i2c_func(struct i2c_adapter *a)
|
||||
+{
|
||||
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
+}
|
||||
+
|
||||
+static const struct i2c_algorithm rt_i2c_algo = {
|
||||
+ .master_xfer = rt_i2c_master_xfer,
|
||||
+ .functionality = rt_i2c_func,
|
||||
+};
|
||||
+
|
||||
+static int rt_i2c_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!res) {
|
||||
+ dev_err(&pdev->dev, "no memory resource found\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
|
||||
+ if (!adapter) {
|
||||
+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ membase = devm_request_and_ioremap(&pdev->dev, res);
|
||||
+ if (IS_ERR(membase))
|
||||
+ return PTR_ERR(membase);
|
||||
+
|
||||
+ strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
|
||||
+ adapter->owner = THIS_MODULE;
|
||||
+ adapter->nr = pdev->id;
|
||||
+ adapter->timeout = HZ;
|
||||
+ adapter->algo = &rt_i2c_algo;
|
||||
+ adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
+ adapter->dev.parent = &pdev->dev;
|
||||
+ adapter->dev.of_node = pdev->dev.of_node;
|
||||
+
|
||||
+ ret = i2c_add_numbered_adapter(adapter);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ of_i2c_register_devices(adapter);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, adapter);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "loaded\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rt_i2c_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ platform_set_drvdata(pdev, NULL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id i2c_rt_dt_ids[] = {
|
||||
+ { .compatible = "ralink,rt2880-i2c", },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
|
||||
+
|
||||
+static struct platform_driver rt_i2c_driver = {
|
||||
+ .probe = rt_i2c_probe,
|
||||
+ .remove = rt_i2c_remove,
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = "i2c-ralink",
|
||||
+ .of_match_table = i2c_rt_dt_ids,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init i2c_rt_init (void)
|
||||
+{
|
||||
+ return platform_driver_register(&rt_i2c_driver);
|
||||
+}
|
||||
+subsys_initcall(i2c_rt_init);
|
||||
+
|
||||
+static void __exit i2c_rt_exit (void)
|
||||
+{
|
||||
+ platform_driver_unregister(&rt_i2c_driver);
|
||||
+}
|
||||
+
|
||||
+module_exit (i2c_rt_exit);
|
||||
+
|
||||
+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
|
||||
+MODULE_DESCRIPTION("Ralink I2c host driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_ALIAS("platform:Ralink-I2C");
|
||||
|
|
@ -1,529 +0,0 @@
|
|||
From d6cfbdfa001891894efe078a49ad82ac8a932dbb Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 20 May 2013 15:42:01 +0200
|
||||
Subject: [PATCH 154/164] reset: Add reset controller API
|
||||
|
||||
backport from v3.10-rc1
|
||||
61fc41317666be400802ac793f47de816ef7bd57
|
||||
6034bb22d8387708075c083385e5d2e1072a4f33
|
||||
4e11f848c65b1c87782cb232a6e3b47a9d4c1f98
|
||||
|
||||
This adds a simple API for devices to request being reset
|
||||
by separate reset controller hardware and implements the
|
||||
reset signal device tree binding.
|
||||
|
||||
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
Reviewed-by: Stephen Warren <swarren@nvidia.com>
|
||||
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
|
||||
Reviewed-by: Marek Vasut <marex@denx.de>
|
||||
Reviewed-by: Pavel Machek <pavel@ucw.cz>
|
||||
---
|
||||
Documentation/devicetree/bindings/reset/reset.txt | 75 ++++++
|
||||
drivers/Kconfig | 2 +
|
||||
drivers/Makefile | 3 +
|
||||
drivers/reset/Kconfig | 13 +
|
||||
drivers/reset/Makefile | 1 +
|
||||
drivers/reset/core.c | 297 +++++++++++++++++++++
|
||||
include/linux/reset-controller.h | 51 ++++
|
||||
include/linux/reset.h | 17 ++
|
||||
8 files changed, 459 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/reset/reset.txt
|
||||
create mode 100644 drivers/reset/Kconfig
|
||||
create mode 100644 drivers/reset/Makefile
|
||||
create mode 100644 drivers/reset/core.c
|
||||
create mode 100644 include/linux/reset-controller.h
|
||||
create mode 100644 include/linux/reset.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/reset/reset.txt
|
||||
@@ -0,0 +1,75 @@
|
||||
+= Reset Signal Device Tree Bindings =
|
||||
+
|
||||
+This binding is intended to represent the hardware reset signals present
|
||||
+internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
|
||||
+standalone chips are most likely better represented as GPIOs, although there
|
||||
+are likely to be exceptions to this rule.
|
||||
+
|
||||
+Hardware blocks typically receive a reset signal. This signal is generated by
|
||||
+a reset provider (e.g. power management or clock module) and received by a
|
||||
+reset consumer (the module being reset, or a module managing when a sub-
|
||||
+ordinate module is reset). This binding exists to represent the provider and
|
||||
+consumer, and provide a way to couple the two together.
|
||||
+
|
||||
+A reset signal is represented by the phandle of the provider, plus a reset
|
||||
+specifier - a list of DT cells that represents the reset signal within the
|
||||
+provider. The length (number of cells) and semantics of the reset specifier
|
||||
+are dictated by the binding of the reset provider, although common schemes
|
||||
+are described below.
|
||||
+
|
||||
+A word on where to place reset signal consumers in device tree: It is possible
|
||||
+in hardware for a reset signal to affect multiple logically separate HW blocks
|
||||
+at once. In this case, it would be unwise to represent this reset signal in
|
||||
+the DT node of each affected HW block, since if activated, an unrelated block
|
||||
+may be reset. Instead, reset signals should be represented in the DT node
|
||||
+where it makes most sense to control it; this may be a bus node if all
|
||||
+children of the bus are affected by the reset signal, or an individual HW
|
||||
+block node for dedicated reset signals. The intent of this binding is to give
|
||||
+appropriate software access to the reset signals in order to manage the HW,
|
||||
+rather than to slavishly enumerate the reset signal that affects each HW
|
||||
+block.
|
||||
+
|
||||
+= Reset providers =
|
||||
+
|
||||
+Required properties:
|
||||
+#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
|
||||
+ with a single reset output and 1 for nodes with multiple
|
||||
+ reset outputs.
|
||||
+
|
||||
+For example:
|
||||
+
|
||||
+ rst: reset-controller {
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+= Reset consumers =
|
||||
+
|
||||
+Required properties:
|
||||
+resets: List of phandle and reset specifier pairs, one pair
|
||||
+ for each reset signal that affects the device, or that the
|
||||
+ device manages. Note: if the reset provider specifies '0' for
|
||||
+ #reset-cells, then only the phandle portion of the pair will
|
||||
+ appear.
|
||||
+
|
||||
+Optional properties:
|
||||
+reset-names: List of reset signal name strings sorted in the same order as
|
||||
+ the resets property. Consumers drivers will use reset-names to
|
||||
+ match reset signal names with reset specifiers.
|
||||
+
|
||||
+For example:
|
||||
+
|
||||
+ device {
|
||||
+ resets = <&rst 20>;
|
||||
+ reset-names = "reset";
|
||||
+ };
|
||||
+
|
||||
+This represents a device with a single reset signal named "reset".
|
||||
+
|
||||
+ bus {
|
||||
+ resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
|
||||
+ reset-names = "i2s1", "i2s2", "dma", "mixer";
|
||||
+ };
|
||||
+
|
||||
+This represents a bus that controls the reset signal of each of four sub-
|
||||
+ordinate devices. Consider for example a bus that fails to operate unless no
|
||||
+child device has reset asserted.
|
||||
--- a/drivers/Kconfig
|
||||
+++ b/drivers/Kconfig
|
||||
@@ -164,4 +164,6 @@ source "drivers/irqchip/Kconfig"
|
||||
|
||||
source "drivers/ipack/Kconfig"
|
||||
|
||||
+source "drivers/reset/Kconfig"
|
||||
+
|
||||
endmenu
|
||||
--- a/drivers/Makefile
|
||||
+++ b/drivers/Makefile
|
||||
@@ -38,6 +38,9 @@ obj-$(CONFIG_XEN) += xen/
|
||||
# regulators early, since some subsystems rely on them to initialize
|
||||
obj-$(CONFIG_REGULATOR) += regulator/
|
||||
|
||||
+# reset controllers early, since gpu drivers might rely on them to initialize
|
||||
+obj-$(CONFIG_RESET_CONTROLLER) += reset/
|
||||
+
|
||||
# tty/ comes before char/ so that the VT console is the boot-time
|
||||
# default.
|
||||
obj-y += tty/
|
||||
--- /dev/null
|
||||
+++ b/drivers/reset/Kconfig
|
||||
@@ -0,0 +1,13 @@
|
||||
+config ARCH_HAS_RESET_CONTROLLER
|
||||
+ bool
|
||||
+
|
||||
+menuconfig RESET_CONTROLLER
|
||||
+ bool "Reset Controller Support"
|
||||
+ default y if ARCH_HAS_RESET_CONTROLLER
|
||||
+ help
|
||||
+ Generic Reset Controller support.
|
||||
+
|
||||
+ This framework is designed to abstract reset handling of devices
|
||||
+ via GPIOs or SoC-internal reset controller modules.
|
||||
+
|
||||
+ If unsure, say no.
|
||||
--- /dev/null
|
||||
+++ b/drivers/reset/Makefile
|
||||
@@ -0,0 +1 @@
|
||||
+obj-$(CONFIG_RESET_CONTROLLER) += core.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/reset/core.c
|
||||
@@ -0,0 +1,297 @@
|
||||
+/*
|
||||
+ * Reset Controller framework
|
||||
+ *
|
||||
+ * Copyright 2013 Philipp Zabel, Pengutronix
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version.
|
||||
+ */
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/export.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/reset-controller.h>
|
||||
+#include <linux/slab.h>
|
||||
+
|
||||
+static DEFINE_MUTEX(reset_controller_list_mutex);
|
||||
+static LIST_HEAD(reset_controller_list);
|
||||
+
|
||||
+/**
|
||||
+ * struct reset_control - a reset control
|
||||
+ * @rcdev: a pointer to the reset controller device
|
||||
+ * this reset control belongs to
|
||||
+ * @id: ID of the reset controller in the reset
|
||||
+ * controller device
|
||||
+ */
|
||||
+struct reset_control {
|
||||
+ struct reset_controller_dev *rcdev;
|
||||
+ struct device *dev;
|
||||
+ unsigned int id;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
+ * of_reset_simple_xlate - translate reset_spec to the reset line number
|
||||
+ * @rcdev: a pointer to the reset controller device
|
||||
+ * @reset_spec: reset line specifier as found in the device tree
|
||||
+ * @flags: a flags pointer to fill in (optional)
|
||||
+ *
|
||||
+ * This simple translation function should be used for reset controllers
|
||||
+ * with 1:1 mapping, where reset lines can be indexed by number without gaps.
|
||||
+ */
|
||||
+int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
|
||||
+ const struct of_phandle_args *reset_spec)
|
||||
+{
|
||||
+ if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (reset_spec->args[0] >= rcdev->nr_resets)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return reset_spec->args[0];
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(of_reset_simple_xlate);
|
||||
+
|
||||
+/**
|
||||
+ * reset_controller_register - register a reset controller device
|
||||
+ * @rcdev: a pointer to the initialized reset controller device
|
||||
+ */
|
||||
+int reset_controller_register(struct reset_controller_dev *rcdev)
|
||||
+{
|
||||
+ if (!rcdev->of_xlate) {
|
||||
+ rcdev->of_reset_n_cells = 1;
|
||||
+ rcdev->of_xlate = of_reset_simple_xlate;
|
||||
+ }
|
||||
+
|
||||
+ mutex_lock(&reset_controller_list_mutex);
|
||||
+ list_add(&rcdev->list, &reset_controller_list);
|
||||
+ mutex_unlock(&reset_controller_list_mutex);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_controller_register);
|
||||
+
|
||||
+/**
|
||||
+ * reset_controller_unregister - unregister a reset controller device
|
||||
+ * @rcdev: a pointer to the reset controller device
|
||||
+ */
|
||||
+void reset_controller_unregister(struct reset_controller_dev *rcdev)
|
||||
+{
|
||||
+ mutex_lock(&reset_controller_list_mutex);
|
||||
+ list_del(&rcdev->list);
|
||||
+ mutex_unlock(&reset_controller_list_mutex);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_controller_unregister);
|
||||
+
|
||||
+/**
|
||||
+ * reset_control_reset - reset the controlled device
|
||||
+ * @rstc: reset controller
|
||||
+ */
|
||||
+int reset_control_reset(struct reset_control *rstc)
|
||||
+{
|
||||
+ if (rstc->rcdev->ops->reset)
|
||||
+ return rstc->rcdev->ops->reset(rstc->rcdev, rstc->id);
|
||||
+
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_control_reset);
|
||||
+
|
||||
+/**
|
||||
+ * reset_control_assert - asserts the reset line
|
||||
+ * @rstc: reset controller
|
||||
+ */
|
||||
+int reset_control_assert(struct reset_control *rstc)
|
||||
+{
|
||||
+ if (rstc->rcdev->ops->assert)
|
||||
+ return rstc->rcdev->ops->assert(rstc->rcdev, rstc->id);
|
||||
+
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_control_assert);
|
||||
+
|
||||
+/**
|
||||
+ * reset_control_deassert - deasserts the reset line
|
||||
+ * @rstc: reset controller
|
||||
+ */
|
||||
+int reset_control_deassert(struct reset_control *rstc)
|
||||
+{
|
||||
+ if (rstc->rcdev->ops->deassert)
|
||||
+ return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id);
|
||||
+
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_control_deassert);
|
||||
+
|
||||
+/**
|
||||
+ * reset_control_get - Lookup and obtain a reference to a reset controller.
|
||||
+ * @dev: device to be reset by the controller
|
||||
+ * @id: reset line name
|
||||
+ *
|
||||
+ * Returns a struct reset_control or IS_ERR() condition containing errno.
|
||||
+ *
|
||||
+ * Use of id names is optional.
|
||||
+ */
|
||||
+struct reset_control *reset_control_get(struct device *dev, const char *id)
|
||||
+{
|
||||
+ struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER);
|
||||
+ struct reset_controller_dev *r, *rcdev;
|
||||
+ struct of_phandle_args args;
|
||||
+ int index = 0;
|
||||
+ int rstc_id;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!dev)
|
||||
+ return ERR_PTR(-EINVAL);
|
||||
+
|
||||
+ if (id)
|
||||
+ index = of_property_match_string(dev->of_node,
|
||||
+ "reset-names", id);
|
||||
+ ret = of_parse_phandle_with_args(dev->of_node, "resets", "#reset-cells",
|
||||
+ index, &args);
|
||||
+ if (ret)
|
||||
+ return ERR_PTR(ret);
|
||||
+
|
||||
+ mutex_lock(&reset_controller_list_mutex);
|
||||
+ rcdev = NULL;
|
||||
+ list_for_each_entry(r, &reset_controller_list, list) {
|
||||
+ if (args.np == r->of_node) {
|
||||
+ rcdev = r;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ of_node_put(args.np);
|
||||
+
|
||||
+ if (!rcdev) {
|
||||
+ mutex_unlock(&reset_controller_list_mutex);
|
||||
+ return ERR_PTR(-ENODEV);
|
||||
+ }
|
||||
+
|
||||
+ rstc_id = rcdev->of_xlate(rcdev, &args);
|
||||
+ if (rstc_id < 0) {
|
||||
+ mutex_unlock(&reset_controller_list_mutex);
|
||||
+ return ERR_PTR(rstc_id);
|
||||
+ }
|
||||
+
|
||||
+ try_module_get(rcdev->owner);
|
||||
+ mutex_unlock(&reset_controller_list_mutex);
|
||||
+
|
||||
+ rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
|
||||
+ if (!rstc) {
|
||||
+ module_put(rcdev->owner);
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+ }
|
||||
+
|
||||
+ rstc->dev = dev;
|
||||
+ rstc->rcdev = rcdev;
|
||||
+ rstc->id = rstc_id;
|
||||
+
|
||||
+ return rstc;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_control_get);
|
||||
+
|
||||
+/**
|
||||
+ * reset_control_put - free the reset controller
|
||||
+ * @rstc: reset controller
|
||||
+ */
|
||||
+
|
||||
+void reset_control_put(struct reset_control *rstc)
|
||||
+{
|
||||
+ if (IS_ERR(rstc))
|
||||
+ return;
|
||||
+
|
||||
+ module_put(rstc->rcdev->owner);
|
||||
+ kfree(rstc);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(reset_control_put);
|
||||
+
|
||||
+static void devm_reset_control_release(struct device *dev, void *res)
|
||||
+{
|
||||
+ reset_control_put(*(struct reset_control **)res);
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * devm_reset_control_get - resource managed reset_control_get()
|
||||
+ * @dev: device to be reset by the controller
|
||||
+ * @id: reset line name
|
||||
+ *
|
||||
+ * Managed reset_control_get(). For reset controllers returned from this
|
||||
+ * function, reset_control_put() is called automatically on driver detach.
|
||||
+ * See reset_control_get() for more information.
|
||||
+ */
|
||||
+struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
|
||||
+{
|
||||
+ struct reset_control **ptr, *rstc;
|
||||
+
|
||||
+ ptr = devres_alloc(devm_reset_control_release, sizeof(*ptr),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!ptr)
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+
|
||||
+ rstc = reset_control_get(dev, id);
|
||||
+ if (!IS_ERR(rstc)) {
|
||||
+ *ptr = rstc;
|
||||
+ devres_add(dev, ptr);
|
||||
+ } else {
|
||||
+ devres_free(ptr);
|
||||
+ }
|
||||
+
|
||||
+ return rstc;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(devm_reset_control_get);
|
||||
+
|
||||
+static int devm_reset_control_match(struct device *dev, void *res, void *data)
|
||||
+{
|
||||
+ struct reset_control **rstc = res;
|
||||
+ if (WARN_ON(!rstc || !*rstc))
|
||||
+ return 0;
|
||||
+ return *rstc == data;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * devm_reset_control_put - resource managed reset_control_put()
|
||||
+ * @rstc: reset controller to free
|
||||
+ *
|
||||
+ * Deallocate a reset control allocated withd devm_reset_control_get().
|
||||
+ * This function will not need to be called normally, as devres will take
|
||||
+ * care of freeing the resource.
|
||||
+ */
|
||||
+void devm_reset_control_put(struct reset_control *rstc)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = devres_release(rstc->dev, devm_reset_control_release,
|
||||
+ devm_reset_control_match, rstc);
|
||||
+ if (ret)
|
||||
+ WARN_ON(ret);
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(devm_reset_control_put);
|
||||
+
|
||||
+/**
|
||||
+ * device_reset - find reset controller associated with the device
|
||||
+ * and perform reset
|
||||
+ * @dev: device to be reset by the controller
|
||||
+ *
|
||||
+ * Convenience wrapper for reset_control_get() and reset_control_reset().
|
||||
+ * This is useful for the common case of devices with single, dedicated reset
|
||||
+ * lines.
|
||||
+ */
|
||||
+int device_reset(struct device *dev)
|
||||
+{
|
||||
+ struct reset_control *rstc;
|
||||
+ int ret;
|
||||
+
|
||||
+ rstc = reset_control_get(dev, NULL);
|
||||
+ if (IS_ERR(rstc))
|
||||
+ return PTR_ERR(rstc);
|
||||
+
|
||||
+ ret = reset_control_reset(rstc);
|
||||
+
|
||||
+ reset_control_put(rstc);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(device_reset);
|
||||
--- /dev/null
|
||||
+++ b/include/linux/reset-controller.h
|
||||
@@ -0,0 +1,51 @@
|
||||
+#ifndef _LINUX_RESET_CONTROLLER_H_
|
||||
+#define _LINUX_RESET_CONTROLLER_H_
|
||||
+
|
||||
+#include <linux/list.h>
|
||||
+
|
||||
+struct reset_controller_dev;
|
||||
+
|
||||
+/**
|
||||
+ * struct reset_control_ops
|
||||
+ *
|
||||
+ * @reset: for self-deasserting resets, does all necessary
|
||||
+ * things to reset the device
|
||||
+ * @assert: manually assert the reset line, if supported
|
||||
+ * @deassert: manually deassert the reset line, if supported
|
||||
+ */
|
||||
+struct reset_control_ops {
|
||||
+ int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
+ int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
+ int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
+};
|
||||
+
|
||||
+struct module;
|
||||
+struct device_node;
|
||||
+
|
||||
+/**
|
||||
+ * struct reset_controller_dev - reset controller entity that might
|
||||
+ * provide multiple reset controls
|
||||
+ * @ops: a pointer to device specific struct reset_control_ops
|
||||
+ * @owner: kernel module of the reset controller driver
|
||||
+ * @list: internal list of reset controller devices
|
||||
+ * @of_node: corresponding device tree node as phandle target
|
||||
+ * @of_reset_n_cells: number of cells in reset line specifiers
|
||||
+ * @of_xlate: translation function to translate from specifier as found in the
|
||||
+ * device tree to id as given to the reset control ops
|
||||
+ * @nr_resets: number of reset controls in this reset controller device
|
||||
+ */
|
||||
+struct reset_controller_dev {
|
||||
+ struct reset_control_ops *ops;
|
||||
+ struct module *owner;
|
||||
+ struct list_head list;
|
||||
+ struct device_node *of_node;
|
||||
+ int of_reset_n_cells;
|
||||
+ int (*of_xlate)(struct reset_controller_dev *rcdev,
|
||||
+ const struct of_phandle_args *reset_spec);
|
||||
+ unsigned int nr_resets;
|
||||
+};
|
||||
+
|
||||
+int reset_controller_register(struct reset_controller_dev *rcdev);
|
||||
+void reset_controller_unregister(struct reset_controller_dev *rcdev);
|
||||
+
|
||||
+#endif
|
||||
--- /dev/null
|
||||
+++ b/include/linux/reset.h
|
||||
@@ -0,0 +1,17 @@
|
||||
+#ifndef _LINUX_RESET_H_
|
||||
+#define _LINUX_RESET_H_
|
||||
+
|
||||
+struct device;
|
||||
+struct reset_control;
|
||||
+
|
||||
+int reset_control_reset(struct reset_control *rstc);
|
||||
+int reset_control_assert(struct reset_control *rstc);
|
||||
+int reset_control_deassert(struct reset_control *rstc);
|
||||
+
|
||||
+struct reset_control *reset_control_get(struct device *dev, const char *id);
|
||||
+void reset_control_put(struct reset_control *rstc);
|
||||
+struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
|
||||
+
|
||||
+int device_reset(struct device *dev);
|
||||
+
|
||||
+#endif
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
From 4bec674c9f3f0bc137cf5aa4d2cb01e9f8027b3d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 8 May 2013 22:08:39 +0200
|
||||
Subject: [PATCH 155/164] reset: MIPS: ralink: add core/device reset wrapper
|
||||
|
||||
Add a helper for reseting different devices ont he SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/Kconfig | 1 +
|
||||
arch/mips/ralink/of.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/reset.c | 1 +
|
||||
3 files changed, 61 insertions(+)
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -444,6 +444,7 @@ config RALINK
|
||||
select HAVE_MACH_CLKDEV
|
||||
select CLKDEV_LOOKUP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
+ select ARCH_HAS_RESET_CONTROLLER
|
||||
|
||||
config SGI_IP22
|
||||
bool "SGI IP22 (Indy/Indigo2)"
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -14,16 +14,22 @@
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_address.h>
|
||||
+#include <linux/reset-controller.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
#include "common.h"
|
||||
|
||||
+#define SYSC_REG_RESET_CTRL 0x034
|
||||
+
|
||||
__iomem void *rt_sysc_membase;
|
||||
__iomem void *rt_memc_membase;
|
||||
|
||||
@@ -96,6 +102,53 @@ void __init plat_mem_setup(void)
|
||||
soc_info.mem_size_max * SZ_1M);
|
||||
}
|
||||
|
||||
+static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val |= BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_deassert_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (id < 8)
|
||||
+ return -1;
|
||||
+
|
||||
+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
+ val &= ~BIT(id);
|
||||
+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ralink_reset_device(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
+{
|
||||
+ ralink_assert_device(rcdev, id);
|
||||
+ return ralink_deassert_device(rcdev, id);
|
||||
+}
|
||||
+
|
||||
+static struct reset_control_ops reset_ops = {
|
||||
+ .reset = ralink_reset_device,
|
||||
+ .assert = ralink_assert_device,
|
||||
+ .deassert = ralink_deassert_device,
|
||||
+};
|
||||
+
|
||||
+static struct reset_controller_dev reset_dev = {
|
||||
+ .ops = &reset_ops,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .nr_resets = 32,
|
||||
+ .of_reset_n_cells = 1,
|
||||
+};
|
||||
+
|
||||
static int __init plat_of_setup(void)
|
||||
{
|
||||
static struct of_device_id of_ids[3];
|
||||
@@ -110,6 +163,12 @@ static int __init plat_of_setup(void)
|
||||
if (of_platform_populate(NULL, of_ids, NULL, NULL))
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
+ reset_dev.of_node = of_find_compatible_node(NULL, NULL, "ralink,rt2880-reset");
|
||||
+ if (!reset_dev.of_node)
|
||||
+ panic("Failed to find reset controller node");
|
||||
+
|
||||
+ reset_controller_register(&reset_dev);
|
||||
+
|
||||
ralink_pinmux();
|
||||
|
||||
return 0;
|
||||
--- a/arch/mips/ralink/reset.c
|
||||
+++ b/arch/mips/ralink/reset.c
|
||||
@@ -10,6 +10,7 @@
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
From 14b015461adfb540ee46baf432691cc9eda6c046 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 17 Mar 2013 09:29:15 +0100
|
||||
Subject: [PATCH 156/164] NET: add of_get_mac_address_mtd()
|
||||
|
||||
Many embedded devices have information such as mac addresses stored inside mtd
|
||||
devices. This patch allows us to add a property inside a node describing a
|
||||
network interface. The new property points at a mtd partition with an offset
|
||||
where the mac address can be found.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++
|
||||
include/linux/of_net.h | 1 +
|
||||
2 files changed, 38 insertions(+)
|
||||
|
||||
--- a/drivers/of/of_net.c
|
||||
+++ b/drivers/of/of_net.c
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/export.h>
|
||||
+#include <linux/mtd/mtd.h>
|
||||
|
||||
/**
|
||||
* It maps 'enum phy_interface_t' found in include/linux/phy.h
|
||||
@@ -92,3 +93,39 @@ const void *of_get_mac_address(struct de
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(of_get_mac_address);
|
||||
+
|
||||
+int of_get_mac_address_mtd(struct device_node *np, void *mac)
|
||||
+{
|
||||
+ struct device_node *mtd_np = NULL;
|
||||
+ size_t retlen;
|
||||
+ int size, ret;
|
||||
+ struct mtd_info *mtd;
|
||||
+ const char *part;
|
||||
+ const __be32 *list;
|
||||
+ phandle phandle;
|
||||
+
|
||||
+ list = of_get_property(np, "mtd-mac-address", &size);
|
||||
+ if (!list || (size != (2 * sizeof(*list))))
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ phandle = be32_to_cpup(list++);
|
||||
+ if (phandle)
|
||||
+ mtd_np = of_find_node_by_phandle(phandle);
|
||||
+
|
||||
+ if (!mtd_np)
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ part = of_get_property(mtd_np, "label", NULL);
|
||||
+ if (!part)
|
||||
+ part = mtd_np->name;
|
||||
+
|
||||
+ mtd = get_mtd_device_nm(part);
|
||||
+ if (IS_ERR(mtd))
|
||||
+ return PTR_ERR(mtd);
|
||||
+
|
||||
+ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
|
||||
+ put_mtd_device(mtd);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
|
||||
--- a/include/linux/of_net.h
|
||||
+++ b/include/linux/of_net.h
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/of.h>
|
||||
extern const int of_get_phy_mode(struct device_node *np);
|
||||
extern const void *of_get_mac_address(struct device_node *np);
|
||||
+extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_OF_NET_H */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
From 611c89720d9992d54da93bd946000c574d23f2b7 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 11 May 2013 23:40:19 +0200
|
||||
Subject: [PATCH 157/164] NET: multi phy support
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/net/phy/phy.c | 9 ++++++---
|
||||
include/linux/phy.h | 2 +-
|
||||
2 files changed, 7 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/phy.c
|
||||
+++ b/drivers/net/phy/phy.c
|
||||
@@ -847,7 +847,8 @@ void phy_state_machine(struct work_struc
|
||||
* negotiation for now */
|
||||
if (!phydev->link) {
|
||||
phydev->state = PHY_NOLINK;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
break;
|
||||
}
|
||||
@@ -938,7 +939,8 @@ void phy_state_machine(struct work_struc
|
||||
netif_carrier_on(phydev->attached_dev);
|
||||
} else {
|
||||
phydev->state = PHY_NOLINK;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
}
|
||||
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
@@ -950,7 +952,8 @@ void phy_state_machine(struct work_struc
|
||||
case PHY_HALTED:
|
||||
if (phydev->link) {
|
||||
phydev->link = 0;
|
||||
- netif_carrier_off(phydev->attached_dev);
|
||||
+ if (!phydev->no_auto_carrier_off)
|
||||
+ netif_carrier_off(phydev->attached_dev);
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
}
|
||||
break;
|
||||
--- a/include/linux/phy.h
|
||||
+++ b/include/linux/phy.h
|
||||
@@ -298,7 +298,7 @@ struct phy_device {
|
||||
|
||||
struct phy_c45_device_ids c45_ids;
|
||||
bool is_c45;
|
||||
-
|
||||
+ bool no_auto_carrier_off;
|
||||
enum phy_state state;
|
||||
|
||||
u32 dev_flags;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,228 +0,0 @@
|
|||
From efe391a3614b98a0f84fd49e63b4009185ff9a1a Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 2 May 2013 23:29:08 +0200
|
||||
Subject: [PATCH 160/164] USB: phy: add ralink SoC driver
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
drivers/usb/phy/Kconfig | 8 ++
|
||||
drivers/usb/phy/Makefile | 1 +
|
||||
drivers/usb/phy/ralink-phy.c | 191 ++++++++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 200 insertions(+)
|
||||
create mode 100644 drivers/usb/phy/ralink-phy.c
|
||||
|
||||
--- a/drivers/usb/phy/Kconfig
|
||||
+++ b/drivers/usb/phy/Kconfig
|
||||
@@ -74,3 +74,11 @@ config SAMSUNG_USBPHY
|
||||
help
|
||||
Enable this to support Samsung USB phy controller for samsung
|
||||
SoCs.
|
||||
+
|
||||
+config RALINK_USBPHY
|
||||
+ bool "Ralink USB PHY controller Driver"
|
||||
+ depends on MIPS && RALINK
|
||||
+ select USB_OTG_UTILS
|
||||
+ help
|
||||
+ Enable this to support ralink USB phy controller for ralink
|
||||
+ SoCs.
|
||||
--- a/drivers/usb/phy/Makefile
|
||||
+++ b/drivers/usb/phy/Makefile
|
||||
@@ -12,3 +12,4 @@ obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.
|
||||
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
|
||||
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
|
||||
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
|
||||
+obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/usb/phy/ralink-phy.c
|
||||
@@ -0,0 +1,191 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ *
|
||||
+ * based on: Renesas R-Car USB phy driver
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/usb/otg.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/spinlock.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/reset.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
+#define RT_SYSC_REG_SYSCFG1 0x014
|
||||
+#define RT_SYSC_REG_CLKCFG1 0x030
|
||||
+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
|
||||
+
|
||||
+#define RT_RSTCTRL_UDEV BIT(25)
|
||||
+#define RT_RSTCTRL_UHST BIT(22)
|
||||
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
|
||||
+
|
||||
+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
|
||||
+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
|
||||
+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
|
||||
+
|
||||
+#define USB_PHY_UTMI_8B60M BIT(1)
|
||||
+#define UDEV_WAKEUP BIT(0)
|
||||
+
|
||||
+static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
|
||||
+static struct reset_control *rstdev;
|
||||
+static struct reset_control *rsthost;
|
||||
+static u32 phy_clk;
|
||||
+
|
||||
+static void usb_phy_enable(int state)
|
||||
+{
|
||||
+ if (state)
|
||||
+ rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
|
||||
+ else
|
||||
+ rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
|
||||
+ mdelay(100);
|
||||
+}
|
||||
+
|
||||
+static int usb_power_on(struct usb_phy *phy)
|
||||
+{
|
||||
+ if (atomic_inc_return(&usb_pwr_ref) == 1) {
|
||||
+ u32 t;
|
||||
+
|
||||
+ usb_phy_enable(1);
|
||||
+
|
||||
+// reset_control_assert(rstdev);
|
||||
+// reset_control_assert(rsthost);
|
||||
+
|
||||
+ if (OTG_STATE_B_HOST) {
|
||||
+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
|
||||
+ reset_control_deassert(rsthost);
|
||||
+ } else {
|
||||
+ rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
|
||||
+ reset_control_deassert(rstdev);
|
||||
+ }
|
||||
+ mdelay(100);
|
||||
+
|
||||
+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
|
||||
+ dev_info(phy->dev, "remote usb device wakeup %s\n",
|
||||
+ (t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
|
||||
+ if (t & USB_PHY_UTMI_8B60M)
|
||||
+ dev_info(phy->dev, "UTMI 8bit 60MHz\n");
|
||||
+ else
|
||||
+ dev_info(phy->dev, "UTMI 16bit 30MHz\n");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void usb_power_off(struct usb_phy *phy)
|
||||
+{
|
||||
+ if (atomic_dec_return(&usb_pwr_ref) == 0) {
|
||||
+ usb_phy_enable(0);
|
||||
+ reset_control_assert(rstdev);
|
||||
+ reset_control_assert(rsthost);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int usb_set_host(struct usb_otg *otg, struct usb_bus *host)
|
||||
+{
|
||||
+ otg->gadget = NULL;
|
||||
+ otg->host = host;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int usb_set_peripheral(struct usb_otg *otg,
|
||||
+ struct usb_gadget *gadget)
|
||||
+{
|
||||
+ otg->host = NULL;
|
||||
+ otg->gadget = gadget;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id ralink_usbphy_dt_match[] = {
|
||||
+ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
|
||||
+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);
|
||||
+
|
||||
+static int usb_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *match;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct usb_otg *otg;
|
||||
+ struct usb_phy *phy;
|
||||
+ int ret;
|
||||
+
|
||||
+ match = of_match_device(ralink_usbphy_dt_match, &pdev->dev);
|
||||
+ phy_clk = (int) match->data;
|
||||
+
|
||||
+ rsthost = devm_reset_control_get(&pdev->dev, "host");
|
||||
+ if (IS_ERR(rsthost))
|
||||
+ return PTR_ERR(rsthost);
|
||||
+
|
||||
+ rstdev = devm_reset_control_get(&pdev->dev, "device");
|
||||
+ if (IS_ERR(rstdev))
|
||||
+ return PTR_ERR(rstdev);
|
||||
+
|
||||
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
+ if (!phy) {
|
||||
+ dev_err(&pdev->dev, "unable to allocate memory for USB PHY\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
|
||||
+ if (!otg) {
|
||||
+ dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ phy->dev = dev;
|
||||
+ phy->label = dev_name(dev);
|
||||
+ phy->init = usb_power_on;
|
||||
+ phy->shutdown = usb_power_off;
|
||||
+ otg->set_host = usb_set_host;
|
||||
+ otg->set_peripheral = usb_set_peripheral;
|
||||
+ otg->phy = phy;
|
||||
+ phy->otg = otg;
|
||||
+ ret = usb_add_phy(phy, USB_PHY_TYPE_USB2);
|
||||
+
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(dev, "usb phy addition error\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ platform_set_drvdata(pdev, phy);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "loaded\n");
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int usb_phy_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct usb_phy *phy = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ usb_remove_phy(phy);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver usb_phy_driver = {
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = "rt3xxx-usbphy",
|
||||
+ .of_match_table = of_match_ptr(ralink_usbphy_dt_match),
|
||||
+ },
|
||||
+ .probe = usb_phy_probe,
|
||||
+ .remove = usb_phy_remove,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(usb_phy_driver);
|
||||
+
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_DESCRIPTION("Ralink USB phy");
|
||||
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
|
|
@ -1,234 +0,0 @@
|
|||
From 9a15efea2e55327cf7c813da64589509f9c40786 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 16 May 2013 23:11:45 +0200
|
||||
Subject: [PATCH 161/164] USB: add OHCI/EHCI OF binding
|
||||
|
||||
based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 2 ++
|
||||
drivers/usb/Makefile | 3 ++-
|
||||
drivers/usb/host/ehci-platform.c | 44 ++++++++++++++++++++++++++++++++------
|
||||
drivers/usb/host/ohci-platform.c | 37 +++++++++++++++++++++++++++-----
|
||||
4 files changed, 74 insertions(+), 12 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -27,6 +27,8 @@ choice
|
||||
bool "MT7620"
|
||||
select CLKEVT_RT3352
|
||||
select HW_HAS_PCI
|
||||
+ select USB_ARCH_HAS_OHCI
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
|
||||
endchoice
|
||||
|
||||
--- a/drivers/usb/Makefile
|
||||
+++ b/drivers/usb/Makefile
|
||||
@@ -12,6 +12,8 @@ obj-$(CONFIG_USB_DWC3) += dwc3/
|
||||
|
||||
obj-$(CONFIG_USB_MON) += mon/
|
||||
|
||||
+obj-$(CONFIG_USB_OTG_UTILS) += phy/
|
||||
+
|
||||
obj-$(CONFIG_PCI) += host/
|
||||
obj-$(CONFIG_USB_EHCI_HCD) += host/
|
||||
obj-$(CONFIG_USB_ISP116X_HCD) += host/
|
||||
@@ -46,7 +48,6 @@ obj-$(CONFIG_USB_MICROTEK) += image/
|
||||
obj-$(CONFIG_USB_SERIAL) += serial/
|
||||
|
||||
obj-$(CONFIG_USB) += misc/
|
||||
-obj-$(CONFIG_USB_OTG_UTILS) += phy/
|
||||
obj-$(CONFIG_EARLY_PRINTK_DBGP) += early/
|
||||
|
||||
obj-$(CONFIG_USB_ATM) += atm/
|
||||
--- a/drivers/usb/host/ehci-platform.c
|
||||
+++ b/drivers/usb/host/ehci-platform.c
|
||||
@@ -18,14 +18,18 @@
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
+#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/hrtimer.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb.h>
|
||||
#include <linux/usb/hcd.h>
|
||||
+#include <linux/usb/otg.h>
|
||||
+#include <linux/usb/phy.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
|
||||
#include "ehci.h"
|
||||
@@ -63,22 +67,32 @@ static const struct ehci_driver_override
|
||||
.reset = ehci_platform_reset,
|
||||
};
|
||||
|
||||
+static struct usb_ehci_pdata ehci_platform_defaults;
|
||||
+
|
||||
static int ehci_platform_probe(struct platform_device *dev)
|
||||
{
|
||||
struct usb_hcd *hcd;
|
||||
struct resource *res_mem;
|
||||
- struct usb_ehci_pdata *pdata = dev->dev.platform_data;
|
||||
+ struct usb_ehci_pdata *pdata;
|
||||
int irq;
|
||||
int err = -ENOMEM;
|
||||
|
||||
- if (!pdata) {
|
||||
- WARN_ON(1);
|
||||
- return -ENODEV;
|
||||
- }
|
||||
-
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
+ /*
|
||||
+ * use reasonable defaults so platforms don't have to provide these.
|
||||
+ * with DT probing on ARM, none of these are set.
|
||||
+ */
|
||||
+ if (!dev->dev.platform_data)
|
||||
+ dev->dev.platform_data = &ehci_platform_defaults;
|
||||
+ if (!dev->dev.dma_mask)
|
||||
+ dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
|
||||
+ if (!dev->dev.coherent_dma_mask)
|
||||
+ dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
+
|
||||
+ pdata = dev->dev.platform_data;
|
||||
+
|
||||
irq = platform_get_irq(dev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&dev->dev, "no irq provided");
|
||||
@@ -106,6 +120,15 @@ static int ehci_platform_probe(struct pl
|
||||
hcd->rsrc_start = res_mem->start;
|
||||
hcd->rsrc_len = resource_size(res_mem);
|
||||
|
||||
+#ifdef CONFIG_USB_OTG_UTILS
|
||||
+ hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
|
||||
+ if (!IS_ERR_OR_NULL(hcd->phy)) {
|
||||
+ otg_set_host(hcd->phy->otg,
|
||||
+ &hcd->self);
|
||||
+ usb_phy_init(hcd->phy);
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
|
||||
if (IS_ERR(hcd->regs)) {
|
||||
err = PTR_ERR(hcd->regs);
|
||||
@@ -140,6 +163,9 @@ static int ehci_platform_remove(struct p
|
||||
if (pdata->power_off)
|
||||
pdata->power_off(dev);
|
||||
|
||||
+ if (pdata == &ehci_platform_defaults)
|
||||
+ dev->dev.platform_data = NULL;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -184,6 +210,11 @@ static int ehci_platform_resume(struct d
|
||||
#define ehci_platform_resume NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
+static const struct of_device_id ralink_ehci_ids[] = {
|
||||
+ { .compatible = "ralink,rt3xxx-ehci", },
|
||||
+ {}
|
||||
+};
|
||||
+
|
||||
static const struct platform_device_id ehci_platform_table[] = {
|
||||
{ "ehci-platform", 0 },
|
||||
{ }
|
||||
@@ -204,6 +235,7 @@ static struct platform_driver ehci_platf
|
||||
.owner = THIS_MODULE,
|
||||
.name = "ehci-platform",
|
||||
.pm = &ehci_platform_pm_ops,
|
||||
+ .of_match_table = of_match_ptr(ralink_ehci_ids),
|
||||
}
|
||||
};
|
||||
|
||||
--- a/drivers/usb/host/ohci-platform.c
|
||||
+++ b/drivers/usb/host/ohci-platform.c
|
||||
@@ -16,6 +16,10 @@
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/of.h>
|
||||
+
|
||||
+static struct usb_ohci_pdata ohci_platform_defaults;
|
||||
|
||||
static int ohci_platform_reset(struct usb_hcd *hcd)
|
||||
{
|
||||
@@ -88,14 +92,22 @@ static int ohci_platform_probe(struct pl
|
||||
{
|
||||
struct usb_hcd *hcd;
|
||||
struct resource *res_mem;
|
||||
- struct usb_ohci_pdata *pdata = dev->dev.platform_data;
|
||||
+ struct usb_ohci_pdata *pdata;
|
||||
int irq;
|
||||
int err = -ENOMEM;
|
||||
|
||||
- if (!pdata) {
|
||||
- WARN_ON(1);
|
||||
- return -ENODEV;
|
||||
- }
|
||||
+ /*
|
||||
+ * use reasonable defaults so platforms don't have to provide these.
|
||||
+ * with DT probing on ARM, none of these are set.
|
||||
+ */
|
||||
+ if (!dev->dev.platform_data)
|
||||
+ dev->dev.platform_data = &ohci_platform_defaults;
|
||||
+ if (!dev->dev.dma_mask)
|
||||
+ dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
|
||||
+ if (!dev->dev.coherent_dma_mask)
|
||||
+ dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
+
|
||||
+ pdata = dev->dev.platform_data;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
@@ -128,6 +140,12 @@ static int ohci_platform_probe(struct pl
|
||||
hcd->rsrc_start = res_mem->start;
|
||||
hcd->rsrc_len = resource_size(res_mem);
|
||||
|
||||
+#ifdef CONFIG_USB_OTG_UTILS
|
||||
+ hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
|
||||
+ if (!IS_ERR_OR_NULL(hcd->phy))
|
||||
+ usb_phy_init(hcd->phy);
|
||||
+#endif
|
||||
+
|
||||
hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
|
||||
if (IS_ERR(hcd->regs)) {
|
||||
err = PTR_ERR(hcd->regs);
|
||||
@@ -162,6 +180,9 @@ static int ohci_platform_remove(struct p
|
||||
if (pdata->power_off)
|
||||
pdata->power_off(dev);
|
||||
|
||||
+ if (pdata == &ohci_platform_defaults)
|
||||
+ dev->dev.platform_data = NULL;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -201,6 +222,11 @@ static int ohci_platform_resume(struct d
|
||||
#define ohci_platform_resume NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
+static const struct of_device_id ralink_ohci_ids[] = {
|
||||
+ { .compatible = "ralink,rt3xxx-ohci", },
|
||||
+ {}
|
||||
+};
|
||||
+
|
||||
static const struct platform_device_id ohci_platform_table[] = {
|
||||
{ "ohci-platform", 0 },
|
||||
{ }
|
||||
@@ -221,5 +247,6 @@ static struct platform_driver ohci_platf
|
||||
.owner = THIS_MODULE,
|
||||
.name = "ohci-platform",
|
||||
.pm = &ohci_platform_pm_ops,
|
||||
+ .of_match_table = of_match_ptr(ralink_ohci_ids),
|
||||
}
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,41 +0,0 @@
|
|||
From 7bb04eed36ee0b2f3148fc33db7f75d9b4c8548c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 24 May 2013 21:28:08 +0200
|
||||
Subject: [PATCH 163/164] USB: MIPS: ralink: fix usb issue on mt7620
|
||||
|
||||
USB fails when frequency scaling is enabled. Increase the idle cpu speed when
|
||||
scaled.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
|
||||
arch/mips/ralink/mt7620.c | 8 ++++++++
|
||||
2 files changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -20,6 +20,7 @@
|
||||
#define SYSC_REG_CHIP_REV 0x0c
|
||||
#define SYSC_REG_SYSTEM_CONFIG0 0x10
|
||||
#define SYSC_REG_SYSTEM_CONFIG1 0x14
|
||||
+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
|
||||
#define SYSC_REG_CPLL_CONFIG0 0x54
|
||||
#define SYSC_REG_CPLL_CONFIG1 0x58
|
||||
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -186,6 +186,14 @@ void __init ralink_clk_init(void)
|
||||
ralink_clk_add("10000500.uart", 40000000);
|
||||
ralink_clk_add("10000b00.spi", 40000000);
|
||||
ralink_clk_add("10000c00.uartlite", 40000000);
|
||||
+
|
||||
+#ifdef CONFIG_USB
|
||||
+ /*
|
||||
+ * When the CPU goes into sleep mode, the BUS clock will be too low for
|
||||
+ * USB to function properly
|
||||
+ */
|
||||
+ rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG);
|
||||
+#endif
|
||||
}
|
||||
|
||||
void __init ralink_of_remap(void)
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
From 3630032605c18986555263eccc08b929e4c6d473 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 17 May 2013 01:03:45 +0200
|
||||
Subject: [PATCH 164/164] Kbuild: add missing space
|
||||
|
||||
Currently the output looks like this:
|
||||
DTC arch/mips/ralink/dts/mt7620a_eval.dtb
|
||||
DTB arch/mips/ralink/dts/mt7620a_eval.dtb.S
|
||||
AS arch/mips/ralink/dts/mt7620a_eval.dtb.o
|
||||
|
||||
Whitespace error was introduced by initial commit
|
||||
commit aab94339cd85d726abeae78fc02351fc1910e6a4
|
||||
Author: Dirk Brandewie <dirk.brandewie@gmail.com>
|
||||
Date: Wed Dec 22 11:57:26 2010 -0800
|
||||
|
||||
of: Add support for linking device tree blobs into vmlinux
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
scripts/Makefile.lib | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -251,7 +251,7 @@ cmd_gzip = (cat $(filter-out FORCE,$^) |
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
# Generate an assembly file to wrap the output of the device tree compiler
|
||||
-quiet_cmd_dt_S_dtb= DTB $@
|
||||
+quiet_cmd_dt_S_dtb= DTB $@
|
||||
cmd_dt_S_dtb= \
|
||||
( \
|
||||
echo '\#include <asm-generic/vmlinux.lds.h>'; \
|
||||
|
|
@ -1,325 +0,0 @@
|
|||
From 7d8a8b0e46a970fba505d967e93123e9729d97b5 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 23 Jun 2013 00:16:22 +0200
|
||||
Subject: [PATCH] owrt: GPIO: add gpio_export_with_name
|
||||
|
||||
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-November/133856.html
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
Documentation/devicetree/bindings/gpio/gpio.txt | 60 ++++++++++++++++++++
|
||||
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++
|
||||
drivers/gpio/gpiolib.c | 24 +++++---
|
||||
include/asm-generic/gpio.h | 6 +-
|
||||
include/linux/gpio.h | 26 ++++++++-
|
||||
5 files changed, 172 insertions(+), 12 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
@@ -112,3 +112,63 @@ where,
|
||||
|
||||
The pinctrl node must have "#gpio-range-cells" property to show number of
|
||||
arguments to pass with phandle from gpio controllers node.
|
||||
+
|
||||
+3) gpio-export
|
||||
+--------------
|
||||
+
|
||||
+gpio-export will allow you to automatically export gpio
|
||||
+
|
||||
+required properties:
|
||||
+- compatible: Should be "gpio-export"
|
||||
+
|
||||
+in each child node will reprensent a gpio or if no name is specified
|
||||
+a list of gpio to export
|
||||
+
|
||||
+required properties:
|
||||
+- gpios: gpio to export
|
||||
+
|
||||
+optional properties:
|
||||
+ - gpio-export,name: export name
|
||||
+ - gpio-export,output: to set the as output with default value
|
||||
+ if no present gpio as input
|
||||
+ - pio-export,direction_may_change: boolean to allow the direction to be controllable
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+
|
||||
+gpio_export {
|
||||
+ compatible = "gpio-export";
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ in {
|
||||
+ gpio-export,name = "in";
|
||||
+ gpios = <&pioC 20 0>;
|
||||
+ };
|
||||
+
|
||||
+ out {
|
||||
+ gpio-export,name = "out";
|
||||
+ gpio-export,output = <1>;
|
||||
+ gpio-export,direction_may_change;
|
||||
+ gpios = <&pioC 21 0>;
|
||||
+ };
|
||||
+
|
||||
+ in_out {
|
||||
+ gpio-export,name = "in_out";
|
||||
+ gpio-export,direction_may_change;
|
||||
+ gpios = <&pioC 21 0>;
|
||||
+ };
|
||||
+
|
||||
+ gpios_in {
|
||||
+ gpios = <&pioB 0 0
|
||||
+ &pioB 3 0
|
||||
+ &pioC 4 0>;
|
||||
+ gpio-export,direction_may_change;
|
||||
+ };
|
||||
+
|
||||
+ gpios_out {
|
||||
+ gpios = <&pioB 1 0
|
||||
+ &pioB 2 0
|
||||
+ &pioC 3 0>;
|
||||
+ gpio-export,output = <1>;
|
||||
+ };
|
||||
+};
|
||||
--- a/drivers/gpio/gpiolib-of.c
|
||||
+++ b/drivers/gpio/gpiolib-of.c
|
||||
@@ -21,6 +21,8 @@
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/slab.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
/* Private data structure for of_gpiochip_find_and_xlate */
|
||||
struct gg_data {
|
||||
@@ -253,3 +255,69 @@ void of_gpiochip_remove(struct gpio_chip
|
||||
if (chip->of_node)
|
||||
of_node_put(chip->of_node);
|
||||
}
|
||||
+
|
||||
+static struct of_device_id gpio_export_ids[] = {
|
||||
+ { .compatible = "gpio-export" },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
+static int __init of_gpio_export_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct device_node *cnp;
|
||||
+ u32 val;
|
||||
+ int nb = 0;
|
||||
+
|
||||
+ for_each_child_of_node(np, cnp) {
|
||||
+ const char *name = NULL;
|
||||
+ int gpio;
|
||||
+ bool dmc;
|
||||
+ int max_gpio = 1;
|
||||
+ int i;
|
||||
+
|
||||
+ of_property_read_string(cnp, "gpio-export,name", &name);
|
||||
+
|
||||
+ if (!name)
|
||||
+ max_gpio = of_gpio_count(cnp);
|
||||
+
|
||||
+ for (i = 0; i < max_gpio; i++) {
|
||||
+ unsigned flags = 0;
|
||||
+ enum of_gpio_flags of_flags;
|
||||
+
|
||||
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
|
||||
+
|
||||
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
|
||||
+ flags |= GPIOF_ACTIVE_LOW;
|
||||
+
|
||||
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
|
||||
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
|
||||
+ else
|
||||
+ flags |= GPIOF_IN;
|
||||
+
|
||||
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
|
||||
+ continue;
|
||||
+
|
||||
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
|
||||
+ gpio_export_with_name(gpio, dmc, name);
|
||||
+ nb++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver gpio_export_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "gpio-export",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = of_match_ptr(gpio_export_ids),
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init of_gpio_export_init(void)
|
||||
+{
|
||||
+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
|
||||
+}
|
||||
+device_initcall(of_gpio_export_init);
|
||||
--- a/drivers/gpio/gpiolib.c
|
||||
+++ b/drivers/gpio/gpiolib.c
|
||||
@@ -96,7 +96,7 @@ static int gpiod_get_value(const struct
|
||||
static void gpiod_set_value(struct gpio_desc *desc, int value);
|
||||
static int gpiod_cansleep(const struct gpio_desc *desc);
|
||||
static int gpiod_to_irq(const struct gpio_desc *desc);
|
||||
-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
|
||||
+static int gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
|
||||
static int gpiod_export_link(struct device *dev, const char *name,
|
||||
struct gpio_desc *desc);
|
||||
static int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
|
||||
@@ -674,7 +674,7 @@ static ssize_t export_store(struct class
|
||||
status = -ENODEV;
|
||||
goto done;
|
||||
}
|
||||
- status = gpiod_export(desc, true);
|
||||
+ status = gpiod_export(desc, true, NULL);
|
||||
if (status < 0)
|
||||
gpiod_free(desc);
|
||||
else
|
||||
@@ -736,9 +736,10 @@ static struct class gpio_class = {
|
||||
|
||||
|
||||
/**
|
||||
- * gpio_export - export a GPIO through sysfs
|
||||
+ * gpio_export_with_name - export a GPIO through sysfs
|
||||
* @gpio: gpio to make available, already requested
|
||||
* @direction_may_change: true if userspace may change gpio direction
|
||||
+ * @name: gpio name
|
||||
* Context: arch_initcall or later
|
||||
*
|
||||
* When drivers want to make a GPIO accessible to userspace after they
|
||||
@@ -750,7 +751,7 @@ static struct class gpio_class = {
|
||||
*
|
||||
* Returns zero on success, else an error.
|
||||
*/
|
||||
-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
|
||||
+static int gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
|
||||
{
|
||||
unsigned long flags;
|
||||
int status;
|
||||
@@ -783,6 +784,8 @@ static int gpiod_export(struct gpio_desc
|
||||
goto fail_unlock;
|
||||
}
|
||||
|
||||
+ if (name)
|
||||
+ ioname = name;
|
||||
if (!desc->chip->direction_input || !desc->chip->direction_output)
|
||||
direction_may_change = false;
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
@@ -829,11 +832,11 @@ fail_unlock:
|
||||
return status;
|
||||
}
|
||||
|
||||
-int gpio_export(unsigned gpio, bool direction_may_change)
|
||||
+int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
|
||||
{
|
||||
- return gpiod_export(gpio_to_desc(gpio), direction_may_change);
|
||||
+ return gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
|
||||
}
|
||||
-EXPORT_SYMBOL_GPL(gpio_export);
|
||||
+EXPORT_SYMBOL_GPL(gpio_export_with_name);
|
||||
|
||||
static int match_export(struct device *dev, const void *data)
|
||||
{
|
||||
@@ -1092,7 +1095,7 @@ static inline void gpiochip_unexport(str
|
||||
}
|
||||
|
||||
static inline int gpiod_export(struct gpio_desc *desc,
|
||||
- bool direction_may_change)
|
||||
+ bool direction_may_change, const char *name)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
@@ -1521,6 +1524,9 @@ int gpio_request_one(unsigned gpio, unsi
|
||||
if (flags & GPIOF_OPEN_SOURCE)
|
||||
set_bit(FLAG_OPEN_SOURCE, &desc->flags);
|
||||
|
||||
+ if (flags & GPIOF_ACTIVE_LOW)
|
||||
+ set_bit(FLAG_ACTIVE_LOW, &gpio_desc[gpio].flags);
|
||||
+
|
||||
if (flags & GPIOF_DIR_IN)
|
||||
err = gpiod_direction_input(desc);
|
||||
else
|
||||
@@ -1531,7 +1537,7 @@ int gpio_request_one(unsigned gpio, unsi
|
||||
goto free_gpio;
|
||||
|
||||
if (flags & GPIOF_EXPORT) {
|
||||
- err = gpiod_export(desc, flags & GPIOF_EXPORT_CHANGEABLE);
|
||||
+ err = gpiod_export(desc, flags & GPIOF_EXPORT_CHANGEABLE, NULL);
|
||||
if (err)
|
||||
goto free_gpio;
|
||||
}
|
||||
--- a/include/asm-generic/gpio.h
|
||||
+++ b/include/asm-generic/gpio.h
|
||||
@@ -202,7 +202,8 @@ extern void gpio_free_array(const struct
|
||||
* A sysfs interface can be exported by individual drivers if they want,
|
||||
* but more typically is configured entirely from userspace.
|
||||
*/
|
||||
-extern int gpio_export(unsigned gpio, bool direction_may_change);
|
||||
+extern int gpio_export_with_name(unsigned gpio, bool direction_may_change,
|
||||
+ const char *name);
|
||||
extern int gpio_export_link(struct device *dev, const char *name,
|
||||
unsigned gpio);
|
||||
extern int gpio_sysfs_set_active_low(unsigned gpio, int value);
|
||||
@@ -284,7 +285,8 @@ struct device;
|
||||
|
||||
/* sysfs support is only available with gpiolib, where it's optional */
|
||||
|
||||
-static inline int gpio_export(unsigned gpio, bool direction_may_change)
|
||||
+static inline int gpio_export_with_name(unsigned gpio,
|
||||
+ bool direction_may_change, const char *name)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
--- a/include/linux/gpio.h
|
||||
+++ b/include/linux/gpio.h
|
||||
@@ -27,6 +27,9 @@
|
||||
#define GPIOF_EXPORT_DIR_FIXED (GPIOF_EXPORT)
|
||||
#define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
|
||||
|
||||
+#define GPIOF_ACTIVE_LOW (1 << 6)
|
||||
+
|
||||
+
|
||||
/**
|
||||
* struct gpio - a structure describing a GPIO with configuration
|
||||
* @gpio: the GPIO number
|
||||
@@ -169,7 +172,8 @@ static inline void gpio_set_value_cansle
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
-static inline int gpio_export(unsigned gpio, bool direction_may_change)
|
||||
+static inline int gpio_export_with_name(unsigned gpio,
|
||||
+ bool direction_may_change, const char *name)
|
||||
{
|
||||
/* GPIO can never have been requested or set as {in,out}put */
|
||||
WARN_ON(1);
|
||||
@@ -236,4 +240,24 @@ int devm_gpio_request_one(struct device
|
||||
unsigned long flags, const char *label);
|
||||
void devm_gpio_free(struct device *dev, unsigned int gpio);
|
||||
|
||||
+/**
|
||||
+ * gpio_export - export a GPIO through sysfs
|
||||
+ * @gpio: gpio to make available, already requested
|
||||
+ * @direction_may_change: true if userspace may change gpio direction
|
||||
+ * Context: arch_initcall or later
|
||||
+ *
|
||||
+ * When drivers want to make a GPIO accessible to userspace after they
|
||||
+ * have requested it -- perhaps while debugging, or as part of their
|
||||
+ * public interface -- they may use this routine. If the GPIO can
|
||||
+ * change direction (some can't) and the caller allows it, userspace
|
||||
+ * will see "direction" sysfs attribute which may be used to change
|
||||
+ * the gpio's direction. A "value" attribute will always be provided.
|
||||
+ *
|
||||
+ * Returns zero on success, else an error.
|
||||
+ */
|
||||
+static inline int gpio_export(unsigned gpio,bool direction_may_change)
|
||||
+{
|
||||
+ return gpio_export_with_name(gpio, direction_may_change, NULL);
|
||||
+}
|
||||
+
|
||||
#endif /* __LINUX_GPIO_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,52 +0,0 @@
|
|||
From 6beb1af1b1475478c8f275b9579c9ebe4dad2904 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 19 Mar 2013 10:16:42 +0100
|
||||
Subject: [PATCH 205/208] owrt: MIPS: add OWRTDTB secion
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/kernel/head.S | 3 +++
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/of.c | 4 +++-
|
||||
3 files changed, 7 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/kernel/head.S
|
||||
+++ b/arch/mips/kernel/head.S
|
||||
@@ -146,6 +146,9 @@ EXPORT(__image_cmdline)
|
||||
.fill 0x400
|
||||
#endif /* CONFIG_IMAGE_CMDLINE_HACK */
|
||||
|
||||
+ .ascii "OWRTDTB:"
|
||||
+ EXPORT(__image_dtb)
|
||||
+ .fill 0x4000
|
||||
__REF
|
||||
|
||||
NESTED(kernel_entry, 16, sp) # kernel entry point
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -17,4 +17,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
|
||||
|
||||
obj-$(CONFIG_DEBUG_FS) += bootrom.o
|
||||
|
||||
-obj-y += dts/
|
||||
+#obj-y += dts/
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -83,6 +83,8 @@ void __init device_tree_init(void)
|
||||
//free_bootmem(base, size);
|
||||
}
|
||||
|
||||
+extern struct boot_param_header __image_dtb;
|
||||
+
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
set_io_port_base(KSEG1);
|
||||
@@ -91,7 +93,7 @@ void __init plat_mem_setup(void)
|
||||
* Load the builtin devicetree. This causes the chosen node to be
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
- __dt_setup_arch(&__dtb_start);
|
||||
+ __dt_setup_arch(&__image_dtb);
|
||||
|
||||
if (soc_info.mem_size)
|
||||
add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
|
||||
|
|
@ -1,301 +0,0 @@
|
|||
From b35a0a294d39316c20f85004335c02f33a70ab68 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 24 Mar 2013 17:17:17 +0100
|
||||
Subject: [PATCH 206/208] owrt: MIPS: ralink: add pseudo pwm led trigger based
|
||||
on timer0
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/timer.c | 213 ++++++++++++++++++++++++++++++++++++++++++----
|
||||
1 file changed, 197 insertions(+), 16 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/timer.c
|
||||
+++ b/arch/mips/ralink/timer.c
|
||||
@@ -12,6 +12,8 @@
|
||||
#include <linux/timer.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/clk.h>
|
||||
+#include <linux/leds.h>
|
||||
+#include <linux/slab.h>
|
||||
|
||||
#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
@@ -23,16 +25,34 @@
|
||||
|
||||
#define TMR0CTL_ENABLE BIT(7)
|
||||
#define TMR0CTL_MODE_PERIODIC BIT(4)
|
||||
-#define TMR0CTL_PRESCALER 1
|
||||
+#define TMR0CTL_PRESCALER 2
|
||||
#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
|
||||
#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
|
||||
|
||||
+struct rt_timer_gpio {
|
||||
+ struct list_head list;
|
||||
+ struct led_classdev *led;
|
||||
+};
|
||||
+
|
||||
struct rt_timer {
|
||||
- struct device *dev;
|
||||
- void __iomem *membase;
|
||||
- int irq;
|
||||
- unsigned long timer_freq;
|
||||
- unsigned long timer_div;
|
||||
+ struct device *dev;
|
||||
+ void __iomem *membase;
|
||||
+ int irq;
|
||||
+
|
||||
+ unsigned long timer_freq;
|
||||
+ unsigned long timer_div;
|
||||
+
|
||||
+ struct list_head gpios;
|
||||
+ struct led_trigger led_trigger;
|
||||
+ unsigned int duty_cycle;
|
||||
+ unsigned int duty;
|
||||
+
|
||||
+ unsigned int fade;
|
||||
+ unsigned int fade_min;
|
||||
+ unsigned int fade_max;
|
||||
+ unsigned int fade_speed;
|
||||
+ unsigned int fade_dir;
|
||||
+ unsigned int fade_count;
|
||||
};
|
||||
|
||||
static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
|
||||
@@ -48,18 +68,46 @@ static inline u32 rt_timer_r32(struct rt
|
||||
static irqreturn_t rt_timer_irq(int irq, void *_rt)
|
||||
{
|
||||
struct rt_timer *rt = (struct rt_timer *) _rt;
|
||||
+ struct rt_timer_gpio *gpio;
|
||||
+ unsigned int val;
|
||||
|
||||
- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
|
||||
+ if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
|
||||
+ rt->fade_count = 0;
|
||||
+ if (rt->duty_cycle <= rt->fade_min)
|
||||
+ rt->fade_dir = 1;
|
||||
+ else if (rt->duty_cycle >= rt->fade_max)
|
||||
+ rt->fade_dir = 0;
|
||||
+
|
||||
+ if (rt->fade_dir)
|
||||
+ rt->duty_cycle += 1;
|
||||
+ else
|
||||
+ rt->duty_cycle -= 1;
|
||||
+
|
||||
+ }
|
||||
+
|
||||
+ val = rt->timer_freq / rt->timer_div;
|
||||
+ if (rt->duty)
|
||||
+ val *= rt->duty_cycle;
|
||||
+ else
|
||||
+ val *= (100 - rt->duty_cycle);
|
||||
+ val /= 100;
|
||||
+
|
||||
+ if (!list_empty(&rt->gpios))
|
||||
+ list_for_each_entry(gpio, &rt->gpios, list)
|
||||
+ led_set_brightness(gpio->led, !!rt->duty);
|
||||
+
|
||||
+ rt->duty = !rt->duty;
|
||||
+
|
||||
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
|
||||
rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
-
|
||||
static int rt_timer_request(struct rt_timer *rt)
|
||||
{
|
||||
- int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
|
||||
- dev_name(rt->dev), rt);
|
||||
+ int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
|
||||
+ IRQF_DISABLED, dev_name(rt->dev), rt);
|
||||
if (err) {
|
||||
dev_err(rt->dev, "failed to request irq\n");
|
||||
} else {
|
||||
@@ -81,8 +129,6 @@ static int rt_timer_config(struct rt_tim
|
||||
else
|
||||
rt->timer_div = divisor;
|
||||
|
||||
- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
|
||||
-
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -108,11 +154,128 @@ static void rt_timer_disable(struct rt_t
|
||||
rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
|
||||
}
|
||||
|
||||
+static ssize_t led_fade_show(struct device *dev,
|
||||
+ struct device_attribute *attr, char *buf)
|
||||
+{
|
||||
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+
|
||||
+ return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
|
||||
+}
|
||||
+
|
||||
+static ssize_t led_fade_store(struct device *dev,
|
||||
+ struct device_attribute *attr, const char *buf, size_t size)
|
||||
+{
|
||||
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+ unsigned int speed = 0, min = 0, max = 0;
|
||||
+ ssize_t ret = -EINVAL;
|
||||
+
|
||||
+ ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
|
||||
+
|
||||
+ if (ret == 3) {
|
||||
+ rt->fade_speed = speed;
|
||||
+ rt->fade_min = min;
|
||||
+ rt->fade_max = max;
|
||||
+ rt->fade = 1;
|
||||
+ } else {
|
||||
+ rt->fade = 0;
|
||||
+ }
|
||||
+
|
||||
+ return size;
|
||||
+}
|
||||
+
|
||||
+static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
|
||||
+
|
||||
+static ssize_t led_duty_cycle_show(struct device *dev,
|
||||
+ struct device_attribute *attr, char *buf)
|
||||
+{
|
||||
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+
|
||||
+ return sprintf(buf, "%u\n", rt->duty_cycle);
|
||||
+}
|
||||
+
|
||||
+static ssize_t led_duty_cycle_store(struct device *dev,
|
||||
+ struct device_attribute *attr, const char *buf, size_t size)
|
||||
+{
|
||||
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+ unsigned long state;
|
||||
+ ssize_t ret = -EINVAL;
|
||||
+
|
||||
+ ret = kstrtoul(buf, 10, &state);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (state <= 100)
|
||||
+ rt->duty_cycle = state;
|
||||
+ else
|
||||
+ rt->duty_cycle = 100;
|
||||
+
|
||||
+ rt->fade = 0;
|
||||
+
|
||||
+ return size;
|
||||
+}
|
||||
+
|
||||
+static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
|
||||
+
|
||||
+static void rt_timer_trig_activate(struct led_classdev *led_cdev)
|
||||
+{
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+ struct rt_timer_gpio *gpio_data;
|
||||
+ int rc;
|
||||
+
|
||||
+ led_cdev->trigger_data = NULL;
|
||||
+ gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
|
||||
+ if (!gpio_data)
|
||||
+ return;
|
||||
+
|
||||
+ rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
|
||||
+ if (rc)
|
||||
+ goto err_gpio;
|
||||
+ rc = device_create_file(led_cdev->dev, &dev_attr_fade);
|
||||
+ if (rc)
|
||||
+ goto err_out_duty_cycle;
|
||||
+
|
||||
+ led_cdev->activated = true;
|
||||
+ led_cdev->trigger_data = gpio_data;
|
||||
+ gpio_data->led = led_cdev;
|
||||
+ list_add(&gpio_data->list, &rt->gpios);
|
||||
+ led_cdev->trigger_data = gpio_data;
|
||||
+ rt_timer_enable(rt);
|
||||
+ return;
|
||||
+
|
||||
+err_out_duty_cycle:
|
||||
+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
|
||||
+
|
||||
+err_gpio:
|
||||
+ kfree(gpio_data);
|
||||
+}
|
||||
+
|
||||
+static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
|
||||
+{
|
||||
+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
|
||||
+ struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
|
||||
+
|
||||
+ if (led_cdev->activated) {
|
||||
+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
|
||||
+ device_remove_file(led_cdev->dev, &dev_attr_fade);
|
||||
+ led_cdev->activated = false;
|
||||
+ }
|
||||
+
|
||||
+ list_del(&gpio_data->list);
|
||||
+ rt_timer_disable(rt);
|
||||
+ led_set_brightness(led_cdev, LED_OFF);
|
||||
+}
|
||||
+
|
||||
static int rt_timer_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ const __be32 *divisor;
|
||||
struct rt_timer *rt;
|
||||
struct clk *clk;
|
||||
+ int ret;
|
||||
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "no memory resource found\n");
|
||||
@@ -147,12 +310,29 @@ static int rt_timer_probe(struct platfor
|
||||
if (!rt->timer_freq)
|
||||
return -EINVAL;
|
||||
|
||||
+ rt->duty_cycle = 100;
|
||||
rt->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, rt);
|
||||
|
||||
- rt_timer_request(rt);
|
||||
- rt_timer_config(rt, 2);
|
||||
- rt_timer_enable(rt);
|
||||
+ ret = rt_timer_request(rt);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
|
||||
+ if (divisor)
|
||||
+ rt_timer_config(rt, be32_to_cpu(*divisor));
|
||||
+ else
|
||||
+ rt_timer_config(rt, 200);
|
||||
+
|
||||
+ rt->led_trigger.name = "pwmtimer",
|
||||
+ rt->led_trigger.activate = rt_timer_trig_activate,
|
||||
+ rt->led_trigger.deactivate = rt_timer_trig_deactivate,
|
||||
+
|
||||
+ ret = led_trigger_register(&rt->led_trigger);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ INIT_LIST_HEAD(&rt->gpios);
|
||||
|
||||
dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
|
||||
|
||||
@@ -163,6 +343,7 @@ static int rt_timer_remove(struct platfo
|
||||
{
|
||||
struct rt_timer *rt = platform_get_drvdata(pdev);
|
||||
|
||||
+ led_trigger_unregister(&rt->led_trigger);
|
||||
rt_timer_disable(rt);
|
||||
rt_timer_free(rt);
|
||||
|
||||
@@ -187,6 +368,6 @@ static struct platform_driver rt_timer_d
|
||||
|
||||
module_platform_driver(rt_timer_driver);
|
||||
|
||||
-MODULE_DESCRIPTION("Ralink RT2880 timer");
|
||||
+MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
|
||||
MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
From 2a295753a10823a47542c779a25bbb1f52c71281 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 3 Aug 2012 10:27:13 +0200
|
||||
Subject: [PATCH 19/25] owrt mtd split
|
||||
|
||||
---
|
||||
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 +
|
||||
arch/mips/lantiq/setup.c | 7 +
|
||||
drivers/mtd/Kconfig | 4 +
|
||||
drivers/mtd/mtdpart.c | 173 +++++++++++++++++++-
|
||||
4 files changed, 184 insertions(+), 1 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/Kconfig
|
||||
+++ b/drivers/mtd/Kconfig
|
||||
@@ -31,6 +31,10 @@ config MTD_ROOTFS_SPLIT
|
||||
bool "Automatically split 'rootfs' partition for squashfs"
|
||||
default y
|
||||
|
||||
+config MTD_UIMAGE_SPLIT
|
||||
+ bool "Automatically split 'linux' partition into 'kernel' and 'rootfs'"
|
||||
+ default y
|
||||
+
|
||||
config MTD_REDBOOT_PARTS
|
||||
tristate "RedBoot partition table parsing"
|
||||
---help---
|
||||
--- a/drivers/mtd/mtdpart.c
|
||||
+++ b/drivers/mtd/mtdpart.c
|
||||
@@ -833,6 +833,99 @@ static int refresh_rootfs_split(struct m
|
||||
}
|
||||
#endif /* CONFIG_MTD_ROOTFS_SPLIT */
|
||||
|
||||
+#ifdef CONFIG_MTD_UIMAGE_SPLIT
|
||||
+static unsigned long find_uimage_size(struct mtd_info *mtd,
|
||||
+ unsigned long offset)
|
||||
+{
|
||||
+#define UBOOT_MAGIC 0x56190527
|
||||
+ unsigned long magic = 0;
|
||||
+ unsigned long temp;
|
||||
+ size_t len;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = mtd_read(mtd, offset, 4, &len, (void *)&magic);
|
||||
+ if (ret || len != sizeof(magic))
|
||||
+ return 0;
|
||||
+
|
||||
+ if (le32_to_cpu(magic) != UBOOT_MAGIC)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = mtd_read(mtd, offset + 12, 4, &len, (void *)&temp);
|
||||
+ if (ret || len != sizeof(temp))
|
||||
+ return 0;
|
||||
+
|
||||
+ return be32_to_cpu(temp) + 0x40;
|
||||
+}
|
||||
+
|
||||
+static int detect_squashfs_partition(struct mtd_info *mtd, unsigned long offset)
|
||||
+{
|
||||
+ unsigned long temp;
|
||||
+ size_t len;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = mtd_read(mtd, offset, 4, &len, (void *)&temp);
|
||||
+ if (ret || len != sizeof(temp))
|
||||
+ return 0;
|
||||
+
|
||||
+ return le32_to_cpu(temp) == SQUASHFS_MAGIC;
|
||||
+}
|
||||
+
|
||||
+static unsigned long find_squashfs_offset(struct mtd_info *mtd, unsigned long _offset)
|
||||
+{
|
||||
+ /* scan the first 2MB at 64K offsets */
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < 32; i++) {
|
||||
+ unsigned long offset = i * 64 * 1024;
|
||||
+ if (detect_squashfs_partition(mtd, _offset + offset))
|
||||
+ return offset;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int split_uimage(struct mtd_info *mtd,
|
||||
+ const struct mtd_partition *part)
|
||||
+{
|
||||
+ static struct mtd_partition split_partitions[] = {
|
||||
+ {
|
||||
+ .name = "kernel",
|
||||
+ .offset = 0x0,
|
||||
+ .size = 0x0,
|
||||
+ }, {
|
||||
+ .name = "rootfs",
|
||||
+ .offset = 0x0,
|
||||
+ .size = 0x0,
|
||||
+ },
|
||||
+ };
|
||||
+
|
||||
+ split_partitions[0].size = find_uimage_size(mtd, part->offset);
|
||||
+ if (!split_partitions[0].size) {
|
||||
+ split_partitions[0].size = find_squashfs_offset(mtd, part->offset);
|
||||
+ if (!split_partitions[0].size) {
|
||||
+ pr_err("failed to split firmware partition\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!detect_squashfs_partition(mtd,
|
||||
+ part->offset
|
||||
+ + split_partitions[0].size)) {
|
||||
+ split_partitions[0].size &= ~(mtd->erasesize - 1);
|
||||
+ split_partitions[0].size += mtd->erasesize;
|
||||
+ } else {
|
||||
+ pr_info("found squashfs behind kernel\n");
|
||||
+ }
|
||||
+
|
||||
+ split_partitions[0].offset = part->offset;
|
||||
+ split_partitions[1].offset = part->offset + split_partitions[0].size;
|
||||
+ split_partitions[1].size = part->size - split_partitions[0].size;
|
||||
+
|
||||
+ add_mtd_partitions(mtd, split_partitions, 2);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* This function, given a master MTD object and a partition table, creates
|
||||
* and registers slave MTD objects which are bound to the master according to
|
||||
@@ -849,7 +942,7 @@ int add_mtd_partitions(struct mtd_info *
|
||||
struct mtd_part *slave;
|
||||
uint64_t cur_offset = 0;
|
||||
int i;
|
||||
-#ifdef CONFIG_MTD_ROOTFS_SPLIT
|
||||
+#if defined(CONFIG_MTD_ROOTFS_SPLIT) || defined(CONFIG_MTD_UIMAGE_SPLIT)
|
||||
int ret;
|
||||
#endif
|
||||
|
||||
@@ -866,6 +959,14 @@ int add_mtd_partitions(struct mtd_info *
|
||||
|
||||
add_mtd_device(&slave->mtd);
|
||||
|
||||
+#ifdef CONFIG_MTD_UIMAGE_SPLIT
|
||||
+ if (!strcmp(parts[i].name, "firmware")) {
|
||||
+ ret = split_uimage(master, &parts[i]);
|
||||
+ if (ret)
|
||||
+ printk(KERN_WARNING "Can't split firmware partition\n");
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
if (!strcmp(parts[i].name, "rootfs")) {
|
||||
#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV
|
||||
if (ROOT_DEV == 0) {
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
@@ -1957,7 +1957,7 @@ static int __xipram do_erase_chip(struct
|
||||
chip->erase_suspended = 0;
|
||||
}
|
||||
|
||||
- if (chip_ready(map, adr))
|
||||
+ if (chip_good(map, adr, map_word_ff(map)))
|
||||
break;
|
||||
|
||||
if (time_after(jiffies, timeo)) {
|
||||
@@ -2046,7 +2046,7 @@ static int __xipram do_erase_oneblock(st
|
||||
chip->erase_suspended = 0;
|
||||
}
|
||||
|
||||
- if (chip_ready(map, adr)) {
|
||||
+ if (chip_good(map, adr, map_word_ff(map))) {
|
||||
xip_enable(map, chip, adr);
|
||||
break;
|
||||
}
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||
@@ -41,7 +41,7 @@
|
||||
#include <linux/mtd/xip.h>
|
||||
|
||||
#define AMD_BOOTLOC_BUG
|
||||
-#define FORCE_WORD_WRITE 0
|
||||
+#define FORCE_WORD_WRITE 1
|
||||
|
||||
#define MAX_WORD_RETRIES 3
|
||||
|
||||
@@ -52,7 +52,9 @@
|
||||
|
||||
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
|
||||
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||
+#endif
|
||||
static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
|
||||
static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
|
||||
static void cfi_amdstd_sync (struct mtd_info *);
|
||||
@@ -192,6 +194,7 @@ static void fixup_amd_bootblock(struct m
|
||||
}
|
||||
#endif
|
||||
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static void fixup_use_write_buffers(struct mtd_info *mtd)
|
||||
{
|
||||
struct map_info *map = mtd->priv;
|
||||
@@ -201,6 +204,7 @@ static void fixup_use_write_buffers(stru
|
||||
mtd->_write = cfi_amdstd_write_buffers;
|
||||
}
|
||||
}
|
||||
+#endif /* !FORCE_WORD_WRITE */
|
||||
|
||||
/* Atmel chips don't use the same PRI format as AMD chips */
|
||||
static void fixup_convert_atmel_pri(struct mtd_info *mtd)
|
||||
@@ -1461,6 +1465,7 @@ static int cfi_amdstd_write_words(struct
|
||||
/*
|
||||
* FIXME: interleaved mode not tested, and probably not supported!
|
||||
*/
|
||||
+#if !FORCE_WORD_WRITE
|
||||
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
|
||||
unsigned long adr, const u_char *buf,
|
||||
int len)
|
||||
@@ -1585,7 +1590,6 @@ static int __xipram do_write_buffer(stru
|
||||
return ret;
|
||||
}
|
||||
|
||||
-
|
||||
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
|
||||
size_t *retlen, const u_char *buf)
|
||||
{
|
||||
@@ -1660,6 +1664,7 @@ static int cfi_amdstd_write_buffers(stru
|
||||
|
||||
return 0;
|
||||
}
|
||||
+#endif /* !FORCE_WORD_WRITE */
|
||||
|
||||
/*
|
||||
* Wait for the flash chip to become ready to write data
|
||||
Loading…
Reference in New Issue