351 lines
8.4 KiB
C
351 lines
8.4 KiB
C
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/*
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* linux/arch/arm/mach-cns3xxx/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* Copyright 2012 Gateworks Corporation
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* Chris Lang <clang@gateworks.com>
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* Tim Harvey <tharvey@gateworks.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <asm/fiq.h>
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#include <mach/smp.h>
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#include <mach/cns3xxx.h>
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static struct fiq_handler fh = {
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.name = "cns3xxx-fiq"
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};
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static unsigned int fiq_buffer[8];
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#define FIQ_ENABLED 0x80000000
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#define FIQ_GENERATE 0x00010000
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#define CNS3XXX_MAP_AREA 0x01000000
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#define CNS3XXX_UNMAP_AREA 0x02000000
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#define CNS3XXX_FLUSH_RANGE 0x03000000
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extern void cns3xxx_secondary_startup(void);
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extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
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extern unsigned int fiq_number[2];
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extern struct cpu_cache_fns cpu_cache;
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struct cpu_cache_fns cpu_cache_save;
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#define SCU_CPU_STATUS 0x08
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static void __iomem *scu_base;
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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static void __init cns3xxx_set_fiq_regs(void)
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{
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struct pt_regs FIQ_regs;
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unsigned int cpu = smp_processor_id();
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if (cpu) {
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FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
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FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
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} else {
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FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
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FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
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}
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set_fiq_regs(&FIQ_regs);
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}
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static void __init cns3xxx_init_fiq(void)
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{
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void *fiqhandler_start;
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unsigned int fiqhandler_length;
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int ret;
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fiqhandler_start = &cns3xxx_fiq_start;
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fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
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ret = claim_fiq(&fh);
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if (ret) {
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return;
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}
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set_fiq_handler(fiqhandler_start, fiqhandler_length);
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fiq_buffer[0] = (unsigned int)&fiq_number[0];
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fiq_buffer[3] = 0;
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fiq_buffer[4] = (unsigned int)&fiq_number[1];
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fiq_buffer[7] = 0;
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}
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* Setup Secondary Core FIQ regs
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*/
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cns3xxx_set_fiq_regs();
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Fixup DMA Operations
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*
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*/
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cpu_cache.dma_map_area = (void *)smp_dma_map_area;
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cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
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cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores;
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unsigned int status;
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scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
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/* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
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* used in scu_get_core_count
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*/
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status = __raw_readl(scu_base + SCU_CPU_STATUS);
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for (i = 0; i < NR_CPUS+1; i++) {
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if (((status >> (i*2)) & 0x3) == 0)
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set_cpu_possible(i, true);
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else
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break;
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}
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ncores = i;
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++) {
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set_cpu_present(i, true);
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}
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/*
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* enable SCU
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*/
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scu_enable(scu_base);
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The boot monitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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__raw_writel(virt_to_phys(cns3xxx_secondary_startup),
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(void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
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/*
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* Setup FIQ's for main cpu
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*/
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cns3xxx_init_fiq();
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cns3xxx_set_fiq_regs();
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memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
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}
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static inline unsigned long cns3xxx_cpu_id(void)
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{
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unsigned long cpu;
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asm volatile(
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" mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
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: "=r" (cpu) : : "memory", "cc");
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return (cpu & 0xf);
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}
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void smp_dma_map_area(const void *addr, size_t size, int dir)
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{
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unsigned int cpu;
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unsigned long flags;
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raw_local_irq_save(flags);
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cpu = cns3xxx_cpu_id();
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if (cpu) {
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fiq_buffer[1] = (unsigned int)addr;
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fiq_buffer[2] = size;
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fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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cpu_cache_save.dma_map_area(addr, size, dir);
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while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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} else {
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fiq_buffer[5] = (unsigned int)addr;
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fiq_buffer[6] = size;
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fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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cpu_cache_save.dma_map_area(addr, size, dir);
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while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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}
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raw_local_irq_restore(flags);
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}
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void smp_dma_unmap_area(const void *addr, size_t size, int dir)
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{
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unsigned int cpu;
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unsigned long flags;
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raw_local_irq_save(flags);
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cpu = cns3xxx_cpu_id();
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if (cpu) {
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fiq_buffer[1] = (unsigned int)addr;
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fiq_buffer[2] = size;
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fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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cpu_cache_save.dma_unmap_area(addr, size, dir);
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while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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} else {
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fiq_buffer[5] = (unsigned int)addr;
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fiq_buffer[6] = size;
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fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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cpu_cache_save.dma_unmap_area(addr, size, dir);
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while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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}
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raw_local_irq_restore(flags);
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}
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void smp_dma_flush_range(const void *start, const void *end)
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{
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unsigned int cpu;
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unsigned long flags;
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raw_local_irq_save(flags);
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cpu = cns3xxx_cpu_id();
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if (cpu) {
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fiq_buffer[1] = (unsigned int)start;
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fiq_buffer[2] = (unsigned int)end;
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fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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cpu_cache_save.dma_flush_range(start, end);
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while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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} else {
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fiq_buffer[5] = (unsigned int)start;
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fiq_buffer[6] = (unsigned int)end;
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fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
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smp_mb();
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__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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cpu_cache_save.dma_flush_range(start, end);
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while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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}
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raw_local_irq_restore(flags);
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}
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