50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
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From 7328ff547389ee0b455cbf98bdfc819731d9f7b9 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 31 Aug 2012 14:22:35 +0200
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Subject: [PATCH] MIPS: ath79: use correct fractional dividers for
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{CPU,DDR}_PLL on AR934x
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The current dividers in the code are wrong and this
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leads to broken CPU frequency calculation on boards
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where the fractional part is used.
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For example, if the SoC is running from a 40MHz
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reference clock, refdiv=1, nint=14, outdiv=0 and
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nfrac=31 the real frequency is 579.375MHz but the
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current code calculates 569.687MHz instead.
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Because the system time is indirectly related to
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the CPU frequency the broken computation causes
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drift in the system time.
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The correct divider is 2^6 for the CPU PLL and 2^10
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for the DDR PLL. Use the correct values to fix the
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issue.
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Cc: <stable@vger.kernel.org> [3.5+]
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/clock.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(vo
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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- cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
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+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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@@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(vo
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AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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- ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
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+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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