70 lines
2.3 KiB
Diff
70 lines
2.3 KiB
Diff
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From 3ec31fa2ce161d35f787354037f94d9d22d825d1 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Fri, 20 Dec 2013 22:41:08 +0100
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Subject: [PATCH] clocksource: sun5i: Add support for reset controller
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The Allwinner A31 that uses this timer has the timer IP asserted in reset.
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Add an optional reset property to the DT, and deassert the timer from reset if
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it's there.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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.../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt | 4 ++++
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drivers/clocksource/timer-sun5i.c | 6 ++++++
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2 files changed, 10 insertions(+)
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diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
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index 7c26154..27cfc7d 100644
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--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
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+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
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@@ -9,6 +9,9 @@ Required properties:
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one)
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- clocks: phandle to the source clock (usually the AHB clock)
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+Optionnal properties:
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+- resets: phandle to a reset controller asserting the timer
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+
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Example:
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timer@01c60000 {
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@@ -19,4 +22,5 @@ timer@01c60000 {
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<0 53 1>,
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<0 54 1>;
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clocks = <&ahb1_gates 19>;
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+ resets = <&ahb1rst 19>;
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};
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diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
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index deebcd6..0226844 100644
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--- a/drivers/clocksource/timer-sun5i.c
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+++ b/drivers/clocksource/timer-sun5i.c
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@@ -16,6 +16,7 @@
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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+#include <linux/reset.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@@ -143,6 +144,7 @@ static u64 sun5i_timer_sched_read(void)
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static void __init sun5i_timer_init(struct device_node *node)
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{
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+ struct reset_control *rstc;
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unsigned long rate;
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struct clk *clk;
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int ret, irq;
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@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(struct device_node *node)
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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+ rstc = of_reset_control_get(node, NULL);
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+ if (!IS_ERR(rstc))
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+ reset_control_deassert(rstc);
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+
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writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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timer_base + TIMER_CTL_REG(1));
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--
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2.0.3
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