mirror of https://github.com/hak5/openwrt.git
278 lines
12 KiB
C
278 lines
12 KiB
C
/*
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* Freescale SEC (talitos) device dependent data structures
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*
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* Copyright (c) 2006 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* device ID register values */
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#define TALITOS_ID_SEC_2_0 0x40
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#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */
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/*
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* following num_channels, channel-fifo-depth, exec-unit-mask, and
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* descriptor-types-mask are for forward-compatibility with openfirmware
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* flat device trees
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*/
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/*
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* num_channels : the number of channels available in each SEC version.
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*/
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/* n.b. this driver requires these values be a power of 2 */
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#define TALITOS_NCHANNELS_SEC_1_0 4
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#define TALITOS_NCHANNELS_SEC_1_2 1
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#define TALITOS_NCHANNELS_SEC_2_0 4
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#define TALITOS_NCHANNELS_SEC_2_01 4
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#define TALITOS_NCHANNELS_SEC_2_1 4
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#define TALITOS_NCHANNELS_SEC_2_4 4
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/*
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* channel-fifo-depth : The number of descriptor
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* pointers a channel fetch fifo can hold.
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*/
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#define TALITOS_CHFIFOLEN_SEC_1_0 1
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#define TALITOS_CHFIFOLEN_SEC_1_2 1
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#define TALITOS_CHFIFOLEN_SEC_2_0 24
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#define TALITOS_CHFIFOLEN_SEC_2_01 24
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#define TALITOS_CHFIFOLEN_SEC_2_1 24
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#define TALITOS_CHFIFOLEN_SEC_2_4 24
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/*
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* exec-unit-mask : The bitmask representing what Execution Units (EUs)
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* are available. EU information should be encoded following the SEC's
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* EU_SEL0 bitfield documentation, i.e. as follows:
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*
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* bit 31 = set if SEC permits no-EU selection (should be always set)
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* bit 30 = set if SEC has the ARC4 EU (AFEU)
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* bit 29 = set if SEC has the des/3des EU (DEU)
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* bit 28 = set if SEC has the message digest EU (MDEU)
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* bit 27 = set if SEC has the random number generator EU (RNG)
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* bit 26 = set if SEC has the public key EU (PKEU)
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* bit 25 = set if SEC has the aes EU (AESU)
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* bit 24 = set if SEC has the Kasumi EU (KEU)
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*
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*/
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#define TALITOS_HAS_EU_NONE (1<<0)
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#define TALITOS_HAS_EU_AFEU (1<<1)
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#define TALITOS_HAS_EU_DEU (1<<2)
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#define TALITOS_HAS_EU_MDEU (1<<3)
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#define TALITOS_HAS_EU_RNG (1<<4)
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#define TALITOS_HAS_EU_PKEU (1<<5)
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#define TALITOS_HAS_EU_AESU (1<<6)
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#define TALITOS_HAS_EU_KEU (1<<7)
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/* the corresponding masks for each SEC version */
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#define TALITOS_HAS_EUS_SEC_1_0 0x7f
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#define TALITOS_HAS_EUS_SEC_1_2 0x4d
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#define TALITOS_HAS_EUS_SEC_2_0 0x7f
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#define TALITOS_HAS_EUS_SEC_2_01 0x7f
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#define TALITOS_HAS_EUS_SEC_2_1 0xff
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#define TALITOS_HAS_EUS_SEC_2_4 0x7f
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/*
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* descriptor-types-mask : The bitmask representing what descriptors
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* are available. Descriptor type information should be encoded
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* following the SEC's Descriptor Header Dword DESC_TYPE field
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* documentation, i.e. as follows:
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*
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* bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
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* bit 1 = set if SEC supports the ipsec_esp descriptor type
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* bit 2 = set if SEC supports the common_nonsnoop desc. type
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* bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
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* bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
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* bit 5 = set if SEC supports the srtp descriptor type
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* bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
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* bit 7 = set if SEC supports the pkeu_assemble descriptor type
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* bit 8 = set if SEC supports the aesu_key_expand_output desc.type
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* bit 9 = set if SEC supports the pkeu_ptmul descriptor type
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* bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
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* bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
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*
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* ..and so on and so forth.
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*/
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#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0)
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#define TALITOS_HAS_DT_IPSEC_ESP (1<<1)
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#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2)
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/* the corresponding masks for each SEC version */
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#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf
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#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf
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/*
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* a TALITOS_xxx_HI address points to the low data bits (32-63) of the register
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*/
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/* global register offset addresses */
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#define TALITOS_ID 0x1020
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#define TALITOS_ID_HI 0x1024
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#define TALITOS_MCR 0x1030 /* master control register */
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#define TALITOS_MCR_HI 0x1038 /* master control register */
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#define TALITOS_MCR_SWR 0x1
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#define TALITOS_IMR 0x1008 /* interrupt mask register */
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#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */
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#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */
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#define TALITOS_IMR_HI 0x100C /* interrupt mask register */
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#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */
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#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */
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#define TALITOS_ISR 0x1010 /* interrupt status register */
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#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */
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#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */
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#define TALITOS_ISR_HI 0x1014 /* interrupt status register */
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#define TALITOS_ICR 0x1018 /* interrupt clear register */
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#define TALITOS_ICR_HI 0x101C /* interrupt clear register */
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/* channel register address stride */
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#define TALITOS_CH_OFFSET 0x100
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/* channel register offset addresses and bits */
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#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */
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#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */
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#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */
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#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */
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#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */
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#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */
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#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */
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#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */
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#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */
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#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */
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#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */
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#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */
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#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel
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* Descriptor Buffer (debug) */
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/* execution unit register offset addresses and bits */
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#define TALITOS_DEUSR 0x2028 /* DEU status register */
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#define TALITOS_DEUSR_HI 0x202c /* DEU status register */
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#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */
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#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */
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#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */
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#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */
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#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */
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#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */
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#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */
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#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */
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#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */
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#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */
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#define TALITOS_RNGSR 0xa028 /* RNG status register */
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#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */
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#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */
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#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/
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#define TALITOS_RNGDSR 0xa010 /* RNG data size register */
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#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */
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#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */
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#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */
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#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */
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#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */
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#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */
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#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */
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/* descriptor pointer entry */
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struct talitos_desc_ptr {
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u16 len; /* length */
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u8 extent; /* jump (to s/g link table) and extent */
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u8 res; /* reserved */
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u32 ptr; /* pointer */
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};
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/* descriptor */
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struct talitos_desc {
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u32 hdr; /* header */
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u32 res; /* reserved */
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struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */
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};
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/* talitos descriptor header (hdr) bits */
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/* primary execution unit select */
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#define TALITOS_SEL0_AFEU 0x10000000
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#define TALITOS_SEL0_DEU 0x20000000
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#define TALITOS_SEL0_MDEU 0x30000000
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#define TALITOS_SEL0_RNG 0x40000000
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#define TALITOS_SEL0_PKEU 0x50000000
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#define TALITOS_SEL0_AESU 0x60000000
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/* primary execution unit mode (MODE0) and derivatives */
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#define TALITOS_MODE0_AESU_CBC 0x00200000
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#define TALITOS_MODE0_AESU_ENC 0x00100000
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#define TALITOS_MODE0_DEU_CBC 0x00400000
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#define TALITOS_MODE0_DEU_3DES 0x00200000
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#define TALITOS_MODE0_DEU_ENC 0x00100000
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#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */
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#define TALITOS_MODE0_MDEU_HMAC 0x00800000
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#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */
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#define TALITOS_MODE0_MDEU_MD5 0x00200000
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#define TALITOS_MODE0_MDEU_SHA256 0x00100000
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#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */
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#define TALITOS_MODE0_MDEU_MD5_HMAC \
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(TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC)
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#define TALITOS_MODE0_MDEU_SHA256_HMAC \
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(TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC)
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#define TALITOS_MODE0_MDEU_SHA1_HMAC \
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(TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC)
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/* secondary execution unit select (SEL1) */
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/* it's MDEU or nothing */
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#define TALITOS_SEL1_MDEU 0x00030000
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/* secondary execution unit mode (MODE1) and derivatives */
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#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */
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#define TALITOS_MODE1_MDEU_HMAC 0x00000800
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#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */
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#define TALITOS_MODE1_MDEU_MD5 0x00000200
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#define TALITOS_MODE1_MDEU_SHA256 0x00000100
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#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */
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#define TALITOS_MODE1_MDEU_MD5_HMAC \
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(TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC)
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#define TALITOS_MODE1_MDEU_SHA256_HMAC \
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(TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC)
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#define TALITOS_MODE1_MDEU_SHA1_HMAC \
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(TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC)
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/* direction of overall data flow (DIR) */
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#define TALITOS_DIR_OUTBOUND 0x00000000
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#define TALITOS_DIR_INBOUND 0x00000002
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/* done notification (DN) */
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#define TALITOS_DONE_NOTIFY 0x00000001
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/* descriptor types */
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/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */
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#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3)
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#define TD_TYPE_IPSEC_ESP (1 << 3)
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#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3)
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#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3)
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#define TALITOS_HDR_DONE_BITS 0xff000000
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#define DPRINTF(a...) do { \
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if (debug) { \
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printk("%s: ", sc ? \
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device_get_nameunit(sc->sc_cdev) : "talitos"); \
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printk(a); \
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} \
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} while (0)
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