mirror of https://github.com/hak5/openwrt.git
447 lines
13 KiB
Diff
447 lines
13 KiB
Diff
From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001
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From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
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Date: Mon, 23 Oct 2017 12:10:33 +0800
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Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks
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Add MT2712 clock dt-bindings, include topckgen, apmixedsys,
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infracfg, pericfg, mcucfg and subsystem clocks.
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Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++
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1 file changed, 427 insertions(+)
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create mode 100644 include/dt-bindings/clock/mt2712-clk.h
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--- /dev/null
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+++ b/include/dt-bindings/clock/mt2712-clk.h
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@@ -0,0 +1,427 @@
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+/*
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+ * Copyright (c) 2017 MediaTek Inc.
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+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef _DT_BINDINGS_CLK_MT2712_H
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+#define _DT_BINDINGS_CLK_MT2712_H
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+
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+/* APMIXEDSYS */
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+
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+#define CLK_APMIXED_MAINPLL 0
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+#define CLK_APMIXED_UNIVPLL 1
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+#define CLK_APMIXED_VCODECPLL 2
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+#define CLK_APMIXED_VENCPLL 3
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+#define CLK_APMIXED_APLL1 4
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+#define CLK_APMIXED_APLL2 5
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+#define CLK_APMIXED_LVDSPLL 6
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+#define CLK_APMIXED_LVDSPLL2 7
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+#define CLK_APMIXED_MSDCPLL 8
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+#define CLK_APMIXED_MSDCPLL2 9
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+#define CLK_APMIXED_TVDPLL 10
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+#define CLK_APMIXED_MMPLL 11
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+#define CLK_APMIXED_ARMCA35PLL 12
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+#define CLK_APMIXED_ARMCA72PLL 13
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+#define CLK_APMIXED_ETHERPLL 14
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+#define CLK_APMIXED_NR_CLK 15
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+
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+/* TOPCKGEN */
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+
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+#define CLK_TOP_ARMCA35PLL 0
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+#define CLK_TOP_ARMCA35PLL_600M 1
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+#define CLK_TOP_ARMCA35PLL_400M 2
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+#define CLK_TOP_ARMCA72PLL 3
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+#define CLK_TOP_SYSPLL 4
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+#define CLK_TOP_SYSPLL_D2 5
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+#define CLK_TOP_SYSPLL1_D2 6
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+#define CLK_TOP_SYSPLL1_D4 7
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+#define CLK_TOP_SYSPLL1_D8 8
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+#define CLK_TOP_SYSPLL1_D16 9
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+#define CLK_TOP_SYSPLL_D3 10
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+#define CLK_TOP_SYSPLL2_D2 11
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+#define CLK_TOP_SYSPLL2_D4 12
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+#define CLK_TOP_SYSPLL_D5 13
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+#define CLK_TOP_SYSPLL3_D2 14
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+#define CLK_TOP_SYSPLL3_D4 15
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+#define CLK_TOP_SYSPLL_D7 16
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+#define CLK_TOP_SYSPLL4_D2 17
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+#define CLK_TOP_SYSPLL4_D4 18
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+#define CLK_TOP_UNIVPLL 19
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+#define CLK_TOP_UNIVPLL_D7 20
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+#define CLK_TOP_UNIVPLL_D26 21
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+#define CLK_TOP_UNIVPLL_D52 22
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+#define CLK_TOP_UNIVPLL_D104 23
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+#define CLK_TOP_UNIVPLL_D208 24
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+#define CLK_TOP_UNIVPLL_D2 25
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+#define CLK_TOP_UNIVPLL1_D2 26
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+#define CLK_TOP_UNIVPLL1_D4 27
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+#define CLK_TOP_UNIVPLL1_D8 28
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+#define CLK_TOP_UNIVPLL_D3 29
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+#define CLK_TOP_UNIVPLL2_D2 30
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+#define CLK_TOP_UNIVPLL2_D4 31
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+#define CLK_TOP_UNIVPLL2_D8 32
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+#define CLK_TOP_UNIVPLL_D5 33
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+#define CLK_TOP_UNIVPLL3_D2 34
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+#define CLK_TOP_UNIVPLL3_D4 35
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+#define CLK_TOP_UNIVPLL3_D8 36
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+#define CLK_TOP_F_MP0_PLL1 37
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+#define CLK_TOP_F_MP0_PLL2 38
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+#define CLK_TOP_F_BIG_PLL1 39
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+#define CLK_TOP_F_BIG_PLL2 40
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+#define CLK_TOP_F_BUS_PLL1 41
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+#define CLK_TOP_F_BUS_PLL2 42
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+#define CLK_TOP_APLL1 43
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+#define CLK_TOP_APLL1_D2 44
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+#define CLK_TOP_APLL1_D4 45
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+#define CLK_TOP_APLL1_D8 46
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+#define CLK_TOP_APLL1_D16 47
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+#define CLK_TOP_APLL2 48
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+#define CLK_TOP_APLL2_D2 49
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+#define CLK_TOP_APLL2_D4 50
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+#define CLK_TOP_APLL2_D8 51
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+#define CLK_TOP_APLL2_D16 52
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+#define CLK_TOP_LVDSPLL 53
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+#define CLK_TOP_LVDSPLL_D2 54
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+#define CLK_TOP_LVDSPLL_D4 55
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+#define CLK_TOP_LVDSPLL_D8 56
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+#define CLK_TOP_LVDSPLL2 57
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+#define CLK_TOP_LVDSPLL2_D2 58
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+#define CLK_TOP_LVDSPLL2_D4 59
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+#define CLK_TOP_LVDSPLL2_D8 60
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+#define CLK_TOP_ETHERPLL_125M 61
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+#define CLK_TOP_ETHERPLL_50M 62
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+#define CLK_TOP_CVBS 63
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+#define CLK_TOP_CVBS_D2 64
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+#define CLK_TOP_SYS_26M 65
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+#define CLK_TOP_MMPLL 66
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+#define CLK_TOP_MMPLL_D2 67
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+#define CLK_TOP_VENCPLL 68
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+#define CLK_TOP_VENCPLL_D2 69
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+#define CLK_TOP_VCODECPLL 70
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+#define CLK_TOP_VCODECPLL_D2 71
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+#define CLK_TOP_TVDPLL 72
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+#define CLK_TOP_TVDPLL_D2 73
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+#define CLK_TOP_TVDPLL_D4 74
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+#define CLK_TOP_TVDPLL_D8 75
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+#define CLK_TOP_TVDPLL_429M 76
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+#define CLK_TOP_TVDPLL_429M_D2 77
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+#define CLK_TOP_TVDPLL_429M_D4 78
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+#define CLK_TOP_MSDCPLL 79
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+#define CLK_TOP_MSDCPLL_D2 80
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+#define CLK_TOP_MSDCPLL_D4 81
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+#define CLK_TOP_MSDCPLL2 82
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+#define CLK_TOP_MSDCPLL2_D2 83
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+#define CLK_TOP_MSDCPLL2_D4 84
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+#define CLK_TOP_CLK26M_D2 85
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+#define CLK_TOP_D2A_ULCLK_6P5M 86
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+#define CLK_TOP_VPLL3_DPIX 87
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+#define CLK_TOP_VPLL_DPIX 88
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+#define CLK_TOP_LTEPLL_FS26M 89
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+#define CLK_TOP_DMPLL 90
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+#define CLK_TOP_DSI0_LNTC 91
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+#define CLK_TOP_DSI1_LNTC 92
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+#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
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+#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
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+#define CLK_TOP_CLKRTC_EXT 95
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+#define CLK_TOP_CLKRTC_INT 96
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+#define CLK_TOP_CSI0 97
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+#define CLK_TOP_CVBSPLL 98
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+#define CLK_TOP_AXI_SEL 99
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+#define CLK_TOP_MEM_SEL 100
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+#define CLK_TOP_MM_SEL 101
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+#define CLK_TOP_PWM_SEL 102
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+#define CLK_TOP_VDEC_SEL 103
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+#define CLK_TOP_VENC_SEL 104
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+#define CLK_TOP_MFG_SEL 105
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+#define CLK_TOP_CAMTG_SEL 106
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+#define CLK_TOP_UART_SEL 107
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+#define CLK_TOP_SPI_SEL 108
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+#define CLK_TOP_USB20_SEL 109
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+#define CLK_TOP_USB30_SEL 110
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+#define CLK_TOP_MSDC50_0_HCLK_SEL 111
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+#define CLK_TOP_MSDC50_0_SEL 112
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+#define CLK_TOP_MSDC30_1_SEL 113
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+#define CLK_TOP_MSDC30_2_SEL 114
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+#define CLK_TOP_MSDC30_3_SEL 115
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+#define CLK_TOP_AUDIO_SEL 116
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+#define CLK_TOP_AUD_INTBUS_SEL 117
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+#define CLK_TOP_PMICSPI_SEL 118
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+#define CLK_TOP_DPILVDS1_SEL 119
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+#define CLK_TOP_ATB_SEL 120
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+#define CLK_TOP_NR_SEL 121
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+#define CLK_TOP_NFI2X_SEL 122
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+#define CLK_TOP_IRDA_SEL 123
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+#define CLK_TOP_CCI400_SEL 124
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+#define CLK_TOP_AUD_1_SEL 125
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+#define CLK_TOP_AUD_2_SEL 126
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+#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
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+#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
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+#define CLK_TOP_SCAM_SEL 129
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+#define CLK_TOP_NFIECC_SEL 130
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+#define CLK_TOP_PE2_MAC_P0_SEL 131
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+#define CLK_TOP_PE2_MAC_P1_SEL 132
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+#define CLK_TOP_DPILVDS_SEL 133
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+#define CLK_TOP_MSDC50_3_HCLK_SEL 134
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+#define CLK_TOP_HDCP_SEL 135
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+#define CLK_TOP_HDCP_24M_SEL 136
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+#define CLK_TOP_RTC_SEL 137
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+#define CLK_TOP_SPINOR_SEL 138
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+#define CLK_TOP_APLL_SEL 139
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+#define CLK_TOP_APLL2_SEL 140
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+#define CLK_TOP_A1SYS_HP_SEL 141
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+#define CLK_TOP_A2SYS_HP_SEL 142
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+#define CLK_TOP_ASM_L_SEL 143
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+#define CLK_TOP_ASM_M_SEL 144
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+#define CLK_TOP_ASM_H_SEL 145
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+#define CLK_TOP_I2SO1_SEL 146
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+#define CLK_TOP_I2SO2_SEL 147
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+#define CLK_TOP_I2SO3_SEL 148
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+#define CLK_TOP_TDMO0_SEL 149
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+#define CLK_TOP_TDMO1_SEL 150
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+#define CLK_TOP_I2SI1_SEL 151
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+#define CLK_TOP_I2SI2_SEL 152
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+#define CLK_TOP_I2SI3_SEL 153
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+#define CLK_TOP_ETHER_125M_SEL 154
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+#define CLK_TOP_ETHER_50M_SEL 155
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+#define CLK_TOP_JPGDEC_SEL 156
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+#define CLK_TOP_SPISLV_SEL 157
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+#define CLK_TOP_ETHER_50M_RMII_SEL 158
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+#define CLK_TOP_CAM2TG_SEL 159
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+#define CLK_TOP_DI_SEL 160
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+#define CLK_TOP_TVD_SEL 161
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+#define CLK_TOP_I2C_SEL 162
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+#define CLK_TOP_PWM_INFRA_SEL 163
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+#define CLK_TOP_MSDC0P_AES_SEL 164
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+#define CLK_TOP_CMSYS_SEL 165
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+#define CLK_TOP_GCPU_SEL 166
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+#define CLK_TOP_AUD_APLL1_SEL 167
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+#define CLK_TOP_AUD_APLL2_SEL 168
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+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
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+#define CLK_TOP_APLL_DIV0 170
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+#define CLK_TOP_APLL_DIV1 171
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+#define CLK_TOP_APLL_DIV2 172
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+#define CLK_TOP_APLL_DIV3 173
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+#define CLK_TOP_APLL_DIV4 174
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+#define CLK_TOP_APLL_DIV5 175
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+#define CLK_TOP_APLL_DIV6 176
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+#define CLK_TOP_APLL_DIV7 177
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+#define CLK_TOP_APLL_DIV_PDN0 178
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+#define CLK_TOP_APLL_DIV_PDN1 179
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+#define CLK_TOP_APLL_DIV_PDN2 180
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+#define CLK_TOP_APLL_DIV_PDN3 181
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+#define CLK_TOP_APLL_DIV_PDN4 182
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+#define CLK_TOP_APLL_DIV_PDN5 183
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+#define CLK_TOP_APLL_DIV_PDN6 184
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+#define CLK_TOP_APLL_DIV_PDN7 185
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+#define CLK_TOP_NR_CLK 186
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+
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+/* INFRACFG */
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+
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+#define CLK_INFRA_DBGCLK 0
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+#define CLK_INFRA_GCE 1
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+#define CLK_INFRA_M4U 2
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+#define CLK_INFRA_KP 3
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+#define CLK_INFRA_AO_SPI0 4
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+#define CLK_INFRA_AO_SPI1 5
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+#define CLK_INFRA_AO_UART5 6
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+#define CLK_INFRA_NR_CLK 7
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+
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+/* PERICFG */
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+
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+#define CLK_PERI_NFI 0
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+#define CLK_PERI_THERM 1
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+#define CLK_PERI_PWM0 2
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+#define CLK_PERI_PWM1 3
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+#define CLK_PERI_PWM2 4
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+#define CLK_PERI_PWM3 5
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+#define CLK_PERI_PWM4 6
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+#define CLK_PERI_PWM5 7
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+#define CLK_PERI_PWM6 8
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+#define CLK_PERI_PWM7 9
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+#define CLK_PERI_PWM 10
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+#define CLK_PERI_AP_DMA 11
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+#define CLK_PERI_MSDC30_0 12
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+#define CLK_PERI_MSDC30_1 13
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+#define CLK_PERI_MSDC30_2 14
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+#define CLK_PERI_MSDC30_3 15
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+#define CLK_PERI_UART0 16
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+#define CLK_PERI_UART1 17
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+#define CLK_PERI_UART2 18
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+#define CLK_PERI_UART3 19
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+#define CLK_PERI_I2C0 20
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+#define CLK_PERI_I2C1 21
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+#define CLK_PERI_I2C2 22
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+#define CLK_PERI_I2C3 23
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+#define CLK_PERI_I2C4 24
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+#define CLK_PERI_AUXADC 25
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+#define CLK_PERI_SPI0 26
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+#define CLK_PERI_SPI 27
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+#define CLK_PERI_I2C5 28
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+#define CLK_PERI_SPI2 29
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+#define CLK_PERI_SPI3 30
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+#define CLK_PERI_SPI5 31
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+#define CLK_PERI_UART4 32
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+#define CLK_PERI_SFLASH 33
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+#define CLK_PERI_GMAC 34
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+#define CLK_PERI_PCIE0 35
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+#define CLK_PERI_PCIE1 36
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+#define CLK_PERI_GMAC_PCLK 37
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+#define CLK_PERI_MSDC50_0_EN 38
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+#define CLK_PERI_MSDC30_1_EN 39
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+#define CLK_PERI_MSDC30_2_EN 40
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+#define CLK_PERI_MSDC30_3_EN 41
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+#define CLK_PERI_MSDC50_0_HCLK_EN 42
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+#define CLK_PERI_MSDC50_3_HCLK_EN 43
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+#define CLK_PERI_NR_CLK 44
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+
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+/* MCUCFG */
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+
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+#define CLK_MCU_MP0_SEL 0
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+#define CLK_MCU_MP2_SEL 1
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+#define CLK_MCU_BUS_SEL 2
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+#define CLK_MCU_NR_CLK 3
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+
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+/* MFGCFG */
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+
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+#define CLK_MFG_BG3D 0
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+#define CLK_MFG_NR_CLK 1
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+
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+/* MMSYS */
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+
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+#define CLK_MM_SMI_COMMON 0
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+#define CLK_MM_SMI_LARB0 1
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+#define CLK_MM_CAM_MDP 2
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+#define CLK_MM_MDP_RDMA0 3
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+#define CLK_MM_MDP_RDMA1 4
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+#define CLK_MM_MDP_RSZ0 5
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+#define CLK_MM_MDP_RSZ1 6
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+#define CLK_MM_MDP_RSZ2 7
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+#define CLK_MM_MDP_TDSHP0 8
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+#define CLK_MM_MDP_TDSHP1 9
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+#define CLK_MM_MDP_CROP 10
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+#define CLK_MM_MDP_WDMA 11
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+#define CLK_MM_MDP_WROT0 12
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+#define CLK_MM_MDP_WROT1 13
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+#define CLK_MM_FAKE_ENG 14
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+#define CLK_MM_MUTEX_32K 15
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+#define CLK_MM_DISP_OVL0 16
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+#define CLK_MM_DISP_OVL1 17
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+#define CLK_MM_DISP_RDMA0 18
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+#define CLK_MM_DISP_RDMA1 19
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+#define CLK_MM_DISP_RDMA2 20
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+#define CLK_MM_DISP_WDMA0 21
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+#define CLK_MM_DISP_WDMA1 22
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+#define CLK_MM_DISP_COLOR0 23
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+#define CLK_MM_DISP_COLOR1 24
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+#define CLK_MM_DISP_AAL 25
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+#define CLK_MM_DISP_GAMMA 26
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+#define CLK_MM_DISP_UFOE 27
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+#define CLK_MM_DISP_SPLIT0 28
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+#define CLK_MM_DISP_OD 29
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+#define CLK_MM_DISP_PWM0_MM 30
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+#define CLK_MM_DISP_PWM0_26M 31
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+#define CLK_MM_DISP_PWM1_MM 32
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+#define CLK_MM_DISP_PWM1_26M 33
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+#define CLK_MM_DSI0_ENGINE 34
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+#define CLK_MM_DSI0_DIGITAL 35
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+#define CLK_MM_DSI1_ENGINE 36
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+#define CLK_MM_DSI1_DIGITAL 37
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+#define CLK_MM_DPI_PIXEL 38
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+#define CLK_MM_DPI_ENGINE 39
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+#define CLK_MM_DPI1_PIXEL 40
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+#define CLK_MM_DPI1_ENGINE 41
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+#define CLK_MM_LVDS_PIXEL 42
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+#define CLK_MM_LVDS_CTS 43
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+#define CLK_MM_SMI_LARB4 44
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+#define CLK_MM_SMI_COMMON1 45
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+#define CLK_MM_SMI_LARB5 46
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+#define CLK_MM_MDP_RDMA2 47
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+#define CLK_MM_MDP_TDSHP2 48
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+#define CLK_MM_DISP_OVL2 49
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+#define CLK_MM_DISP_WDMA2 50
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+#define CLK_MM_DISP_COLOR2 51
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+#define CLK_MM_DISP_AAL1 52
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+#define CLK_MM_DISP_OD1 53
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+#define CLK_MM_LVDS1_PIXEL 54
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+#define CLK_MM_LVDS1_CTS 55
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+#define CLK_MM_SMI_LARB7 56
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+#define CLK_MM_MDP_RDMA3 57
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+#define CLK_MM_MDP_WROT2 58
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+#define CLK_MM_DSI2 59
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+#define CLK_MM_DSI2_DIGITAL 60
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+#define CLK_MM_DSI3 61
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+#define CLK_MM_DSI3_DIGITAL 62
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+#define CLK_MM_NR_CLK 63
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+
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+/* IMGSYS */
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+
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+#define CLK_IMG_SMI_LARB2 0
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+#define CLK_IMG_SENINF_SCAM_EN 1
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+#define CLK_IMG_SENINF_CAM_EN 2
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+#define CLK_IMG_CAM_SV_EN 3
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+#define CLK_IMG_CAM_SV1_EN 4
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+#define CLK_IMG_CAM_SV2_EN 5
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+#define CLK_IMG_NR_CLK 6
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+
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+/* BDPSYS */
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+
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+#define CLK_BDP_BRIDGE_B 0
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+#define CLK_BDP_BRIDGE_DRAM 1
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+#define CLK_BDP_LARB_DRAM 2
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+#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
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+#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
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+#define CLK_BDP_WR_CHANNEL_VDI_B 5
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+#define CLK_BDP_MT_B 6
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+#define CLK_BDP_DISPFMT_27M 7
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+#define CLK_BDP_DISPFMT_27M_VDOUT 8
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+#define CLK_BDP_DISPFMT_27_74_74 9
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+#define CLK_BDP_DISPFMT_2FS 10
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+#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
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+#define CLK_BDP_DISPFMT_B 12
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+#define CLK_BDP_VDO_DRAM 13
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+#define CLK_BDP_VDO_2FS 14
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+#define CLK_BDP_VDO_B 15
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+#define CLK_BDP_WR_CHANNEL_DI_PXL 16
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+#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
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+#define CLK_BDP_WR_CHANNEL_DI_B 18
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+#define CLK_BDP_NR_AGENT 19
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+#define CLK_BDP_NR_DRAM 20
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+#define CLK_BDP_NR_B 21
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+#define CLK_BDP_BRIDGE_RT_B 22
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+#define CLK_BDP_BRIDGE_RT_DRAM 23
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+#define CLK_BDP_LARB_RT_DRAM 24
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+#define CLK_BDP_TVD_TDC 25
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+#define CLK_BDP_TVD_54 26
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+#define CLK_BDP_TVD_CBUS 27
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+#define CLK_BDP_NR_CLK 28
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+
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+/* VDECSYS */
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+
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+#define CLK_VDEC_CKEN 0
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+#define CLK_VDEC_LARB1_CKEN 1
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+#define CLK_VDEC_IMGRZ_CKEN 2
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+#define CLK_VDEC_NR_CLK 3
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+
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+/* VENCSYS */
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+
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+#define CLK_VENC_SMI_COMMON_CON 0
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+#define CLK_VENC_VENC 1
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+#define CLK_VENC_SMI_LARB6 2
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+#define CLK_VENC_NR_CLK 3
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+
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+/* JPGDECSYS */
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+
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+#define CLK_JPGDEC_JPGDEC1 0
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+#define CLK_JPGDEC_JPGDEC 1
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+#define CLK_JPGDEC_NR_CLK 2
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+
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+#endif /* _DT_BINDINGS_CLK_MT2712_H */
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