openwrt/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts

/*
 * TP-Link TL-WDR4900 v1 Device Tree Source
 *
 * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/include/ "fsl/p1010si-pre.dtsi"

/ {
	model = "TP-Link TL-WDR4900 v1";
	compatible = "tplink,tl-wdr4900-v1";

	chosen {
		bootargs = "console=ttyS0,115200";
/*
		stdout-path = "/soc@ffe00000/serial@4500";
*/
	};

	aliases {
		spi0 = &spi0;
		led-boot = &system_green;
		led-failsafe = &system_green;
		led-running = &system_green;
		led-upgrade = &system_green;
	};

	memory {
		device_type = "memory";
	};

	soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		spi0: spi@7000 {
			flash@0 {
				compatible = "jedec,spi-nor";
				reg = <0>;
				spi-max-frequency = <25000000>;

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					partition@0 {
						reg = <0x0 0x0050000>;
						label = "u-boot";
						read-only;
					};

					partition@50000 {
						reg = <0x00050000 0x00010000>;
						label = "dtb";
						read-only;
					};

					partition@60000 {
						compatible = "tplink,firmware";
						reg = <0x00060000 0x00f80000>;
						label = "firmware";
					};

					config: partition@fe0000 {
						reg = <0x00fe0000 0x00010000>;
						label = "config";
						read-only;
					};

					partition@ff0000 {
						reg = <0x00ff0000 0x00010000>;
						label = "caldata";
						read-only;
					};
				};
			};
		};

		gpio0: gpio-controller@fc00 {
		};

		usb@22000 {
			phy_type = "utmi";
			dr_mode = "host";
		};

		mdio@24000 {
			phy0: ethernet-phy@0 {
				reg = <0x0>;
				qca,ar8327-initvals = <
					0x00004 0x07600000 /* PAD0_MODE */
					0x00008 0x00000000 /* PAD5_MODE */
					0x0000c 0x01000000 /* PAD6_MODE */
					0x00010 0x40000000 /* POWER_ON_STRIP */
					0x00050 0xcf35cf35 /* LED_CTRL0 */
					0x00054 0xcf35cf35 /* LED_CTRL1 */
					0x00058 0xcf35cf35 /* LED_CTRL2 */
					0x0005c 0x03ffff00 /* LED_CTRL3 */
					0x0007c 0x0000007e /* PORT0_STATUS */
					0x00094 0x00000200 /* PORT6_STATUS */
				>;
			};
		};

		mdio@25000 {
			status = "disabled";
		};

		mdio@26000 {
			status = "disabled";
		};

		enet0: ethernet@b0000 {
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			mtd-mac-address = <&config 0x144>;
		};

		enet1: ethernet@b1000 {
			status = "disabled";
		};

		enet2: ethernet@b2000 {
			status = "disabled";
		};

		sdhc@2e000 {
			status = "disabled";
		};

		serial1: serial@4600 {
			status = "disabled";
		};

		can0: can@1c000 {
			status = "disabled";
		};

		can1: can@1d000 {
			status = "disabled";
		};

		ptp_clock@b0e00 {
			compatible = "fsl,etsec-ptp";
			reg = <0xb0e00 0xb0>;
			interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
			fsl,cksel       = <1>;
			fsl,tclk-period	= <5>;
			fsl,tmr-prsc	= <2>;
			fsl,tmr-add	= <0xcccccccd>;
			fsl,tmr-fiper1	= <0x3b9ac9fb>; /* 1PPS */
			fsl,tmr-fiper2	= <0x00018696>;
			fsl,max-adj	= <249999999>;
		};
	};

	pci0: pcie@ffe09000 {
		reg = <0 0xffe09000 0 0x1000>;
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	ifc: ifc@ffe1e000 {
		status = "disabled";
	};

	leds {
		compatible = "gpio-leds";

		system_green: system {
			gpios = <&gpio0 2 1>; /* active low */
			label = "tp-link:blue:system";
		};

		usb1 {
			gpios = <&gpio0 3 1>; /* active low */
			label = "tp-link:green:usb1";
		};

		usb2 {
			gpios = <&gpio0 4 1>; /* active low */
			label = "tp-link:green:usb2";
		};

		usbpower {
			gpios = <&gpio0 10 1>; /* active low */
			label = "tp-link:usb:power";
		};
	};

	buttons {
		compatible = "gpio-keys";

		reset {
			label = "Reset button";
			gpios = <&gpio0 5 1>; /* active low */
			linux,code = <0x198>; /* KEY_RESTART */
		};

		rfkill {
			label = "RFKILL switch";
			gpios = <&gpio0 11 1>; /* active low */
			linux,code = <0xf7>; /* RFKill */
		};
	};
};

/include/ "fsl/p1010si-post.dtsi"

/ {
	cpus {
		PowerPC,P1010@0 {
			bus-frequency = <399999996>;
			timebase-frequency = <49999999>;
			clock-frequency = <799999992>;
		};
	};

	memory {
		reg = <0x0 0x0 0x0 0x8000000>;
	};

	soc@ffe00000 {
		bus-frequency = <399999996>;

		serial@4600 {
			clock-frequency = <399999996>;
		};

		serial@4500 {
			clock-frequency = <399999996>;
		};

		pic@40000 {
			clock-frequency = <399999996>;
		};
	};
};

/*
 * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
 * related to the P1010.
 *
 * NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
 * datasheet states that the P1014 does not include the accelerated crypto
 * module (CAAM/SEC4) which is present in the P1010.
 *
 * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
 * SEC4 module, but states that SoCs with System Version Register values
 * 0x80F10110 or 0x80F10120 do not have the security feature.
 *
 * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
 * as: core rev 1.0, "P1014 (without security)".
 *
 * The SVR value is reported by uboot on the serial console.
 */

/ {
	soc: soc@ffe00000 {
		/delete-node/ crypto@30000; /* Pulled in by p1010si-post */
	};
};