mirror of https://github.com/hak5/openwrt.git
108 lines
3.4 KiB
Diff
108 lines
3.4 KiB
Diff
From d377732c8c9aac14ccb900b65678558b0fb8f0f3 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
|
|
Date: Thu, 17 Jul 2014 23:26:32 +0200
|
|
Subject: [PATCH 152/153] Revert "MIPS: Delete unused function
|
|
add_temporary_entry."
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
This reverts commit d7a887a73dec6c387b02a966a71aac767bbd9ce6.
|
|
|
|
Function add_temporary_entry is needed by bcm47xx to support highmem. We
|
|
need to add a temporary entry to check for amount of RAM.
|
|
The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL.
|
|
|
|
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
|
|
Cc: linux-mips@linux-mips.org
|
|
Cc: Hauke Mehrtens <hauke@hauke-m.de>
|
|
Patchwork: https://patchwork.linux-mips.org/patch/7395/
|
|
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
---
|
|
arch/mips/include/asm/pgtable-32.h | 10 ++++++++
|
|
arch/mips/mm/tlb-r4k.c | 47 ++++++++++++++++++++++++++++++++++++++
|
|
2 files changed, 57 insertions(+)
|
|
|
|
--- a/arch/mips/include/asm/pgtable-32.h
|
|
+++ b/arch/mips/include/asm/pgtable-32.h
|
|
@@ -19,6 +19,16 @@
|
|
#include <asm-generic/pgtable-nopmd.h>
|
|
|
|
/*
|
|
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
|
|
+ * starting at the top and working down. This is for populating the
|
|
+ * TLB before trap_init() puts the TLB miss handler in place. It
|
|
+ * should be used only for entries matching the actual page tables,
|
|
+ * to prevent inconsistencies.
|
|
+ */
|
|
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|
+ unsigned long entryhi, unsigned long pagemask);
|
|
+
|
|
+/*
|
|
* Basically we have the same two-level (which is the logical three level
|
|
* Linux page table layout folded) page tables as the i386. Some day
|
|
* when we have proper page coloring support we can have a 1% quicker
|
|
--- a/arch/mips/mm/tlb-r4k.c
|
|
+++ b/arch/mips/mm/tlb-r4k.c
|
|
@@ -389,6 +389,51 @@ int __init has_transparent_hugepage(void
|
|
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
|
|
|
+/*
|
|
+ * Used for loading TLB entries before trap_init() has started, when we
|
|
+ * don't actually want to add a wired entry which remains throughout the
|
|
+ * lifetime of the system
|
|
+ */
|
|
+
|
|
+static int temp_tlb_entry __cpuinitdata;
|
|
+
|
|
+__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|
+ unsigned long entryhi, unsigned long pagemask)
|
|
+{
|
|
+ int ret = 0;
|
|
+ unsigned long flags;
|
|
+ unsigned long wired;
|
|
+ unsigned long old_pagemask;
|
|
+ unsigned long old_ctx;
|
|
+
|
|
+ local_irq_save(flags);
|
|
+ /* Save old context and create impossible VPN2 value */
|
|
+ old_ctx = read_c0_entryhi();
|
|
+ old_pagemask = read_c0_pagemask();
|
|
+ wired = read_c0_wired();
|
|
+ if (--temp_tlb_entry < wired) {
|
|
+ printk(KERN_WARNING
|
|
+ "No TLB space left for add_temporary_entry\n");
|
|
+ ret = -ENOSPC;
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ write_c0_index(temp_tlb_entry);
|
|
+ write_c0_pagemask(pagemask);
|
|
+ write_c0_entryhi(entryhi);
|
|
+ write_c0_entrylo0(entrylo0);
|
|
+ write_c0_entrylo1(entrylo1);
|
|
+ mtc0_tlbw_hazard();
|
|
+ tlb_write_indexed();
|
|
+ tlbw_use_hazard();
|
|
+
|
|
+ write_c0_entryhi(old_ctx);
|
|
+ write_c0_pagemask(old_pagemask);
|
|
+out:
|
|
+ local_irq_restore(flags);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
static int __cpuinitdata ntlb;
|
|
static int __init set_ntlb(char *str)
|
|
{
|
|
@@ -426,6 +471,8 @@ void __cpuinit tlb_init(void)
|
|
write_c0_pagegrain(pg);
|
|
}
|
|
|
|
+ temp_tlb_entry = current_cpu_data.tlbsize - 1;
|
|
+
|
|
/* From this point on the ARC firmware is dead. */
|
|
local_flush_tlb_all();
|
|
|