mirror of https://github.com/hak5/openwrt.git
173 lines
4.6 KiB
Diff
173 lines
4.6 KiB
Diff
From 27c4128ab1835a2aff1a0ce6413bb21cfa614d93 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 21 Feb 2012 09:48:11 +0100
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Subject: [PATCH 36/70] MIPS: lantiq: add vr9 support
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VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
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This patch adds the clkdev init code and SoC detection for the VR9.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
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arch/mips/lantiq/xway/clk.c | 83 ++++++++++++++++++++
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arch/mips/lantiq/xway/prom.c | 6 ++
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arch/mips/lantiq/xway/sysctrl.c | 12 +++-
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4 files changed, 103 insertions(+), 1 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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index e9d2dd4..5d11eb7 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -21,6 +21,9 @@
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#define SOC_ID_ARX188 0x16C
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#define SOC_ID_ARX168 0x16D
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#define SOC_ID_ARX182 0x16F
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+#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */
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+#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */
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+#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */
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/* SoC Types */
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#define SOC_TYPE_DANUBE 0x01
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diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
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index f3b50fc..3635c9f 100644
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--- a/arch/mips/lantiq/xway/clk.c
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+++ b/arch/mips/lantiq/xway/clk.c
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@@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
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return ddr_clock >> 1;
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return ddr_clock;
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}
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+
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+unsigned long ltq_vr9_cpu_hz(void)
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+{
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+ unsigned int cpu_sel;
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+ unsigned long clk;
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+
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+ cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
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+
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+ switch (cpu_sel) {
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+ case 0:
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+ clk = CLOCK_600M;
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+ break;
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+ case 1:
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+ clk = CLOCK_500M;
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+ break;
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+ case 2:
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+ clk = CLOCK_393M;
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+ break;
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+ case 3:
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+ clk = CLOCK_333M;
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+ break;
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+ case 5:
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+ case 6:
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+ clk = CLOCK_196_608M;
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+ break;
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+ case 7:
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+ clk = CLOCK_167M;
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+ break;
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+ case 4:
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+ case 8:
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+ case 9:
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+ clk = CLOCK_125M;
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+ break;
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+ default:
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+ clk = 0;
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+ break;
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+ }
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+
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+ return clk;
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+}
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+
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+unsigned long ltq_vr9_fpi_hz(void)
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+{
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+ unsigned int ocp_sel, cpu_clk;
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+ unsigned long clk;
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+
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+ cpu_clk = ltq_vr9_cpu_hz();
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+ ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
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+
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+ switch (ocp_sel) {
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+ case 0:
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+ /* OCP ratio 1 */
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+ clk = cpu_clk;
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+ break;
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+ case 2:
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+ /* OCP ratio 2 */
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+ clk = cpu_clk / 2;
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+ break;
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+ case 3:
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+ /* OCP ratio 2.5 */
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+ clk = (cpu_clk * 2) / 5;
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+ break;
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+ case 4:
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+ /* OCP ratio 3 */
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+ clk = cpu_clk / 3;
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+ break;
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+ default:
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+ clk = 0;
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+ break;
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+ }
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+
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+ return clk;
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+}
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+
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+unsigned long ltq_vr9_io_region_clock(void)
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+{
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+ return ltq_vr9_fpi_hz();
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+}
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+
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+unsigned long ltq_vr9_fpi_bus_clock(int fpi)
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+{
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+ return ltq_vr9_fpi_hz();
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+}
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diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
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index 0929acb..b6f56b7 100644
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--- a/arch/mips/lantiq/xway/prom.c
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+++ b/arch/mips/lantiq/xway/prom.c
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@@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
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#endif
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break;
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+ case SOC_ID_VRX268:
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+ case SOC_ID_VRX288:
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+ i->name = SOC_VR9;
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+ i->type = SOC_TYPE_VR9;
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+ break;
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+
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default:
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unreachable();
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break;
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diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
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index c5782b5..38f02f9 100644
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
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clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
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clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
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- clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
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+ if (!ltq_is_vr9())
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+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
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if (ltq_is_ase()) {
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if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
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clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
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@@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
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clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
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clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
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clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
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+ } else if (ltq_is_vr9()) {
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+ clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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+ ltq_vr9_io_region_clock());
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+ clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
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+ clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
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+ clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
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+ clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
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+ clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
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+ clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_io_region_clock());
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--
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1.7.7.1
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