mirror of https://github.com/hak5/openwrt.git
980 lines
29 KiB
Diff
980 lines
29 KiB
Diff
From 940b4fea5ebfde3abe03c6469a57c01ee961497a Mon Sep 17 00:00:00 2001
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From: Kurt Mahan <kmahan@freescale.com>
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Date: Wed, 18 Jun 2008 15:20:21 -0600
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Subject: [PATCH] Split 547x/548x and 5445x cache routines into separate files.
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LTIBName: mcfv4e-cache-split
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Signed-off-by: Kurt Mahan <kmahan@freescale.com>
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---
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include/asm-m68k/cf_5445x_cacheflush.h | 447 ++++++++++++++++++++++++++++++++
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include/asm-m68k/cf_548x_cacheflush.h | 259 ++++++++++++++++++
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include/asm-m68k/cf_cacheflush.h | 244 +-----------------
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3 files changed, 711 insertions(+), 239 deletions(-)
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create mode 100644 include/asm-m68k/cf_5445x_cacheflush.h
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create mode 100644 include/asm-m68k/cf_548x_cacheflush.h
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--- /dev/null
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+++ b/include/asm-m68k/cf_5445x_cacheflush.h
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@@ -0,0 +1,447 @@
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+/*
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+ * include/asm-m68k/cf_5445x_cacheflush.h - Coldfire 5445x Cache
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+ *
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+ * Based on include/asm-m68k/cacheflush.h
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+ *
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+ * Coldfire pieces by:
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+ * Kurt Mahan kmahan@freescale.com
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+ *
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+ * Copyright Freescale Semiconductor, Inc. 2007, 2008
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+#ifndef M68K_CF_5445x_CACHEFLUSH_H
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+#define M68K_CF_5445x_CACHEFLUSH_H
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+
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+#include <asm/cfcache.h>
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+
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+/*
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+ * Coldfire Cache Model
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+ *
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+ * The Coldfire processors use a Harvard architecture cache configured
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+ * as four-way set associative. The cache does not implement bus snooping
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+ * so cache coherency with other masters must be maintained in software.
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+ *
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+ * The cache is managed via the CPUSHL instruction in conjunction with
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+ * bits set in the CACR (cache control register). Currently the code
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+ * uses the CPUSHL enhancement which adds the ability to
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+ * invalidate/clear/push a cacheline by physical address. This feature
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+ * is designated in the Hardware Configuration Register [D1-CPES].
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+ *
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+ * CACR Bits:
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+ * DPI[28] cpushl invalidate disable for d-cache
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+ * IDPI[12] cpushl invalidate disable for i-cache
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+ * SPA[14] cpushl search by physical address
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+ * IVO[20] cpushl invalidate only
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+ *
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+ * Random Terminology:
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+ * * invalidate = reset the cache line's valid bit
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+ * * push = generate a line-sized store of the data if its contents are marked
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+ * as modifed (the modified flag is cleared after the store)
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+ * * clear = push + invalidate
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+ */
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+
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+/**
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+ * flush_icache - Flush all of the instruction cache
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+ */
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+static inline void flush_icache(void)
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+{
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+ asm volatile("nop\n"
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+ "moveq%.l #0,%%d0\n"
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+ "moveq%.l #0,%%d1\n"
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+ "move%.l %%d0,%%a0\n"
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+ "1:\n"
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+ "cpushl %%ic,(%%a0)\n"
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+ "add%.l #0x0010,%%a0\n"
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+ "addq%.l #1,%%d1\n"
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+ "cmpi%.l %0,%%d1\n"
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+ "bne 1b\n"
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+ "moveq%.l #0,%%d1\n"
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+ "addq%.l #1,%%d0\n"
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+ "move%.l %%d0,%%a0\n"
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+ "cmpi%.l #4,%%d0\n"
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+ "bne 1b\n"
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+ : : "i" (CACHE_SETS)
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+ : "a0", "d0", "d1");
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+}
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+
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+/**
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+ * flush_dcache - Flush all of the data cache
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+ */
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+static inline void flush_dcache(void)
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+{
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+ asm volatile("nop\n"
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+ "moveq%.l #0,%%d0\n"
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+ "moveq%.l #0,%%d1\n"
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+ "move%.l %%d0,%%a0\n"
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+ "1:\n"
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+ "cpushl %%dc,(%%a0)\n"
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+ "add%.l #0x0010,%%a0\n"
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+ "addq%.l #1,%%d1\n"
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+ "cmpi%.l %0,%%d1\n"
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+ "bne 1b\n"
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+ "moveq%.l #0,%%d1\n"
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+ "addq%.l #1,%%d0\n"
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+ "move%.l %%d0,%%a0\n"
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+ "cmpi%.l #4,%%d0\n"
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+ "bne 1b\n"
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+ : : "i" (CACHE_SETS)
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+ : "a0", "d0", "d1");
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+}
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+
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+/**
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+ * flush_bcache - Flush all of both caches
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+ */
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+static inline void flush_bcache(void)
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+{
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+ asm volatile("nop\n"
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+ "moveq%.l #0,%%d0\n"
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+ "moveq%.l #0,%%d1\n"
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+ "move%.l %%d0,%%a0\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "add%.l #0x0010,%%a0\n"
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+ "addq%.l #1,%%d1\n"
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+ "cmpi%.l %0,%%d1\n"
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+ "bne 1b\n"
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+ "moveq%.l #0,%%d1\n"
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+ "addq%.l #1,%%d0\n"
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+ "move%.l %%d0,%%a0\n"
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+ "cmpi%.l #4,%%d0\n"
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+ "bne 1b\n"
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+ : : "i" (CACHE_SETS)
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+ : "a0", "d0", "d1");
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+}
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+
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+/**
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+ * cf_cache_clear - invalidate cache
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+ * @paddr: starting physical address
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+ * @len: number of bytes
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+ *
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+ * Invalidate cache lines starting at paddr for len bytes.
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+ * Those lines are not pushed.
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+ */
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+static inline void cf_cache_clear(unsigned long paddr, int len)
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+{
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+ /* number of lines */
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+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
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+ if (len == 0)
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+ return;
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+
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+ /* align on set boundary */
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+ paddr &= 0xfffffff0;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%d0\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "subq%.l #1,%%d0\n"
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+ "bne%.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : : "a" (paddr), "r" (len),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA+CF_CACR_IVO)
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+ : "a0", "d0");
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+}
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+
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+/**
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+ * cf_cache_push - Push dirty cache out with no invalidate
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+ * @paddr: starting physical address
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+ * @len: number of bytes
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+ *
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+ * Push the any dirty lines starting at paddr for len bytes.
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+ * Those lines are not invalidated.
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+ */
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+static inline void cf_cache_push(unsigned long paddr, int len)
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+{
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+ /* number of lines */
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+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
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+ if (len == 0)
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+ return;
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+
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+ /* align on set boundary */
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+ paddr &= 0xfffffff0;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%d0\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "subq%.l #1,%%d0\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : : "a" (paddr), "r" (len),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
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+ : "a0", "d0");
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+}
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+
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+/**
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+ * cf_cache_flush - Push dirty cache out and invalidate
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+ * @paddr: starting physical address
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+ * @len: number of bytes
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+ *
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+ * Push the any dirty lines starting at paddr for len bytes and
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+ * invalidate those lines.
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+ */
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+static inline void cf_cache_flush(unsigned long paddr, int len)
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+{
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+ /* number of lines */
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+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
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+ if (len == 0)
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+ return;
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+
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+ /* align on set boundary */
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+ paddr &= 0xfffffff0;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%d0\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "subq%.l #1,%%d0\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : : "a" (paddr), "r" (len),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA)
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+ : "a0", "d0");
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+}
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+
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+/**
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+ * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
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+ * @vstart - starting virtual address
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+ * @vend: ending virtual address
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+ *
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+ * Push the any dirty data/instr lines starting at paddr for len bytes and
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+ * invalidate those lines.
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+ */
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+static inline void cf_cache_flush_range(unsigned long vstart, unsigned long vend)
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+{
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+ int len;
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+
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+ /* align on set boundary */
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+ vstart &= 0xfffffff0;
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+ vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
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+ len = vend - vstart;
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+ if (len == 0)
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+ return;
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+ vstart = __pa(vstart);
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+ vend = vstart + len;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%a1\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "cmpa%.l %%a0,%%a1\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : /* no return */
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+ : "a" (vstart), "a" (vend),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA)
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+ : "a0", "a1", "d0");
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+}
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+
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+/**
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+ * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
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+ * @vstart - starting virtual address
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+ * @vend: ending virtual address
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+ *
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+ * Push the any dirty data lines starting at paddr for len bytes and
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+ * invalidate those lines.
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+ */
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+static inline void cf_dcache_flush_range(unsigned long vstart, unsigned long vend)
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+{
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+ /* align on set boundary */
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+ vstart &= 0xfffffff0;
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+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%a1\n"
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+ "1:\n"
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+ "cpushl %%dc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "cmpa%.l %%a0,%%a1\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : /* no return */
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+ : "a" (__pa(vstart)), "a" (__pa(vend)),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA)
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+ : "a0", "a1", "d0");
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+}
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+
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+/**
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+ * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
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+ * @vstart - starting virtual address
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+ * @vend: ending virtual address
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+ *
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+ * Push the any dirty instr lines starting at paddr for len bytes and
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+ * invalidate those lines. This should just be an invalidate since you
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+ * shouldn't be able to have dirty instruction cache.
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+ */
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+static inline void cf_icache_flush_range(unsigned long vstart, unsigned long vend)
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+{
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+ /* align on set boundary */
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+ vstart &= 0xfffffff0;
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+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
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+
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%a0\n"
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+ "move%.l %1,%%a1\n"
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+ "1:\n"
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+ "cpushl %%ic,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "cmpa%.l %%a0,%%a1\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : /* no return */
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+ : "a" (__pa(vstart)), "a" (__pa(vend)),
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+ "r" (shadow_cacr),
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+ "i" (CF_CACR_SPA)
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+ : "a0", "a1", "d0");
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+}
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+
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+/**
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+ * flush_cache_mm - Flush an mm_struct
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+ * @mm: mm_struct to flush
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+ */
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+static inline void flush_cache_mm(struct mm_struct *mm)
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+{
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+ if (mm == current->mm)
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+ flush_bcache();
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+}
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+
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+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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+
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+/**
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+ * flush_cache_range - Flush a cache range
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+ * @vma: vma struct
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+ * @start: Starting address
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+ * @end: Ending address
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+ *
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+ * flush_cache_range must be a macro to avoid a dependency on
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+ * linux/mm.h which includes this file.
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+ */
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+static inline void flush_cache_range(struct vm_area_struct *vma,
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+ unsigned long start, unsigned long end)
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+{
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+ if (vma->vm_mm == current->mm)
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+ cf_cache_flush_range(start, end);
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+}
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+
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+/**
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+ * flush_cache_page - Flush a page of the cache
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+ * @vma: vma struct
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+ * @vmaddr:
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+ * @pfn: page numer
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+ *
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+ * flush_cache_page must be a macro to avoid a dependency on
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+ * linux/mm.h which includes this file.
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+ */
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+static inline void flush_cache_page(struct vm_area_struct *vma,
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+ unsigned long vmaddr, unsigned long pfn)
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+{
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+ if (vma->vm_mm == current->mm)
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+ cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
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+}
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+
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+/**
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+ * __flush_page_to_ram - Push a page out of the cache
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+ * @vaddr: Virtual address at start of page
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+ *
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+ * Push the page at kernel virtual address *vaddr* and clear
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+ * the icache.
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+ */
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+static inline void __flush_page_to_ram(void *vaddr)
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+{
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+ asm volatile("nop\n"
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+ "move%.l %2,%%d0\n"
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+ "or%.l %3,%%d0\n"
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+ "movec %%d0,%%cacr\n"
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+ "move%.l %0,%%d0\n"
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+ "and%.l #0xfffffff0,%%d0\n"
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+ "move%.l %%d0,%%a0\n"
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+ "move%.l %1,%%d0\n"
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+ "1:\n"
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+ "cpushl %%bc,(%%a0)\n"
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+ "lea 0x10(%%a0),%%a0\n"
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+ "subq%.l #1,%%d0\n"
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+ "bne.b 1b\n"
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+ "movec %2,%%cacr\n"
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+ : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
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+ "r" (shadow_cacr), "i" (CF_CACR_SPA)
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+ : "a0", "d0");
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+}
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+
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+/*
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+ * Various defines for the kernel.
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+ */
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+
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+extern void cache_clear(unsigned long paddr, int len);
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+extern void cache_push(unsigned long paddr, int len);
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+extern void flush_icache_range(unsigned long address, unsigned long endaddr);
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+
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+#define flush_cache_all() flush_bcache()
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+#define flush_cache_vmap(start, end) flush_bcache()
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+#define flush_cache_vunmap(start, end) flush_bcache()
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+
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+#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend)
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+#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
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+#define flush_dcache_mmap_lock(mapping) do { } while (0)
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+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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+
|
|
+#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
|
|
+
|
|
+/**
|
|
+ * copy_to_user_page - Copy memory to user page
|
|
+ */
|
|
+static inline void copy_to_user_page(struct vm_area_struct *vma,
|
|
+ struct page *page, unsigned long vaddr,
|
|
+ void *dst, void *src, int len)
|
|
+{
|
|
+ memcpy(dst, src, len);
|
|
+ cf_cache_flush(page_to_phys(page), PAGE_SIZE);
|
|
+}
|
|
+
|
|
+/**
|
|
+ * copy_from_user_page - Copy memory from user page
|
|
+ */
|
|
+static inline void copy_from_user_page(struct vm_area_struct *vma,
|
|
+ struct page *page, unsigned long vaddr,
|
|
+ void *dst, void *src, int len)
|
|
+{
|
|
+ cf_cache_flush(page_to_phys(page), PAGE_SIZE);
|
|
+ memcpy(dst, src, len);
|
|
+}
|
|
+
|
|
+#endif /* M68K_CF_5445x_CACHEFLUSH_H */
|
|
--- /dev/null
|
|
+++ b/include/asm-m68k/cf_548x_cacheflush.h
|
|
@@ -0,0 +1,259 @@
|
|
+/*
|
|
+ * include/asm-m68k/cf_548x_cacheflush.h - Coldfire 547x/548x Cache
|
|
+ *
|
|
+ * Based on include/asm-m68k/cacheflush.h
|
|
+ *
|
|
+ * Coldfire pieces by:
|
|
+ * Kurt Mahan kmahan@freescale.com
|
|
+ *
|
|
+ * Copyright Freescale Semiconductor, Inc. 2007, 2008
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ */
|
|
+#ifndef M68K_CF_548x_CACHEFLUSH_H
|
|
+#define M68K_CF_548x_CACHEFLUSH_H
|
|
+
|
|
+#include <asm/cfcache.h>
|
|
+/*
|
|
+ * Cache handling functions
|
|
+ */
|
|
+
|
|
+#define flush_icache() \
|
|
+({ \
|
|
+ unsigned long set; \
|
|
+ unsigned long start_set; \
|
|
+ unsigned long end_set; \
|
|
+ \
|
|
+ start_set = 0; \
|
|
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
+ \
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
+ asm volatile("cpushl %%ic,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%ic,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%ic,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
|
|
+ } \
|
|
+})
|
|
+
|
|
+#define flush_dcache() \
|
|
+({ \
|
|
+ unsigned long set; \
|
|
+ unsigned long start_set; \
|
|
+ unsigned long end_set; \
|
|
+ \
|
|
+ start_set = 0; \
|
|
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
+ \
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
+ asm volatile("cpushl %%dc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%dc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%dc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
|
|
+ } \
|
|
+})
|
|
+
|
|
+#define flush_bcache() \
|
|
+({ \
|
|
+ unsigned long set; \
|
|
+ unsigned long start_set; \
|
|
+ unsigned long end_set; \
|
|
+ \
|
|
+ start_set = 0; \
|
|
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
+ \
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
+ asm volatile("cpushl %%bc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%bc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%bc,(%0)\n" \
|
|
+ "\taddq%.l #1,%0\n" \
|
|
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
|
|
+ } \
|
|
+})
|
|
+
|
|
+/*
|
|
+ * invalidate the cache for the specified memory range.
|
|
+ * It starts at the physical address specified for
|
|
+ * the given number of bytes.
|
|
+ */
|
|
+extern void cache_clear(unsigned long paddr, int len);
|
|
+/*
|
|
+ * push any dirty cache in the specified memory range.
|
|
+ * It starts at the physical address specified for
|
|
+ * the given number of bytes.
|
|
+ */
|
|
+extern void cache_push(unsigned long paddr, int len);
|
|
+
|
|
+/*
|
|
+ * push and invalidate pages in the specified user virtual
|
|
+ * memory range.
|
|
+ */
|
|
+extern void cache_push_v(unsigned long vaddr, int len);
|
|
+
|
|
+/* This is needed whenever the virtual mapping of the current
|
|
+ process changes. */
|
|
+
|
|
+/**
|
|
+ * flush_cache_mm - Flush an mm_struct
|
|
+ * @mm: mm_struct to flush
|
|
+ */
|
|
+static inline void flush_cache_mm(struct mm_struct *mm)
|
|
+{
|
|
+ if (mm == current->mm)
|
|
+ flush_bcache();
|
|
+}
|
|
+
|
|
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
|
+
|
|
+#define flush_cache_all() flush_bcache()
|
|
+
|
|
+/**
|
|
+ * flush_cache_range - Flush a cache range
|
|
+ * @vma: vma struct
|
|
+ * @start: Starting address
|
|
+ * @end: Ending address
|
|
+ *
|
|
+ * flush_cache_range must be a macro to avoid a dependency on
|
|
+ * linux/mm.h which includes this file.
|
|
+ */
|
|
+static inline void flush_cache_range(struct vm_area_struct *vma,
|
|
+ unsigned long start, unsigned long end)
|
|
+{
|
|
+ if (vma->vm_mm == current->mm)
|
|
+ flush_bcache();
|
|
+// cf_cache_flush_range(start, end);
|
|
+}
|
|
+
|
|
+/**
|
|
+ * flush_cache_page - Flush a page of the cache
|
|
+ * @vma: vma struct
|
|
+ * @vmaddr:
|
|
+ * @pfn: page numer
|
|
+ *
|
|
+ * flush_cache_page must be a macro to avoid a dependency on
|
|
+ * linux/mm.h which includes this file.
|
|
+ */
|
|
+static inline void flush_cache_page(struct vm_area_struct *vma,
|
|
+ unsigned long vmaddr, unsigned long pfn)
|
|
+{
|
|
+ if (vma->vm_mm == current->mm)
|
|
+ flush_bcache();
|
|
+// cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
|
|
+}
|
|
+
|
|
+/* Push the page at kernel virtual address and clear the icache */
|
|
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
|
|
+#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
|
|
+extern inline void __flush_page_to_ram(void *address)
|
|
+{
|
|
+ unsigned long set;
|
|
+ unsigned long start_set;
|
|
+ unsigned long end_set;
|
|
+ unsigned long addr = (unsigned long) address;
|
|
+
|
|
+ addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
|
|
+
|
|
+ start_set = addr & _ICACHE_SET_MASK;
|
|
+ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
|
|
+
|
|
+ if (start_set > end_set) {
|
|
+ /* from the begining to the lowest address */
|
|
+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
|
|
+ asm volatile("cpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
|
|
+ }
|
|
+ /* next loop will finish the cache ie pass the hole */
|
|
+ end_set = LAST_ICACHE_ADDR;
|
|
+ }
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
|
|
+ asm volatile("cpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
|
|
+ }
|
|
+}
|
|
+
|
|
+/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
|
|
+#define flush_dcache_page(page) \
|
|
+ __flush_page_to_ram((void *) page_address(page))
|
|
+#define flush_icache_page(vma,pg) \
|
|
+ __flush_page_to_ram((void *) page_address(pg))
|
|
+#define flush_icache_user_range(adr,len) do { } while (0)
|
|
+/* NL */
|
|
+#define flush_icache_user_page(vma,page,addr,len) do { } while (0)
|
|
+
|
|
+/* Push n pages at kernel virtual address and clear the icache */
|
|
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
|
|
+extern inline void flush_icache_range (unsigned long address,
|
|
+ unsigned long endaddr)
|
|
+{
|
|
+ unsigned long set;
|
|
+ unsigned long start_set;
|
|
+ unsigned long end_set;
|
|
+
|
|
+ start_set = address & _ICACHE_SET_MASK;
|
|
+ end_set = endaddr & _ICACHE_SET_MASK;
|
|
+
|
|
+ if (start_set > end_set) {
|
|
+ /* from the begining to the lowest address */
|
|
+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
|
|
+ asm volatile("cpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
|
|
+ }
|
|
+ /* next loop will finish the cache ie pass the hole */
|
|
+ end_set = LAST_ICACHE_ADDR;
|
|
+ }
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
|
|
+ asm volatile("cpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
|
|
+ }
|
|
+}
|
|
+
|
|
+static inline void copy_to_user_page(struct vm_area_struct *vma,
|
|
+ struct page *page, unsigned long vaddr,
|
|
+ void *dst, void *src, int len)
|
|
+{
|
|
+ memcpy(dst, src, len);
|
|
+ flush_icache_user_page(vma, page, vaddr, len);
|
|
+}
|
|
+static inline void copy_from_user_page(struct vm_area_struct *vma,
|
|
+ struct page *page, unsigned long vaddr,
|
|
+ void *dst, void *src, int len)
|
|
+{
|
|
+ memcpy(dst, src, len);
|
|
+}
|
|
+
|
|
+#define flush_cache_vmap(start, end) flush_cache_all()
|
|
+#define flush_cache_vunmap(start, end) flush_cache_all()
|
|
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
|
|
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
|
|
+
|
|
+#endif /* M68K_CF_548x_CACHEFLUSH_H */
|
|
--- a/include/asm-m68k/cf_cacheflush.h
|
|
+++ b/include/asm-m68k/cf_cacheflush.h
|
|
@@ -1,244 +1,10 @@
|
|
#ifndef M68K_CF_CACHEFLUSH_H
|
|
#define M68K_CF_CACHEFLUSH_H
|
|
|
|
-#include <asm/cfcache.h>
|
|
-/*
|
|
- * Cache handling functions
|
|
- */
|
|
-
|
|
-#define flush_icache() \
|
|
-({ \
|
|
- unsigned long set; \
|
|
- unsigned long start_set; \
|
|
- unsigned long end_set; \
|
|
- \
|
|
- start_set = 0; \
|
|
- end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
- \
|
|
- for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
- asm volatile("cpushl %%ic,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%ic,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%ic,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
|
|
- } \
|
|
-})
|
|
-
|
|
-#define flush_dcache() \
|
|
-({ \
|
|
- unsigned long set; \
|
|
- unsigned long start_set; \
|
|
- unsigned long end_set; \
|
|
- \
|
|
- start_set = 0; \
|
|
- end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
- \
|
|
- for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
- asm volatile("cpushl %%dc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%dc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%dc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
|
|
- } \
|
|
-})
|
|
-
|
|
-#define flush_bcache() \
|
|
-({ \
|
|
- unsigned long set; \
|
|
- unsigned long start_set; \
|
|
- unsigned long end_set; \
|
|
- \
|
|
- start_set = 0; \
|
|
- end_set = (unsigned long)LAST_DCACHE_ADDR; \
|
|
- \
|
|
- for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
|
|
- asm volatile("cpushl %%bc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%bc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%bc,(%0)\n" \
|
|
- "\taddq%.l #1,%0\n" \
|
|
- "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
|
|
- } \
|
|
-})
|
|
-
|
|
-/*
|
|
- * invalidate the cache for the specified memory range.
|
|
- * It starts at the physical address specified for
|
|
- * the given number of bytes.
|
|
- */
|
|
-extern void cache_clear(unsigned long paddr, int len);
|
|
-/*
|
|
- * push any dirty cache in the specified memory range.
|
|
- * It starts at the physical address specified for
|
|
- * the given number of bytes.
|
|
- */
|
|
-extern void cache_push(unsigned long paddr, int len);
|
|
-
|
|
-/*
|
|
- * push and invalidate pages in the specified user virtual
|
|
- * memory range.
|
|
- */
|
|
-extern void cache_push_v(unsigned long vaddr, int len);
|
|
-
|
|
-/* This is needed whenever the virtual mapping of the current
|
|
- process changes. */
|
|
-
|
|
-/**
|
|
- * flush_cache_mm - Flush an mm_struct
|
|
- * @mm: mm_struct to flush
|
|
- */
|
|
-static inline void flush_cache_mm(struct mm_struct *mm)
|
|
-{
|
|
- if (mm == current->mm)
|
|
- flush_bcache();
|
|
-}
|
|
-
|
|
-#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
|
-
|
|
-#define flush_cache_all() flush_bcache()
|
|
-
|
|
-/**
|
|
- * flush_cache_range - Flush a cache range
|
|
- * @vma: vma struct
|
|
- * @start: Starting address
|
|
- * @end: Ending address
|
|
- *
|
|
- * flush_cache_range must be a macro to avoid a dependency on
|
|
- * linux/mm.h which includes this file.
|
|
- */
|
|
-static inline void flush_cache_range(struct vm_area_struct *vma,
|
|
- unsigned long start, unsigned long end)
|
|
-{
|
|
- if (vma->vm_mm == current->mm)
|
|
- flush_bcache();
|
|
-// cf_cache_flush_range(start, end);
|
|
-}
|
|
-
|
|
-/**
|
|
- * flush_cache_page - Flush a page of the cache
|
|
- * @vma: vma struct
|
|
- * @vmaddr:
|
|
- * @pfn: page numer
|
|
- *
|
|
- * flush_cache_page must be a macro to avoid a dependency on
|
|
- * linux/mm.h which includes this file.
|
|
- */
|
|
-static inline void flush_cache_page(struct vm_area_struct *vma,
|
|
- unsigned long vmaddr, unsigned long pfn)
|
|
-{
|
|
- if (vma->vm_mm == current->mm)
|
|
- flush_bcache();
|
|
-// cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
|
|
-}
|
|
-
|
|
-/* Push the page at kernel virtual address and clear the icache */
|
|
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
|
|
-#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
|
|
-extern inline void __flush_page_to_ram(void *address)
|
|
-{
|
|
- unsigned long set;
|
|
- unsigned long start_set;
|
|
- unsigned long end_set;
|
|
- unsigned long addr = (unsigned long) address;
|
|
-
|
|
- addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
|
|
-
|
|
- start_set = addr & _ICACHE_SET_MASK;
|
|
- end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
|
|
-
|
|
- if (start_set > end_set) {
|
|
- /* from the begining to the lowest address */
|
|
- for (set = 0; set <= end_set; set += (0x10 - 3)) {
|
|
- asm volatile("cpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
|
|
- }
|
|
- /* next loop will finish the cache ie pass the hole */
|
|
- end_set = LAST_ICACHE_ADDR;
|
|
- }
|
|
- for (set = start_set; set <= end_set; set += (0x10 - 3)) {
|
|
- asm volatile("cpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
|
|
- }
|
|
-}
|
|
-
|
|
-/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
|
|
-#define flush_dcache_page(page) \
|
|
- __flush_page_to_ram((void *) page_address(page))
|
|
-#define flush_icache_page(vma,pg) \
|
|
- __flush_page_to_ram((void *) page_address(pg))
|
|
-#define flush_icache_user_range(adr,len) do { } while (0)
|
|
-/* NL */
|
|
-#define flush_icache_user_page(vma,page,addr,len) do { } while (0)
|
|
-
|
|
-/* Push n pages at kernel virtual address and clear the icache */
|
|
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
|
|
-extern inline void flush_icache_range (unsigned long address,
|
|
- unsigned long endaddr)
|
|
-{
|
|
- unsigned long set;
|
|
- unsigned long start_set;
|
|
- unsigned long end_set;
|
|
-
|
|
- start_set = address & _ICACHE_SET_MASK;
|
|
- end_set = endaddr & _ICACHE_SET_MASK;
|
|
-
|
|
- if (start_set > end_set) {
|
|
- /* from the begining to the lowest address */
|
|
- for (set = 0; set <= end_set; set += (0x10 - 3)) {
|
|
- asm volatile("cpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
|
|
- }
|
|
- /* next loop will finish the cache ie pass the hole */
|
|
- end_set = LAST_ICACHE_ADDR;
|
|
- }
|
|
- for (set = start_set; set <= end_set; set += (0x10 - 3)) {
|
|
- asm volatile("cpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)\n"
|
|
- "\taddq%.l #1,%0\n"
|
|
- "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
|
|
- }
|
|
-}
|
|
-
|
|
-static inline void copy_to_user_page(struct vm_area_struct *vma,
|
|
- struct page *page, unsigned long vaddr,
|
|
- void *dst, void *src, int len)
|
|
-{
|
|
- memcpy(dst, src, len);
|
|
- flush_icache_user_page(vma, page, vaddr, len);
|
|
-}
|
|
-static inline void copy_from_user_page(struct vm_area_struct *vma,
|
|
- struct page *page, unsigned long vaddr,
|
|
- void *dst, void *src, int len)
|
|
-{
|
|
- memcpy(dst, src, len);
|
|
-}
|
|
-
|
|
-#define flush_cache_vmap(start, end) flush_cache_all()
|
|
-#define flush_cache_vunmap(start, end) flush_cache_all()
|
|
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
|
|
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
|
|
+#ifdef CONFIG_M5445X
|
|
+#include "cf_5445x_cacheflush.h"
|
|
+#else
|
|
+#include "cf_548x_cacheflush.h"
|
|
+#endif
|
|
|
|
#endif /* M68K_CF_CACHEFLUSH_H */
|