mirror of https://github.com/hak5/openwrt.git
91 lines
1.3 KiB
Plaintext
91 lines
1.3 KiB
Plaintext
/dts-v1/;
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
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model = "Ralink MT7620A evaluation board";
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gpio-keys-polled {
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compatible = "gpio-keys";
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poll-interval = <20>;
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wps {
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label = "wps";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_1>;
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};
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};
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};
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&gpio0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <1000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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ðernet {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&ephy_pins>;
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mediatek,portmap = "llllw";
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};
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&gsw {
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mediatek,port4 = "ephy";
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};
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&sdhci {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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