mirror of https://github.com/hak5/openwrt.git
90 lines
2.5 KiB
Diff
90 lines
2.5 KiB
Diff
From 016f1f659cf70cc78e72e12a2130d8f3e1a6e0d3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 13 Apr 2013 15:13:40 +0200
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Subject: [PATCH 123/137] MIPS: ralink: add memory definition for RT305x
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Populate struct soc_info with the data that describes our RAM window.
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As memory detection fails on RT5350 we read the amount of available memory
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from the system controller.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5180/
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 6 ++++
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arch/mips/ralink/rt305x.c | 45 ++++++++++++++++++++++++++++
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2 files changed, 51 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
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#define RT3352_RSTCTRL_UDEV BIT(25)
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#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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+#define RT305X_SDRAM_BASE 0x00000000
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+#define RT305X_MEM_SIZE_MIN 2
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+#define RT305X_MEM_SIZE_MAX 64
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+#define RT3352_MEM_SIZE_MIN 2
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+#define RT3352_MEM_SIZE_MAX 256
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+
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#endif
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
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.wdt_reset = rt305x_wdt_reset,
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};
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+static unsigned long rt5350_get_mem_size(void)
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+{
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+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
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+ unsigned long ret;
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+ u32 t;
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+
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+ t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
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+ t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
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+ RT5350_SYSCFG0_DRAM_SIZE_MASK;
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+
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+ switch (t) {
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+ case RT5350_SYSCFG0_DRAM_SIZE_2M:
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+ ret = 2;
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+ break;
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+ case RT5350_SYSCFG0_DRAM_SIZE_8M:
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+ ret = 8;
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+ break;
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+ case RT5350_SYSCFG0_DRAM_SIZE_16M:
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+ ret = 16;
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+ break;
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+ case RT5350_SYSCFG0_DRAM_SIZE_32M:
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+ ret = 32;
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+ break;
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+ case RT5350_SYSCFG0_DRAM_SIZE_64M:
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+ ret = 64;
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+ break;
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+ default:
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+ panic("rt5350: invalid DRAM size: %u", t);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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@@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_inf
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name,
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
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(id & CHIP_ID_REV_MASK));
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+
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+ soc_info->mem_base = RT305X_SDRAM_BASE;
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+ if (soc_is_rt5350()) {
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+ soc_info->mem_size = rt5350_get_mem_size();
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+ } else if (soc_is_rt305x() || soc_is_rt3350()) {
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+ soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
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+ soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
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+ } else if (soc_is_rt3352()) {
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+ soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
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+ soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
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+ }
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}
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