mirror of https://github.com/hak5/openwrt.git
62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Wed, 7 Sep 2016 16:44:28 +0530
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Subject: PCI: qcom: Force GEN1 support
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Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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drivers/pci/host/pcie-qcom.c | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/drivers/pci/host/pcie-qcom.c
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -90,6 +90,8 @@
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#define PCIE20_PARF_CONFIG_BITS 0x50
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#define PHY_RX0_EQ(x) (x << 24)
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+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
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+
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struct qcom_pcie_resources_v0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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@@ -138,6 +140,7 @@ struct qcom_pcie {
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struct phy *phy;
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struct gpio_desc *reset;
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struct qcom_pcie_ops *ops;
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+ uint32_t force_gen1;
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};
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#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
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@@ -477,6 +480,11 @@ static int qcom_pcie_init_v0(struct qcom
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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+ if (pcie->force_gen1) {
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+ writel_relaxed((readl_relaxed(
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+ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
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+ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
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+ }
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qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
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qcom_pcie_prog_viewport_mem2_outbound(pcie);
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@@ -666,6 +674,8 @@ static int qcom_pcie_probe(struct platfo
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struct qcom_pcie *pcie;
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struct pcie_port *pp;
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int ret;
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+ uint32_t force_gen1 = 0;
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+ struct device_node *np = pdev->dev.of_node;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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@@ -678,6 +688,9 @@ static int qcom_pcie_probe(struct platfo
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if (IS_ERR(pcie->reset))
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return PTR_ERR(pcie->reset);
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+ of_property_read_u32(np, "force_gen1", &force_gen1);
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+ pcie->force_gen1 = force_gen1;
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+
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
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pcie->parf = devm_ioremap_resource(dev, res);
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if (IS_ERR(pcie->parf))
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