mirror of https://github.com/hak5/openwrt.git
205 lines
5.5 KiB
Diff
205 lines
5.5 KiB
Diff
From 4ca0e8a959569852b520b607d39ce6ceeeb0f518 Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 15 Jun 2015 19:20:49 +0800
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Subject: [PATCH 36/76] mmc: mediatek: Add PM support for MMC driver
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Add PM support for Mediatek MMC driver
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Save/restore registers when PM
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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---
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drivers/mmc/host/mtk-sd.c | 89 +++++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 86 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -22,6 +22,8 @@
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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+#include <linux/pm.h>
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+#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spinlock.h>
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@@ -212,6 +214,7 @@
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#define MSDC_ASYNC_FLAG (0x1 << 1)
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#define MSDC_MMAP_FLAG (0x1 << 2)
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+#define MTK_MMC_AUTOSUSPEND_DELAY 50
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#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
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#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
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@@ -254,6 +257,15 @@ struct msdc_dma {
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dma_addr_t bd_addr; /* the physical address of bd array */
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};
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+struct msdc_save_para {
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+ u32 msdc_cfg;
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+ u32 iocon;
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+ u32 sdc_cfg;
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+ u32 pad_tune;
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+ u32 patch_bit0;
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+ u32 patch_bit1;
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+};
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+
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struct msdc_host {
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struct device *dev;
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struct mmc_host *mmc; /* mmc structure */
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@@ -286,6 +298,7 @@ struct msdc_host {
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u32 sclk; /* SD/MS bus clock frequency */
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bool ddr;
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bool vqmmc_enabled;
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+ struct msdc_save_para save_para; /* used when gate HCLK */
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};
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static void sdr_set_bits(void __iomem *reg, u32 bs)
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@@ -677,6 +690,9 @@ static void msdc_request_done(struct msd
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if (mrq->data)
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msdc_unprepare_data(host, mrq);
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mmc_request_done(host->mmc, mrq);
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+
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+ pm_runtime_mark_last_busy(host->dev);
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+ pm_runtime_put_autosuspend(host->dev);
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}
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/* returns true if command is fully handled; returns false otherwise */
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@@ -831,6 +847,8 @@ static void msdc_ops_request(struct mmc_
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WARN_ON(host->mrq);
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host->mrq = mrq;
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+ pm_runtime_get_sync(host->dev);
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+
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if (mrq->data)
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msdc_prepare_data(host, mrq);
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@@ -1145,6 +1163,8 @@ static void msdc_ops_set_ios(struct mmc_
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int ret;
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u32 ddr = 0;
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+ pm_runtime_get_sync(host->dev);
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+
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if (ios->timing == MMC_TIMING_UHS_DDR50 ||
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ios->timing == MMC_TIMING_MMC_DDR52)
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ddr = 1;
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@@ -1159,7 +1179,7 @@ static void msdc_ops_set_ios(struct mmc_
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ios->vdd);
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if (ret) {
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dev_err(host->dev, "Failed to set vmmc power!\n");
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- return;
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+ goto end;
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}
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}
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break;
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@@ -1187,6 +1207,10 @@ static void msdc_ops_set_ios(struct mmc_
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if (host->mclk != ios->clock || host->ddr != ddr)
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msdc_set_mclk(host, ddr, ios->clock);
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+
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+end:
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+ pm_runtime_mark_last_busy(host->dev);
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+ pm_runtime_put_autosuspend(host->dev);
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}
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static struct mmc_host_ops mt_msdc_ops = {
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@@ -1310,12 +1334,18 @@ static int msdc_drv_probe(struct platfor
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if (ret)
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goto release;
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+ pm_runtime_set_active(host->dev);
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+ pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
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+ pm_runtime_use_autosuspend(host->dev);
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+ pm_runtime_enable(host->dev);
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ret = mmc_add_host(mmc);
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+
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if (ret)
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- goto release;
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+ goto end;
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return 0;
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-
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+end:
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+ pm_runtime_disable(host->dev);
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release:
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platform_set_drvdata(pdev, NULL);
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msdc_deinit_hw(host);
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@@ -1343,11 +1373,15 @@ static int msdc_drv_remove(struct platfo
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mmc = platform_get_drvdata(pdev);
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host = mmc_priv(mmc);
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+ pm_runtime_get_sync(host->dev);
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+
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platform_set_drvdata(pdev, NULL);
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mmc_remove_host(host->mmc);
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msdc_deinit_hw(host);
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msdc_gate_clock(host);
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+ pm_runtime_disable(host->dev);
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+ pm_runtime_put_noidle(host->dev);
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dma_free_coherent(&pdev->dev,
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sizeof(struct mt_gpdma_desc),
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host->dma.gpd, host->dma.gpd_addr);
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@@ -1359,6 +1393,54 @@ static int msdc_drv_remove(struct platfo
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return 0;
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}
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+#ifdef CONFIG_PM
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+static void msdc_save_reg(struct msdc_host *host)
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+{
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+ host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
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+ host->save_para.iocon = readl(host->base + MSDC_IOCON);
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+ host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
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+ host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
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+ host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
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+ host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
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+}
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+
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+static void msdc_restore_reg(struct msdc_host *host)
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+{
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+ writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
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+ writel(host->save_para.iocon, host->base + MSDC_IOCON);
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+ writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
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+ writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
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+ writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
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+ writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
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+}
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+
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+static int msdc_runtime_suspend(struct device *dev)
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+{
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+ struct mmc_host *mmc = dev_get_drvdata(dev);
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+ struct msdc_host *host = mmc_priv(mmc);
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+
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+ msdc_save_reg(host);
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+ msdc_gate_clock(host);
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+ return 0;
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+}
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+
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+static int msdc_runtime_resume(struct device *dev)
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+{
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+ struct mmc_host *mmc = dev_get_drvdata(dev);
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+ struct msdc_host *host = mmc_priv(mmc);
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+
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+ msdc_ungate_clock(host);
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+ msdc_restore_reg(host);
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+ return 0;
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+}
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+#endif
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+
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+static const struct dev_pm_ops msdc_dev_pm_ops = {
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+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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+ pm_runtime_force_resume)
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+ SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
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+};
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+
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static const struct of_device_id msdc_of_ids[] = {
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{ .compatible = "mediatek,mt8135-mmc", },
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{}
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@@ -1370,6 +1452,7 @@ static struct platform_driver mt_msdc_dr
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.driver = {
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.name = "mtk-msdc",
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.of_match_table = msdc_of_ids,
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+ .pm = &msdc_dev_pm_ops,
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},
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};
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