mirror of https://github.com/hak5/openwrt.git
130 lines
6.0 KiB
C
130 lines
6.0 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_ppe_danube.h
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** PROJECT : UEIP
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** MODULES : ATM (ADSL)
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**
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** DATE : 1 AUG 2005
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM Driver (PPE Registers)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 4 AUG 2005 Xu Liang Initiate Version
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** 23 OCT 2006 Xu Liang Add GPL header.
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** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
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*******************************************************************************/
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#ifndef IFXMIPS_ATM_PPE_DANUBE_H
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#define IFXMIPS_ATM_PPE_DANUBE_H
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#include <lantiq.h>
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/*
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* FPI Configuration Bus Register and Memory Address Mapping
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*/
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#define IFX_PPE (KSEG1 | 0x1E180000)
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#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
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#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
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#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
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#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
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#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
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#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
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#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
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#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
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#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
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#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
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#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
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#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
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#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))
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#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
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#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))
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#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
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/*
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* DWORD-Length of Memory Blocks
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*/
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#define PP32_DEBUG_REG_DWLEN 0x0030
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#define PPM_INT_REG_DWLEN 0x0010
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#define PP32_INTERNAL_RES_DWLEN 0x00C0
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#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)
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#define PPE_REG_DWLEN 0x1000
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#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)
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#define PPM_INT_UNIT_DWLEN 0x0100
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#define PPM_TIMER0_DWLEN 0x0100
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#define PPM_TASK_IND_REG_DWLEN 0x0100
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#define PPS_BRK_DWLEN 0x0100
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#define PPM_TIMER1_DWLEN 0x0100
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#define SB_RAM0_DWLEN 0x0400
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#define SB_RAM1_DWLEN 0x0800
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#define SB_RAM2_DWLEN 0x0A00
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#define SB_RAM3_DWLEN 0x0400
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#define QSB_CONF_REG_DWLEN 0x0100
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/*
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* PP32 to FPI Address Mapping
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*/
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#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \
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(((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \
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(((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \
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(((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \
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0))
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/*
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* PP32 Debug Control Register
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*/
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#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000)
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#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0)
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#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0)
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#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0)
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#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001)
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#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002)
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#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))
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#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))
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#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))
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#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i))
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#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i))
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#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080)
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#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081)
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#define PP32_DBG_REG_BASE(tsk, i) PP32_DEBUG_REG_ADDR(0, 0x0100 + (tsk) * 16 + (i))
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/*
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* EMA Registers
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*/
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#define EMA_CMDCFG PPE_REG_ADDR(0x0A00)
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#define EMA_DATACFG PPE_REG_ADDR(0x0A01)
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#define EMA_CMDCNT PPE_REG_ADDR(0x0A02)
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#define EMA_DATACNT PPE_REG_ADDR(0x0A03)
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#define EMA_ISR PPE_REG_ADDR(0x0A04)
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#define EMA_IER PPE_REG_ADDR(0x0A05)
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#define EMA_CFG PPE_REG_ADDR(0x0A06)
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#define EMA_SUBID PPE_REG_ADDR(0x0A07)
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#define EMA_ALIGNMENT 4
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/*
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* Mailbox IGU1 Interrupt
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*/
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#define PPE_MAILBOX_IGU1_INT LTQ_PPE_MBOX_INT
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#endif // IFXMIPS_ATM_PPE_DANUBE_H
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