mirror of https://github.com/hak5/openwrt.git
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* ADM5120 NAND interface definitions
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*
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* This header file defines the hardware registers of the ADM5120 SoC
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* built-in NAND interface.
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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*
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* NAND interface routines was based on a driver for Linux 2.6.19+ which
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* was derived from the driver for Linux 2.4.xx published by Mikrotik for
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* their RouterBoard 1xx and 5xx series boards.
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* Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
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* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
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* The original Mikrotik code seems not to have a license.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#ifndef _ADM5120_NAND_H_
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#define _ADM5120_NAND_H_
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#include <linux/types.h>
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#include <linux/io.h>
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#include <adm5120_defs.h>
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#include <adm5120_switch.h>
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/* NAND control registers */
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#define NAND_REG_DATA 0x0 /* data register */
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#define NAND_REG_SET_CEn 0x1 /* CE# low */
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#define NAND_REG_CLR_CEn 0x2 /* CE# high */
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#define NAND_REG_CLR_CLE 0x3 /* CLE low */
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#define NAND_REG_SET_CLE 0x4 /* CLE high */
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#define NAND_REG_CLR_ALE 0x5 /* ALE low */
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#define NAND_REG_SET_ALE 0x6 /* ALE high */
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#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */
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#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */
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#define NAND_REG_SET_WPn 0x9 /* WP# low */
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#define NAND_REG_CLR_WPn 0xA /* WP# high */
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#define NAND_REG_STATUS 0xB /* Status register */
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#define ADM5120_NAND_STATUS_READY 0x80
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#define NAND_READ_REG(r) \
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readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
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#define NAND_WRITE_REG(r, v) \
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writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
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/*-------------------------------------------------------------------------*/
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static inline void adm5120_nand_enable(void)
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{
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SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE);
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SW_WRITE_REG(BOOT_DONE, 1);
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}
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static inline void adm5120_nand_set_wpn(unsigned int set)
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{
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NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
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}
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static inline void adm5120_nand_set_spn(unsigned int set)
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{
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NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
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}
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static inline void adm5120_nand_set_cle(unsigned int set)
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{
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NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
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}
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static inline void adm5120_nand_set_ale(unsigned int set)
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{
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NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
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}
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static inline void adm5120_nand_set_cen(unsigned int set)
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{
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NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
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}
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static inline u8 adm5120_nand_get_status(void)
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{
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return NAND_READ_REG(NAND_REG_STATUS);
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}
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#endif /* _ADM5120_NAND_H_ */
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