mirror of https://github.com/hak5/openwrt.git
243 lines
4.1 KiB
Plaintext
243 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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#include "qcom-ipq4019.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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model = "EZVIZ CS-W3-WD1200G EUP";
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compatible = "ezviz,cs-w3-wd1200g-eup";
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aliases {
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led-boot = &led_status_green;
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led-failsafe = &led_status_red;
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led-running = &led_status_blue;
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led-upgrade = &led_status_green;
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};
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soc {
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rng@22000 {
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status = "okay";
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};
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mdio@90000 {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
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reset-delay-us = <5000>;
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};
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ess-psgmii@98000 {
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status = "okay";
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};
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tcsr@1949000 {
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compatible = "qcom,tcsr";
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reg = <0x1949000 0x100>;
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
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};
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tcsr@194b000 {
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compatible = "qcom,tcsr";
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reg = <0x194b000 0x100>;
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qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
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};
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ess_tcsr@1953000 {
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compatible = "qcom,tcsr";
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reg = <0x1953000 0x1000>;
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
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};
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tcsr@1957000 {
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compatible = "qcom,tcsr";
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reg = <0x1957000 0x100>;
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
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};
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crypto@8e3a000 {
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status = "okay";
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};
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watchdog@b017000 {
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status = "okay";
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};
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ess-switch@c000000 {
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status = "okay";
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};
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edma@c080000 {
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status = "okay";
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status_red: status_red {
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label = "cs-w3-wd1200g-eup:red:status";
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gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
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};
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led_status_green: status_green {
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label = "cs-w3-wd1200g-eup:green:status";
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gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
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};
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led_status_blue: status_blue {
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label = "cs-w3-wd1200g-eup:blue:status";
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gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&tlmm {
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio60", "gpio61";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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mdio_pins: mdio_pinmux {
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mux_1 {
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pins = "gpio53";
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function = "mdio";
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bias-pull-up;
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};
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mux_2 {
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pins = "gpio52";
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function = "mdc";
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bias-pull-up;
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};
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};
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spi_0_pins: spi_0_pinmux {
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pin {
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function = "blsp_spi0";
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pins = "gpio55", "gpio56", "gpio57";
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drive-strength = <12>;
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bias-disable;
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};
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pin_cs {
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function = "gpio";
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pins = "gpio54";
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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};
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&blsp_dma {
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status = "okay";
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};
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition0@0 {
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label = "SBL1";
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reg = <0x00000000 0x00040000>;
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read-only;
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};
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partition1@40000 {
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label = "MIBIB";
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reg = <0x00040000 0x00020000>;
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read-only;
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};
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partition2@60000 {
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label = "QSEE";
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reg = <0x00060000 0x00060000>;
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read-only;
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};
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partition3@c0000 {
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label = "CDT";
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reg = <0x000c0000 0x00010000>;
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read-only;
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};
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partition4@d0000 {
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label = "DDRPARAMS";
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reg = <0x000d0000 0x00010000>;
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read-only;
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};
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partition5@E0000 {
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label = "APPSBLENV";
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reg = <0x000e0000 0x00010000>;
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read-only;
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};
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partition6@F0000 {
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label = "APPSBL";
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reg = <0x000f0000 0x00080000>;
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read-only;
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};
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partition7@170000 {
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label = "ART";
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reg = <0x00170000 0x00010000>;
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read-only;
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};
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partition9@580000 {
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compatible = "denx,fit";
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label = "firmware";
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reg = <0x00180000 0x00e80000>;
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};
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};
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};
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};
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&blsp1_uart1 {
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pinctrl-0 = <&serial_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&cryptobam {
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status = "okay";
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};
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&wifi0 {
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status = "okay";
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qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
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};
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&wifi1 {
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status = "okay";
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qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
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};
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