mirror of https://github.com/hak5/openwrt.git
364 lines
9.8 KiB
Diff
364 lines
9.8 KiB
Diff
--- a/arch/mips/ath25/Kconfig
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+++ b/arch/mips/ath25/Kconfig
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@@ -7,6 +7,7 @@ config SOC_AR5312
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config SOC_AR2315
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bool "Atheros AR2315+ SoC support"
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depends on ATH25
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+ select GPIO_AR2315
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default y
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config PCI_AR2315
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--- a/arch/mips/ath25/ar2315.c
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+++ b/arch/mips/ath25/ar2315.c
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@@ -21,6 +21,8 @@
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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+#include <linux/delay.h>
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+#include <linux/gpio.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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@@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void)
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ar2315_misc_irq_domain = domain;
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}
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+static struct resource ar2315_gpio_res[] = {
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+ {
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+ .name = "ar2315-gpio",
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+ .flags = IORESOURCE_MEM,
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+ .start = AR2315_RST_BASE + AR2315_GPIO,
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+ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
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+ },
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+ {
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+ .name = "ar2315-gpio",
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .name = "ar2315-gpio-irq-base",
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+ .flags = IORESOURCE_IRQ,
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+ .start = AR231X_GPIO_IRQ_BASE,
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+ .end = AR231X_GPIO_IRQ_BASE,
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+ }
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+};
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+
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+static struct platform_device ar2315_gpio = {
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+ .id = -1,
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+ .name = "ar2315-gpio",
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+ .resource = ar2315_gpio_res,
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+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
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+};
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+
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void __init ar2315_init_devices(void)
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{
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/* Find board configuration */
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ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
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+ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
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+ AR2315_MISC_IRQ_GPIO);
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+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
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+ platform_device_register(&ar2315_gpio);
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+
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ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
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}
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@@ -187,8 +220,8 @@ static void ar2315_restart(char *command
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/* Cold reset does not work on the AR2315/6, use the GPIO reset bits
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* a workaround. Give it some time to attempt a gpio based hardware
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* reset (atheros reference design workaround) */
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-
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- /* TODO: implement the GPIO reset workaround */
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+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
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+ mdelay(100);
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/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
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* workaround. Attempt to jump to the mips reset location -
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -141,6 +141,13 @@ config GPIO_BRCMSTB
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help
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Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
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+config GPIO_AR2315
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+ bool "AR2315 SoC GPIO support"
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+ default y if SOC_AR2315
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+ depends on SOC_AR2315
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+ help
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+ Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
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+
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config GPIO_AR5312
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bool "AR5312 SoC GPIO support"
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default y if SOC_AR5312
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp55
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obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
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obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
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obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
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+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
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obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
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obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
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obj-$(CONFIG_ATH79) += gpio-ath79.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-ar2315.c
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@@ -0,0 +1,233 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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+ * Copyright (C) 2006 FON Technology, SL.
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+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>
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+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/platform_device.h>
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+#include <linux/gpio.h>
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+#include <linux/irq.h>
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+
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+#define DRIVER_NAME "ar2315-gpio"
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+
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+#define AR2315_GPIO_DI 0x0000
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+#define AR2315_GPIO_DO 0x0008
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+#define AR2315_GPIO_DIR 0x0010
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+#define AR2315_GPIO_INT 0x0018
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+
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+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
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+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
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+#define AR2315_GPIO_DIR_I(x) (0) /* input */
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+
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+#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
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+#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
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+#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
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+
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+#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
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+#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
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+#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
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+#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
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+
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+#define AR2315_GPIO_NUM 22
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+
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+static u32 ar2315_gpio_intmask;
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+static u32 ar2315_gpio_intval;
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+static unsigned ar2315_gpio_irq_base;
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+static void __iomem *ar2315_mem;
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+
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+static inline u32 ar2315_gpio_reg_read(unsigned reg)
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+{
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+ return __raw_readl(ar2315_mem + reg);
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+}
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+
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+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
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+{
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+ __raw_writel(val, ar2315_mem + reg);
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+}
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+
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+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
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+{
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+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
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+}
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+
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+static void ar2315_gpio_irq_handler(struct irq_desc *desc)
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+{
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+ u32 pend;
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+ int bit = -1;
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+
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+ /* only do one gpio interrupt at a time */
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+ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
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+ pend ^= ar2315_gpio_intval;
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+ pend &= ar2315_gpio_intmask;
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+
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+ if (pend) {
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+ bit = fls(pend) - 1;
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+ pend &= ~(1 << bit);
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+ ar2315_gpio_intval ^= (1 << bit);
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+ }
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+
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+ /* Enable interrupt with edge detection */
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+ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
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+ AR2315_GPIO_DIR_I(bit))
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+ return;
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+
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+ if (bit >= 0)
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+ generic_handle_irq(ar2315_gpio_irq_base + bit);
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+}
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+
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+static void ar2315_gpio_int_setup(unsigned gpio, int trig)
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+{
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+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
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+
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+ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
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+ reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
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+ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
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+}
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+
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+static void ar2315_gpio_irq_unmask(struct irq_data *d)
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+{
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+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
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+ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
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+
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+ /* Enable interrupt with edge detection */
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+ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
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+ return;
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+
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+ ar2315_gpio_intmask |= (1 << gpio);
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+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
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+}
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+
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+static void ar2315_gpio_irq_mask(struct irq_data *d)
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+{
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+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
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+
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+ /* Disable interrupt */
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+ ar2315_gpio_intmask &= ~(1 << gpio);
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+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
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+}
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+
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+static struct irq_chip ar2315_gpio_irq_chip = {
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+ .name = DRIVER_NAME,
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+ .irq_unmask = ar2315_gpio_irq_unmask,
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+ .irq_mask = ar2315_gpio_irq_mask,
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+};
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+
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+static void ar2315_gpio_irq_init(unsigned irq)
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+{
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+ unsigned i;
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+
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+ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
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+ for (i = 0; i < AR2315_GPIO_NUM; i++) {
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+ unsigned _irq = ar2315_gpio_irq_base + i;
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+
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+ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
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+ handle_level_irq);
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+ }
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+ irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
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+}
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+
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+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
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+}
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+
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+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
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+{
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+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
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+
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+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
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+ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
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+}
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+
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+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
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+{
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+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
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+ return 0;
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+}
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+
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+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
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+{
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+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
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+ ar2315_gpio_set_val(chip, gpio, val);
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+ return 0;
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+}
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+
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+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return ar2315_gpio_irq_base + gpio;
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+}
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+
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+static struct gpio_chip ar2315_gpio_chip = {
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+ .label = DRIVER_NAME,
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+ .direction_input = ar2315_gpio_dir_in,
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+ .direction_output = ar2315_gpio_dir_out,
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+ .set = ar2315_gpio_set_val,
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+ .get = ar2315_gpio_get_val,
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+ .to_irq = ar2315_gpio_to_irq,
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+ .base = 0,
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+ .ngpio = AR2315_GPIO_NUM,
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+};
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+
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+static int ar2315_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct resource *res;
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+ unsigned irq;
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+ int ret;
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+
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+ if (ar2315_mem)
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+ return -EBUSY;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
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+ "ar2315-gpio-irq-base");
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+ if (!res) {
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+ dev_err(dev, "not found GPIO IRQ base\n");
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+ return -ENXIO;
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+ }
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+ ar2315_gpio_irq_base = res->start;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
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+ if (!res) {
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+ dev_err(dev, "not found IRQ number\n");
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+ return -ENXIO;
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+ }
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+ irq = res->start;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
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+ ar2315_mem = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(ar2315_mem))
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+ return PTR_ERR(ar2315_mem);
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+
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+ ar2315_gpio_chip.dev = dev;
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+ ret = gpiochip_add(&ar2315_gpio_chip);
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+ if (ret) {
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+ dev_err(dev, "failed to add gpiochip\n");
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+ return ret;
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+ }
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+
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+ ar2315_gpio_irq_init(irq);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver ar2315_gpio_driver = {
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+ .probe = ar2315_gpio_probe,
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+ .driver = {
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+ .name = DRIVER_NAME,
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+ .owner = THIS_MODULE,
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+ }
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+};
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+
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+static int __init ar2315_gpio_init(void)
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+{
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+ return platform_driver_register(&ar2315_gpio_driver);
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+}
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+subsys_initcall(ar2315_gpio_init);
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--- a/arch/mips/ath25/devices.h
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+++ b/arch/mips/ath25/devices.h
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@@ -3,6 +3,11 @@
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#include <linux/cpu.h>
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+#define AR231X_GPIO_IRQ_BASE 0x30
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+
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+/* GPIO number for AR2315/16 reset issue workaround */
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+#define AR2315_RESET_GPIO 5
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+
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#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
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#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
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--- a/arch/mips/ath25/ar2315_regs.h
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+++ b/arch/mips/ath25/ar2315_regs.h
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@@ -315,6 +315,9 @@
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#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
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#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
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+/* GPIO MMR base address */
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+#define AR2315_GPIO 0x0088
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+
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/*
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* Local Bus Interface Registers
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*/
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