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openwrt/target/linux/ath79/patches-4.14/0017-MIPS-ath79-add-support...

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From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
From: Weijie Gao <hackpascal@gmail.com>
Date: Tue, 6 Mar 2018 08:48:31 +0100
Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
This patch adds soc support for QCA9561 and TP9343.
TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
The qca956x_wmac has not yet been supported by ath9k.
tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
---
arch/mips/ath79/Kconfig | 2 +-
arch/mips/ath79/clock.c | 96 ++++++++++++++++++++++++++++++++
arch/mips/ath79/common.c | 4 ++
arch/mips/ath79/dev-common.c | 7 ++-
arch/mips/ath79/early_printk.c | 2 +
arch/mips/ath79/irq.c | 87 ++++++++++++++++++++++++++++-
arch/mips/ath79/pci.c | 12 ++++
arch/mips/ath79/setup.c | 17 +++++-
arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
9 files changed, 245 insertions(+), 4 deletions(-)
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -119,7 +119,7 @@ config ATH79_DEV_USB
def_bool n
config ATH79_DEV_WMAC
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
def_bool n
endif
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(v
clk_add_alias("uart", NULL, "ref", NULL);
}
+static void __init qca956x_clocks_init(void)
+{
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+ unsigned long ddr_rate;
+ unsigned long ahb_rate;
+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
+ u32 cpu_pll, ddr_pll;
+ u32 bootstrap;
+
+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = 40 * 1000 * 1000;
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
+
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
+
+ cpu_pll = nint * ref_rate / ref_div;
+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
+ cpu_pll /= (1 << out_div);
+
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
+
+ ddr_pll = nint * ref_rate / ref_div;
+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
+ ddr_pll /= (1 << out_div);
+
+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+ cpu_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
+ cpu_rate = ddr_pll / (postdiv + 1);
+ else
+ cpu_rate = cpu_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+ ddr_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
+ ddr_rate = cpu_pll / (postdiv + 1);
+ else
+ ddr_rate = ddr_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+ ahb_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+ ahb_rate = ddr_pll / (postdiv + 1);
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+ ath79_add_sys_clkdev("ref", ref_rate);
+ ath79_add_sys_clkdev("cpu", cpu_rate);
+ ath79_add_sys_clkdev("ddr", ddr_rate);
+ ath79_add_sys_clkdev("ahb", ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+}
+
void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
@@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
qca953x_clocks_init();
else if (soc_is_qca955x())
qca955x_clocks_init();
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ qca956x_clocks_init();
else
BUG();
}
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
else
panic("Reset register not defined for this SOC");
@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
else
panic("Reset register not defined for this SOC");
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
soc_is_ar913x() ||
soc_is_ar934x() ||
soc_is_qca953x() ||
- soc_is_qca955x()) {
+ soc_is_qca955x() ||
+ soc_is_qca956x() ||
+ soc_is_tp9343()) {
ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
@@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
} else if (soc_is_qca955x()) {
ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
ath79_gpio_pdata.oe_inverted = 1;
+ } else if (soc_is_qca956x() || soc_is_tp9343()) {
+ ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
+ ath79_gpio_pdata.oe_inverted = 1;
} else {
BUG();
}
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -120,6 +120,8 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558:
+ case REV_ID_MAJOR_TP9343:
+ case REV_ID_MAJOR_QCA956X:
_prom_putchar = prom_putchar_ar71xx;
break;
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
}
+static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
+{
+ u32 status;
+
+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
+ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
+
+ if (status == 0) {
+ spurious_interrupt();
+ return;
+ }
+
+ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
+ /* TODO: flush DDR? */
+ generic_handle_irq(ATH79_IP2_IRQ(0));
+ }
+
+ if (status & QCA956X_EXT_INT_WMAC_ALL) {
+ /* TODO: flsuh DDR? */
+ generic_handle_irq(ATH79_IP2_IRQ(1));
+ }
+}
+
+static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
+{
+ u32 status;
+
+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
+ status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
+ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
+
+ if (status == 0) {
+ spurious_interrupt();
+ return;
+ }
+
+ if (status & QCA956X_EXT_INT_USB1) {
+ /* TODO: flush DDR? */
+ generic_handle_irq(ATH79_IP3_IRQ(0));
+ }
+
+ if (status & QCA956X_EXT_INT_USB2) {
+ /* TODO: flush DDR? */
+ generic_handle_irq(ATH79_IP3_IRQ(1));
+ }
+
+ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
+ /* TODO: flush DDR? */
+ generic_handle_irq(ATH79_IP3_IRQ(2));
+ }
+}
+
+static void qca956x_enable_timer_cb(void) {
+ u32 misc;
+
+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
+}
+
+static void qca956x_irq_init(void)
+{
+ int i;
+
+ for (i = ATH79_IP2_IRQ_BASE;
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
+
+ for (i = ATH79_IP3_IRQ_BASE;
+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
+
+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
+
+ /* QCA956x timer init workaround has to be applied right before setting
+ * up the clock. Else, there will be no jiffies */
+ late_time_init = &qca956x_enable_timer_cb;
+}
+
void __init arch_init_irq(void)
{
unsigned irq_wb_chan2 = -1;
@@ -183,7 +264,9 @@ void __init arch_init_irq(void)
soc_is_ar933x() ||
soc_is_ar934x() ||
soc_is_qca953x() ||
- soc_is_qca955x())
+ soc_is_qca955x() ||
+ soc_is_qca956x() ||
+ soc_is_tp9343())
misc_is_ar71xx = false;
else
BUG();
@@ -197,4 +280,6 @@ void __init arch_init_irq(void)
qca953x_irq_init();
else if (soc_is_qca955x())
qca955x_irq_init();
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ qca956x_irq_init();
}
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev
} else if (soc_is_qca955x()) {
ath79_pci_irq_map = qca955x_pci_irq_map;
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+ } else if (soc_is_qca956x()) {
+ ath79_pci_irq_map = qca956x_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
} else {
pr_crit("pci %s: invalid irq map\n",
pci_name((struct pci_dev *) dev));
@@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
QCA955X_PCI_MEM_SIZE,
1,
ATH79_IP3_IRQ(2));
+ } else if (soc_is_qca956x()) {
+ pdev = ath79_register_pci_ar724x(0,
+ QCA956X_PCI_CFG_BASE1,
+ QCA956X_PCI_CTRL_BASE1,
+ QCA956X_PCI_CRP_BASE1,
+ QCA956X_PCI_MEM_BASE1,
+ QCA956X_PCI_MEM_SIZE,
+ 1,
+ ATH79_IP3_IRQ(2));
} else {
/* No PCI support */
return -ENODEV;
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
rev = id & QCA955X_REV_ID_REVISION_MASK;
break;
+ case REV_ID_MAJOR_QCA956X:
+ ath79_soc = ATH79_SOC_QCA956X;
+ chip = "956X";
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_TP9343:
+ ath79_soc = ATH79_SOC_TP9343;
+ chip = "9343";
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+
default:
panic("ath79: unknown SoC, id:0x%08x", id);
}
@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
if (ver == 1)
ath79_soc_rev = rev;
- if (soc_is_qca953x() || soc_is_qca955x())
+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, ver, rev);
+ else if (soc_is_tp9343())
+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
+ chip, rev);
else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -35,6 +35,8 @@ enum ath79_soc_type {
ATH79_SOC_QCA9533,
ATH79_SOC_QCA9556,
ATH79_SOC_QCA9558,
+ ATH79_SOC_TP9343,
+ ATH79_SOC_QCA956X,
};
extern enum ath79_soc_type ath79_soc;
@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
return soc_is_qca9556() || soc_is_qca9558();
}
+static inline int soc_is_tp9343(void)
+{
+ return ath79_soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+ return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca9563(void)
+{
+ return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca956x(void)
+{
+ return soc_is_qca9561() || soc_is_qca9563();
+}
+
void ath79_ddr_wb_flush(unsigned int reg);
void ath79_ddr_set_pci_windows(void);
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