mirror of https://github.com/hak5/openwrt.git
58 lines
2.1 KiB
Diff
58 lines
2.1 KiB
Diff
From 6fe4f63b017c3c0a7caa73d01fab23874ca0ed97 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Thu, 4 Jul 2013 22:29:48 +0200
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Subject: [PATCH 10/17] bcma: add some more core names
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These cores were found on a BCM4708 (chipid 53010), this is a ARM SoC
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with two Cortex A9 cores.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/bcma/scan.c | 12 ++++++++++++
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include/linux/bcma/bcma.h | 12 ++++++++++++
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2 files changed, 24 insertions(+)
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--- a/drivers/bcma/scan.c
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+++ b/drivers/bcma/scan.c
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@@ -32,6 +32,18 @@ static const struct bcma_device_id_name
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{ BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
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{ BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
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{ BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
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+ { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
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+ { BCMA_CORE_DMA, "DMA" },
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+ { BCMA_CORE_SDIO3, "SDIO3" },
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+ { BCMA_CORE_USB20, "USB 2.0" },
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+ { BCMA_CORE_USB30, "USB 3.0" },
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+ { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
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+ { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
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+ { BCMA_CORE_ROM, "ROM" },
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+ { BCMA_CORE_NAND, "NAND flash controller" },
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+ { BCMA_CORE_QSPI, "SPI flash controller" },
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+ { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
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+ { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
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{ BCMA_CORE_AMEMC, "AMEMC (DDR)" },
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{ BCMA_CORE_ALTA, "ALTA (I2S)" },
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{ BCMA_CORE_INVALID, "Invalid" },
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -72,7 +72,19 @@ struct bcma_host_ops {
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/* Core-ID values. */
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#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
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#define BCMA_CORE_4706_CHIPCOMMON 0x500
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+#define BCMA_CORE_PCIEG2 0x501
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+#define BCMA_CORE_DMA 0x502
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+#define BCMA_CORE_SDIO3 0x503
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+#define BCMA_CORE_USB20 0x504
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+#define BCMA_CORE_USB30 0x505
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+#define BCMA_CORE_A9JTAG 0x506
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+#define BCMA_CORE_DDR23 0x507
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+#define BCMA_CORE_ROM 0x508
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+#define BCMA_CORE_NAND 0x509
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+#define BCMA_CORE_QSPI 0x50A
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+#define BCMA_CORE_CHIPCOMMON_B 0x50B /* ChipcommonB core */
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#define BCMA_CORE_4706_SOC_RAM 0x50E
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+#define BCMA_CORE_ARMCA9 0x510
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#define BCMA_CORE_4706_MAC_GBIT 0x52D
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#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
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#define BCMA_CORE_ALTA 0x534 /* I2S core */
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