mirror of https://github.com/hak5/openwrt.git
182 lines
5.1 KiB
C
182 lines
5.1 KiB
C
#ifndef __IDT_GPIO_H__
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#define __IDT_GPIO_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* GPIO register definition.
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*
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* File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Update :
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* $Log: gpio.h,v $
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* Revision 1.2 2002/06/06 18:34:04 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.1 2002/05/29 17:33:22 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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*
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******************************************************************************/
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enum
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{
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GPIO0_PhysicalAddress = 0x18050000,
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GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
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GPIO0_VirtualAddress = 0xb8050000,
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GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
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} ;
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typedef struct
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{
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u32 gpiofunc; /* GPIO Function Register
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* gpiofunc[x]==0 bit = gpio
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* func[x]==1 bit = altfunc
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*/
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u32 gpiocfg; /* GPIO Configuration Register
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* gpiocfg[x]==0 bit = input
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* gpiocfg[x]==1 bit = output
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*/
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u32 gpiod; /* GPIO Data Register
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* gpiod[x] read/write gpio pinX status
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*/
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u32 gpioilevel; /* GPIO Interrupt Status Register
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* interrupt level (see gpioistat)
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*/
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u32 gpioistat; /* Gpio Interrupt Status Register
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* istat[x] = (gpiod[x] == level[x])
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* cleared in ISR (STICKY bits)
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*/
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u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
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} volatile * GPIO_t ;
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typedef enum
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{
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GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
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GPIO_alt_v = 1, // gpiofunc use pin as alt.
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GPIO_input_v = 0, // gpiocfg use pin as input.
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GPIO_output_v = 1, // gpiocfg use pin as output.
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GPIO_pin0_b = 0,
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GPIO_pin0_m = 0x00000001,
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GPIO_pin1_b = 1,
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GPIO_pin1_m = 0x00000002,
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GPIO_pin2_b = 2,
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GPIO_pin2_m = 0x00000004,
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GPIO_pin3_b = 3,
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GPIO_pin3_m = 0x00000008,
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GPIO_pin4_b = 4,
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GPIO_pin4_m = 0x00000010,
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GPIO_pin5_b = 5,
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GPIO_pin5_m = 0x00000020,
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GPIO_pin6_b = 6,
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GPIO_pin6_m = 0x00000040,
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GPIO_pin7_b = 7,
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GPIO_pin7_m = 0x00000080,
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GPIO_pin8_b = 8,
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GPIO_pin8_m = 0x00000100,
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GPIO_pin9_b = 9,
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GPIO_pin9_m = 0x00000200,
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GPIO_pin10_b = 10,
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GPIO_pin10_m = 0x00000400,
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GPIO_pin11_b = 11,
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GPIO_pin11_m = 0x00000800,
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GPIO_pin12_b = 12,
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GPIO_pin12_m = 0x00001000,
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GPIO_pin13_b = 13,
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GPIO_pin13_m = 0x00002000,
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GPIO_pin14_b = 14,
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GPIO_pin14_m = 0x00004000,
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GPIO_pin15_b = 15,
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GPIO_pin15_m = 0x00008000,
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GPIO_pin16_b = 16,
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GPIO_pin16_m = 0x00010000,
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GPIO_pin17_b = 17,
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GPIO_pin17_m = 0x00020000,
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GPIO_pin18_b = 18,
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GPIO_pin18_m = 0x00040000,
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GPIO_pin19_b = 19,
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GPIO_pin19_m = 0x00080000,
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GPIO_pin20_b = 20,
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GPIO_pin20_m = 0x00100000,
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GPIO_pin21_b = 21,
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GPIO_pin21_m = 0x00200000,
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GPIO_pin22_b = 22,
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GPIO_pin22_m = 0x00400000,
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GPIO_pin23_b = 23,
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GPIO_pin23_m = 0x00800000,
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GPIO_pin24_b = 24,
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GPIO_pin24_m = 0x01000000,
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GPIO_pin25_b = 25,
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GPIO_pin25_m = 0x02000000,
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GPIO_pin26_b = 26,
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GPIO_pin26_m = 0x04000000,
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GPIO_pin27_b = 27,
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GPIO_pin27_m = 0x08000000,
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GPIO_pin28_b = 28,
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GPIO_pin28_m = 0x10000000,
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GPIO_pin29_b = 29,
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GPIO_pin29_m = 0x20000000,
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GPIO_pin30_b = 30,
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GPIO_pin30_m = 0x40000000,
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GPIO_pin31_b = 31,
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GPIO_pin31_m = 0x80000000,
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// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
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GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
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GPIO_u0sout_m = GPIO_pin0_m,
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GPIO_u0sout_cfg_v = GPIO_output_v,
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GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
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GPIO_u0sinp_m = GPIO_pin1_m,
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GPIO_u0sinp_cfg_v = GPIO_input_v,
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GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
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GPIO_u0rtsn_m = GPIO_pin2_m,
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GPIO_u0rtsn_cfg_v = GPIO_output_v,
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GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
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GPIO_u0ctsn_m = GPIO_pin3_m,
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GPIO_u0ctsn_cfg_v = GPIO_input_v,
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GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
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GPIO_maddr22_m = GPIO_pin4_m,
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GPIO_maddr22_cfg_v = GPIO_output_v,
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GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
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GPIO_maddr23_m = GPIO_pin5_m,
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GPIO_maddr23_cfg_v = GPIO_output_v,
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GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
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GPIO_maddr24_m = GPIO_pin6_m,
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GPIO_maddr24_cfg_v = GPIO_output_v,
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GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
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GPIO_maddr25_m = GPIO_pin7_m,
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GPIO_maddr25_cfg_v = GPIO_output_v,
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GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
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GPIO_cpu_m = GPIO_pin8_m,
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GPIO_cpu_cfg_v = GPIO_output_v,
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GPIO_afspare6_b = GPIO_pin9_b, // reserved.
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GPIO_afspare6_m = GPIO_pin9_m,
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GPIO_afspare6_cfg_v = GPIO_input_v,
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GPIO_afspare4_b = GPIO_pin10_b, // reserved.
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GPIO_afspare4_m = GPIO_pin10_m,
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GPIO_afspare4_cfg_v = GPIO_input_v,
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GPIO_afspare3_b = GPIO_pin11_b, // reserved.
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GPIO_afspare3_m = GPIO_pin11_m,
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GPIO_afspare3_cfg_v = GPIO_input_v,
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GPIO_afspare2_b = GPIO_pin12_b, // reserved.
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GPIO_afspare2_m = GPIO_pin12_m,
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GPIO_afspare2_cfg_v = GPIO_input_v,
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GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
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GPIO_pcimuintn_m = GPIO_pin13_m,
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GPIO_pcimuintn_cfg_v = GPIO_output_v,
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} GPIO_DEFS_t;
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#endif // __IDT_GPIO_H__
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