mirror of https://github.com/hak5/openwrt.git
525 lines
13 KiB
Diff
525 lines
13 KiB
Diff
From 7adbe9a88c33c6e362a10b109d963b5500a21f00 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 09:34:05 +0100
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Subject: [PATCH 25/53] pinctrl: ralink: add pinctrl driver
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/Kconfig | 2 +
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drivers/pinctrl/Kconfig | 5 +
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drivers/pinctrl/Makefile | 1 +
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drivers/pinctrl/pinctrl-rt2880.c | 474 ++++++++++++++++++++++++++++++++++++++
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4 files changed, 482 insertions(+)
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create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -628,6 +628,8 @@ config RALINK
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select CLKDEV_LOOKUP
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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+ select PINCTRL
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+ select PINCTRL_RT2880
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config SGI_IP22
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bool "SGI IP22 (Indy/Indigo2)"
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--- a/drivers/pinctrl/Kconfig
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+++ b/drivers/pinctrl/Kconfig
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@@ -143,6 +143,11 @@ config PINCTRL_LPC18XX
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help
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Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
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+config PINCTRL_RT2880
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+ bool
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+ depends on RALINK
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+ select PINMUX
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+
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config PINCTRL_FALCON
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bool
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depends on SOC_FALCON
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--- a/drivers/pinctrl/Makefile
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+++ b/drivers/pinctrl/Makefile
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@@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-
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obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
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obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
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obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
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+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
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obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_SIRF) += sirf/
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--- /dev/null
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+++ b/drivers/pinctrl/pinctrl-rt2880.c
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@@ -0,0 +1,472 @@
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+/*
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+ * linux/drivers/pinctrl/pinctrl-rt2880.c
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * publishhed by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/device.h>
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+#include <linux/io.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+#include <linux/of.h>
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+#include <linux/pinctrl/pinctrl.h>
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+#include <linux/pinctrl/pinconf.h>
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+#include <linux/pinctrl/pinmux.h>
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+#include <linux/pinctrl/consumer.h>
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+#include <linux/pinctrl/machine.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+#include <asm/mach-ralink/pinmux.h>
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+#include <asm/mach-ralink/mt7620.h>
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+
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+#include "core.h"
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+
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+#define SYSC_REG_GPIO_MODE 0x60
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+#define SYSC_REG_GPIO_MODE2 0x64
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+
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+struct rt2880_priv {
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+ struct device *dev;
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+
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+ struct pinctrl_pin_desc *pads;
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+ struct pinctrl_desc *desc;
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+
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+ struct rt2880_pmx_func **func;
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+ int func_count;
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+
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+ struct rt2880_pmx_group *groups;
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+ const char **group_names;
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+ int group_count;
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+
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+ uint8_t *gpio;
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+ int max_pins;
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+};
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+
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+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ return p->group_count;
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+}
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+
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+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
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+ unsigned group)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ if (group >= p->group_count)
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+ return NULL;
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+
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+ return p->group_names[group];
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+}
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+
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+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
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+ unsigned group,
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+ const unsigned **pins,
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+ unsigned *num_pins)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ if (group >= p->group_count)
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+ return -EINVAL;
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+
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+ *pins = p->groups[group].func[0].pins;
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+ *num_pins = p->groups[group].func[0].pin_count;
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+
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+ return 0;
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+}
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+
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+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
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+ struct pinctrl_map *map, unsigned num_maps)
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+{
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+ int i;
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+
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+ for (i = 0; i < num_maps; i++)
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+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
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+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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+ kfree(map[i].data.configs.configs);
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+ kfree(map);
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+}
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+
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+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
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+ struct seq_file *s,
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+ unsigned offset)
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+{
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+ seq_printf(s, "ralink pio");
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+}
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+
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+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
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+ struct device_node *np,
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+ struct pinctrl_map **map)
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+{
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+ const char *function;
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+ int func = of_property_read_string(np, "ralink,function", &function);
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+ int grps = of_property_count_strings(np, "ralink,group");
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+ int i;
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+
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+ if (func || !grps)
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+ return;
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+
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+ for (i = 0; i < grps; i++) {
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+ const char *group;
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+
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+ of_property_read_string_index(np, "ralink,group", i, &group);
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+
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+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
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+ (*map)->name = function;
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+ (*map)->data.mux.group = group;
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+ (*map)->data.mux.function = function;
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+ (*map)++;
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+ }
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+}
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+
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+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
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+ struct device_node *np_config,
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+ struct pinctrl_map **map,
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+ unsigned *num_maps)
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+{
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+ int max_maps = 0;
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+ struct pinctrl_map *tmp;
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+ struct device_node *np;
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+
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+ for_each_child_of_node(np_config, np) {
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+ int ret = of_property_count_strings(np, "ralink,group");
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+
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+ if (ret >= 0)
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+ max_maps += ret;
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+ }
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+
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+ if (!max_maps)
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+ return -EINVAL;
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+
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+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
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+ if (!*map)
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+ return -ENOMEM;
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+
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+ tmp = *map;
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+
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+ for_each_child_of_node(np_config, np)
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+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
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+ *num_maps = max_maps;
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+
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+ return 0;
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+}
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+
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+static const struct pinctrl_ops rt2880_pctrl_ops = {
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+ .get_groups_count = rt2880_get_group_count,
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+ .get_group_name = rt2880_get_group_name,
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+ .get_group_pins = rt2880_get_group_pins,
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+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
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+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
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+ .dt_free_map = rt2880_pinctrl_dt_free_map,
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+};
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+
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+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ return p->func_count;
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+}
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+
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+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
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+ unsigned func)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ return p->func[func]->name;
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+}
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+
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+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
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+ unsigned func,
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+ const char * const **groups,
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+ unsigned * const num_groups)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ if (p->func[func]->group_count == 1)
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+ *groups = &p->group_names[p->func[func]->groups[0]];
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+ else
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+ *groups = p->group_names;
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+
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+ *num_groups = p->func[func]->group_count;
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+
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+ return 0;
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+}
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+
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+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
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+ unsigned func,
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+ unsigned group)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+ u32 mode = 0;
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+ u32 reg = SYSC_REG_GPIO_MODE;
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+ int i;
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+ int shift;
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+
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+ /* dont allow double use */
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+ if (p->groups[group].enabled) {
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+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
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+ return -EBUSY;
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+ }
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+
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+ p->groups[group].enabled = 1;
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+ p->func[func]->enabled = 1;
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+
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+ shift = p->groups[group].shift;
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+ if (shift >= 32) {
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+ shift -= 32;
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+ reg = SYSC_REG_GPIO_MODE2;
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+ }
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+ mode = rt_sysc_r32(reg);
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+ mode &= ~(p->groups[group].mask << shift);
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+
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+ /* mark the pins as gpio */
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+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
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+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
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+
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+ /* function 0 is gpio and needs special handling */
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+ if (func == 0) {
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+ mode |= p->groups[group].gpio << shift;
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+ } else {
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+ for (i = 0; i < p->func[func]->pin_count; i++)
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+ p->gpio[p->func[func]->pins[i]] = 0;
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+ mode |= p->func[func]->value << shift;
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+ }
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+ rt_sysc_w32(mode, reg);
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+
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+ return 0;
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+}
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+
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+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
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+ struct pinctrl_gpio_range *range,
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+ unsigned pin)
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+{
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+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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+
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+ if (!p->gpio[pin]) {
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+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct pinmux_ops rt2880_pmx_group_ops = {
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+ .get_functions_count = rt2880_pmx_func_count,
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+ .get_function_name = rt2880_pmx_func_name,
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+ .get_function_groups = rt2880_pmx_group_get_groups,
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+ .set_mux = rt2880_pmx_group_enable,
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+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
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+};
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+
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+static struct pinctrl_desc rt2880_pctrl_desc = {
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+ .owner = THIS_MODULE,
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+ .name = "rt2880-pinmux",
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+ .pctlops = &rt2880_pctrl_ops,
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+ .pmxops = &rt2880_pmx_group_ops,
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+};
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+
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+static struct rt2880_pmx_func gpio_func = {
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+ .name = "gpio",
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+};
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+
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+static int rt2880_pinmux_index(struct rt2880_priv *p)
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+{
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+ struct rt2880_pmx_func **f;
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+ struct rt2880_pmx_group *mux = p->groups;
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+ int i, j, c = 0;
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+
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+ /* count the mux functions */
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+ while (mux->name) {
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+ p->group_count++;
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+ mux++;
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+ }
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+
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+ /* allocate the group names array needed by the gpio function */
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+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
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+ if (!p->group_names)
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+ return -1;
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+
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+ for (i = 0; i < p->group_count; i++) {
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+ p->group_names[i] = p->groups[i].name;
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+ p->func_count += p->groups[i].func_count;
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+ }
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+
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+ /* we have a dummy function[0] for gpio */
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+ p->func_count++;
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+
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+ /* allocate our function and group mapping index buffers */
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+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
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+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
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+ if (!f || !gpio_func.groups)
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+ return -1;
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+
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+ /* add a backpointer to the function so it knows its group */
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+ gpio_func.group_count = p->group_count;
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+ for (i = 0; i < gpio_func.group_count; i++)
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+ gpio_func.groups[i] = i;
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+
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+ f[c] = &gpio_func;
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+ c++;
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+
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+ /* add remaining functions */
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+ for (i = 0; i < p->group_count; i++) {
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+ for (j = 0; j < p->groups[i].func_count; j++) {
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+ f[c] = &p->groups[i].func[j];
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+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
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+ f[c]->groups[0] = i;
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+ f[c]->group_count = 1;
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+ c++;
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+ }
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+ }
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+ return 0;
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+}
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+
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+static int rt2880_pinmux_pins(struct rt2880_priv *p)
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+{
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+ int i, j;
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+
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+ /* loop over the functions and initialize the pins array. also work out the highest pin used */
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+ for (i = 0; i < p->func_count; i++) {
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+ int pin;
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+
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+ if (!p->func[i]->pin_count)
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+ continue;
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+
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+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
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+ for (j = 0; j < p->func[i]->pin_count; j++)
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+ p->func[i]->pins[j] = p->func[i]->pin_first + j;
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+
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+ pin = p->func[i]->pin_first + p->func[i]->pin_count;
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+ if (pin > p->max_pins)
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+ p->max_pins = pin;
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+ }
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+
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+ /* the buffer that tells us which pins are gpio */
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+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
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+ GFP_KERNEL);
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+ /* the pads needed to tell pinctrl about our pins */
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+ p->pads = devm_kzalloc(p->dev,
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+ sizeof(struct pinctrl_pin_desc) * p->max_pins,
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+ GFP_KERNEL);
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+ if (!p->pads || !p->gpio ) {
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+ dev_err(p->dev, "Failed to allocate gpio data\n");
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+ return -ENOMEM;
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+ }
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+
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+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
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+ for (i = 0; i < p->func_count; i++) {
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+ if (!p->func[i]->pin_count)
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+ continue;
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+
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+ for (j = 0; j < p->func[i]->pin_count; j++)
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+ p->gpio[p->func[i]->pins[j]] = 0;
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+ }
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+
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+ /* pin 0 is always a gpio */
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+ p->gpio[0] = 1;
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+
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+ /* set the pads */
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+ for (i = 0; i < p->max_pins; i++) {
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+ /* strlen("ioXY") + 1 = 5 */
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+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
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+
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+ if (!name) {
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+ dev_err(p->dev, "Failed to allocate pad name\n");
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+ return -ENOMEM;
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+ }
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+ snprintf(name, 5, "io%d", i);
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+ p->pads[i].number = i;
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+ p->pads[i].name = name;
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+ }
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+ p->desc->pins = p->pads;
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+ p->desc->npins = p->max_pins;
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+
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+ return 0;
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+}
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+
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+static int rt2880_pinmux_probe(struct platform_device *pdev)
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+{
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+ struct rt2880_priv *p;
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+ struct pinctrl_dev *dev;
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+ struct device_node *np;
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+
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+ if (!rt2880_pinmux_data)
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+ return -ENOSYS;
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+
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+ /* setup the private data */
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+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
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+ if (!p)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ p->dev = &pdev->dev;
|
|
+ p->desc = &rt2880_pctrl_desc;
|
|
+ p->groups = rt2880_pinmux_data;
|
|
+ platform_set_drvdata(pdev, p);
|
|
+
|
|
+ /* init the device */
|
|
+ if (rt2880_pinmux_index(p)) {
|
|
+ dev_err(&pdev->dev, "failed to load index\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ if (rt2880_pinmux_pins(p)) {
|
|
+ dev_err(&pdev->dev, "failed to load pins\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ dev = pinctrl_register(p->desc, &pdev->dev, p);
|
|
+ if (IS_ERR(dev))
|
|
+ return PTR_ERR(dev);
|
|
+
|
|
+ /* finalize by adding gpio ranges for enables gpio controllers */
|
|
+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
|
|
+ const __be32 *ngpio, *gpiobase;
|
|
+ struct pinctrl_gpio_range *range;
|
|
+ char *name;
|
|
+
|
|
+ if (!of_device_is_available(np))
|
|
+ continue;
|
|
+
|
|
+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
|
|
+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
|
|
+ if (!ngpio || !gpiobase) {
|
|
+ dev_err(&pdev->dev, "failed to load chip info\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
|
|
+ range->name = name = (char *) &range[1];
|
|
+ sprintf(name, "pio");
|
|
+ range->npins = __be32_to_cpu(*ngpio);
|
|
+ range->base = __be32_to_cpu(*gpiobase);
|
|
+ range->pin_base = range->base;
|
|
+ pinctrl_add_gpio_range(dev, range);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id rt2880_pinmux_match[] = {
|
|
+ { .compatible = "ralink,rt2880-pinmux" },
|
|
+ {},
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
|
|
+
|
|
+static struct platform_driver rt2880_pinmux_driver = {
|
|
+ .probe = rt2880_pinmux_probe,
|
|
+ .driver = {
|
|
+ .name = "rt2880-pinmux",
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = rt2880_pinmux_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init rt2880_pinmux_init(void)
|
|
+{
|
|
+ return platform_driver_register(&rt2880_pinmux_driver);
|
|
+}
|
|
+
|
|
+core_initcall_sync(rt2880_pinmux_init);
|