mirror of https://github.com/hak5/openwrt.git
112 lines
4.4 KiB
Diff
112 lines
4.4 KiB
Diff
From 6cc882cf38b62fce2a07640413b05b43b420c77a Mon Sep 17 00:00:00 2001
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From: Annaliese McDermond <nh6z@nh6z.net>
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Date: Wed, 20 Mar 2019 19:38:44 -0700
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Subject: [PATCH 398/806] ASoC: tlv320aic32x4: Properly Set Processing Blocks
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commit c95e3a4b96293403a427b5185e60fad28af51fdd upstream.
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Different processing blocks are required for different sampling
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rates and power parameters. Set the processing blocks based
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on this information.
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Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/codecs/tlv320aic32x4.c | 56 ++++++++++++++++++++------------
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1 file changed, 36 insertions(+), 20 deletions(-)
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--- a/sound/soc/codecs/tlv320aic32x4.c
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+++ b/sound/soc/codecs/tlv320aic32x4.c
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@@ -59,6 +59,8 @@ struct aic32x4_rate_divs {
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u8 nadc;
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u8 madc;
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u8 blck_N;
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+ u8 r_block;
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+ u8 p_block;
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};
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struct aic32x4_priv {
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@@ -307,34 +309,34 @@ static const struct snd_kcontrol_new aic
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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- {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
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- {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
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- {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
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+ {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},
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+ {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},
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+ {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},
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/* 11.025k rate */
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- {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
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- {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
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+ {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},
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+ {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},
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/* 16k rate */
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- {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
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- {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
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- {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
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+ {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},
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+ {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},
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+ {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},
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/* 22.05k rate */
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- {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
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- {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
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- {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
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+ {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},
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+ {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},
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+ {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},
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/* 32k rate */
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- {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
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- {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
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+ {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},
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+ {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},
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/* 44.1k rate */
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- {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
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- {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
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- {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
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+ {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},
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+ {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},
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+ {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},
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/* 48k rate */
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- {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
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- {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
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- {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
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+ {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},
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+ {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},
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+ {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},
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/* 96k rate */
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- {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
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+ {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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@@ -698,6 +700,18 @@ static int aic32x4_set_dai_fmt(struct sn
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return 0;
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}
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+static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
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+ u8 r_block, u8 p_block)
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+{
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+ if (r_block > 18 || p_block > 25)
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+ return -EINVAL;
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+
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+ snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
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+ snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
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+
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+ return 0;
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+}
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+
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static int aic32x4_setup_clocks(struct snd_soc_component *component,
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unsigned int sample_rate,
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unsigned int parent_rate)
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@@ -710,6 +724,8 @@ static int aic32x4_setup_clocks(struct s
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return i;
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}
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+ aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
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+
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/* MCLK as PLL_CLKIN */
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snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
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AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
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