mirror of https://github.com/hak5/openwrt.git
580 lines
18 KiB
Diff
580 lines
18 KiB
Diff
From 8d513c7a67cce0bf0ef312323753eccbd0f3f71a Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 20 Oct 2015 16:06:57 +0100
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Subject: [PATCH 281/423] drm/vc4: Add support for scaling of display planes.
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This implements a simple policy for choosing scaling modes
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(trapezoidal for decimation, PPF for magnification), and a single PPF
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filter (Mitchell/Netravali's recommendation).
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 21af94cf1a4c2d3450ab7fead58e6e2291ab92a9)
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 4 +
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drivers/gpu/drm/vc4/vc4_hvs.c | 84 +++++++++++++
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drivers/gpu/drm/vc4/vc4_plane.c | 253 +++++++++++++++++++++++++++++++++++++---
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drivers/gpu/drm/vc4/vc4_regs.h | 46 ++++++++
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4 files changed, 374 insertions(+), 13 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -156,7 +156,11 @@ struct vc4_hvs {
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* list. Units are dwords.
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*/
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struct drm_mm dlist_mm;
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+ /* Memory manager for the LBM memory used by HVS scaling. */
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+ struct drm_mm lbm_mm;
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spinlock_t mm_lock;
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+
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+ struct drm_mm_node mitchell_netravali_filter;
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};
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struct vc4_plane {
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -100,12 +100,76 @@ int vc4_hvs_debugfs_regs(struct seq_file
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}
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#endif
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+/* The filter kernel is composed of dwords each containing 3 9-bit
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+ * signed integers packed next to each other.
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+ */
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+#define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
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+#define VC4_PPF_FILTER_WORD(c0, c1, c2) \
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+ ((((c0) & 0x1ff) << 0) | \
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+ (((c1) & 0x1ff) << 9) | \
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+ (((c2) & 0x1ff) << 18))
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+
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+/* The whole filter kernel is arranged as the coefficients 0-16 going
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+ * up, then a pad, then 17-31 going down and reversed within the
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+ * dwords. This means that a linear phase kernel (where it's
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+ * symmetrical at the boundary between 15 and 16) has the last 5
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+ * dwords matching the first 5, but reversed.
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+ */
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+#define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
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+ c9, c10, c11, c12, c13, c14, c15) \
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+ {VC4_PPF_FILTER_WORD(c0, c1, c2), \
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+ VC4_PPF_FILTER_WORD(c3, c4, c5), \
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+ VC4_PPF_FILTER_WORD(c6, c7, c8), \
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+ VC4_PPF_FILTER_WORD(c9, c10, c11), \
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+ VC4_PPF_FILTER_WORD(c12, c13, c14), \
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+ VC4_PPF_FILTER_WORD(c15, c15, 0)}
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+
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+#define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
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+#define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
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+
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+/* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
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+ * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
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+ */
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+static const u32 mitchell_netravali_1_3_1_3_kernel[] =
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+ VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
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+ 50, 82, 119, 155, 187, 213, 227);
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+
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+static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
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+ struct drm_mm_node *space,
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+ const u32 *kernel)
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+{
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+ int ret, i;
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+ u32 __iomem *dst_kernel;
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+
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+ ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS, 1,
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+ 0);
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+ if (ret) {
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+ DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ dst_kernel = hvs->dlist + space->start;
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+
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+ for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
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+ if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
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+ writel(kernel[i], &dst_kernel[i]);
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+ else {
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+ writel(kernel[VC4_KERNEL_DWORDS - i - 1],
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+ &dst_kernel[i]);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = drm->dev_private;
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struct vc4_hvs *hvs = NULL;
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+ int ret;
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hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
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if (!hvs)
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@@ -130,6 +194,22 @@ static int vc4_hvs_bind(struct device *d
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HVS_BOOTLOADER_DLIST_END,
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(SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
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+ /* Set up the HVS LBM memory manager. We could have some more
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+ * complicated data structure that allowed reuse of LBM areas
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+ * between planes when they don't overlap on the screen, but
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+ * for now we just allocate globally.
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+ */
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+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
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+
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+ /* Upload filter kernels. We only have the one for now, so we
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+ * keep it around for the lifetime of the driver.
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+ */
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+ ret = vc4_hvs_upload_linear_kernel(hvs,
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+ &hvs->mitchell_netravali_filter,
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+ mitchell_netravali_1_3_1_3_kernel);
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+ if (ret)
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+ return ret;
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+
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vc4->hvs = hvs;
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return 0;
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}
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@@ -140,7 +220,11 @@ static void vc4_hvs_unbind(struct device
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = drm->dev_private;
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+ if (vc4->hvs->mitchell_netravali_filter.allocated)
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+ drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
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+
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drm_mm_takedown(&vc4->hvs->dlist_mm);
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+ drm_mm_takedown(&vc4->hvs->lbm_mm);
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vc4->hvs = NULL;
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}
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -24,6 +24,12 @@
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#include "drm_fb_cma_helper.h"
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#include "drm_plane_helper.h"
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+enum vc4_scaling_mode {
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+ VC4_SCALING_NONE,
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+ VC4_SCALING_TPZ,
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+ VC4_SCALING_PPF,
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+};
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+
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struct vc4_plane_state {
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struct drm_plane_state base;
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/* System memory copy of the display list for this element, computed
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@@ -47,13 +53,19 @@ struct vc4_plane_state {
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/* Clipped coordinates of the plane on the display. */
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int crtc_x, crtc_y, crtc_w, crtc_h;
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- /* Clipped size of the area scanned from in the FB. */
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- u32 src_w, src_h;
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+ /* Clipped area being scanned from in the FB. */
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+ u32 src_x, src_y, src_w, src_h;
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+
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+ enum vc4_scaling_mode x_scaling, y_scaling;
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+ bool is_unity;
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/* Offset to start scanning out from the start of the plane's
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* BO.
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*/
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u32 offset;
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+
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+ /* Our allocation in LBM for temporary storage during scaling. */
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+ struct drm_mm_node lbm;
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};
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static inline struct vc4_plane_state *
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@@ -106,6 +118,16 @@ static const struct hvs_format *vc4_get_
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return NULL;
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}
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+static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
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+{
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+ if (dst > src)
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+ return VC4_SCALING_PPF;
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+ else if (dst < src)
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+ return VC4_SCALING_TPZ;
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+ else
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+ return VC4_SCALING_NONE;
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+}
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+
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static bool plane_enabled(struct drm_plane_state *state)
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{
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return state->fb && state->crtc;
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@@ -122,6 +144,8 @@ static struct drm_plane_state *vc4_plane
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if (!vc4_state)
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return NULL;
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+ memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
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+
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__drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
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if (vc4_state->dlist) {
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@@ -141,8 +165,17 @@ static struct drm_plane_state *vc4_plane
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static void vc4_plane_destroy_state(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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+ struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+ if (vc4_state->lbm.allocated) {
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+ unsigned long irqflags;
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+
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+ spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
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+ drm_mm_remove_node(&vc4_state->lbm);
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+ spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
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+ }
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+
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kfree(vc4_state->dlist);
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__drm_atomic_helper_plane_destroy_state(plane, &vc4_state->base);
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kfree(state);
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@@ -181,23 +214,60 @@ static void vc4_dlist_write(struct vc4_p
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vc4_state->dlist[vc4_state->dlist_count++] = val;
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}
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+/* Returns the scl0/scl1 field based on whether the dimensions need to
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+ * be up/down/non-scaled.
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+ *
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+ * This is a replication of a table from the spec.
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+ */
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+static u32 vc4_get_scl_field(struct drm_plane_state *state)
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+{
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+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+
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+ switch (vc4_state->x_scaling << 2 | vc4_state->y_scaling) {
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+ case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
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+ return SCALER_CTL0_SCL_H_PPF_V_PPF;
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+ case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
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+ return SCALER_CTL0_SCL_H_TPZ_V_PPF;
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+ case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
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+ return SCALER_CTL0_SCL_H_PPF_V_TPZ;
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+ case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
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+ return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
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+ case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
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+ return SCALER_CTL0_SCL_H_PPF_V_NONE;
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+ case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
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+ return SCALER_CTL0_SCL_H_NONE_V_PPF;
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+ case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
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+ return SCALER_CTL0_SCL_H_NONE_V_TPZ;
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+ case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
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+ return SCALER_CTL0_SCL_H_TPZ_V_NONE;
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+ default:
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+ case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
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+ /* The unity case is independently handled by
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+ * SCALER_CTL0_UNITY.
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+ */
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+ return 0;
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+ }
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+}
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+
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static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
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{
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+ struct drm_plane *plane = state->plane;
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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struct drm_framebuffer *fb = state->fb;
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+ u32 subpixel_src_mask = (1 << 16) - 1;
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vc4_state->offset = fb->offsets[0];
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- if (state->crtc_w << 16 != state->src_w ||
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- state->crtc_h << 16 != state->src_h) {
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- /* We don't support scaling yet, which involves
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- * allocating the LBM memory for scaling temporary
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- * storage, and putting filter kernels in the HVS
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- * context.
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- */
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+ /* We don't support subpixel source positioning for scaling. */
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+ if ((state->src_x & subpixel_src_mask) ||
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+ (state->src_y & subpixel_src_mask) ||
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+ (state->src_w & subpixel_src_mask) ||
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+ (state->src_h & subpixel_src_mask)) {
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return -EINVAL;
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}
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+ vc4_state->src_x = state->src_x >> 16;
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+ vc4_state->src_y = state->src_y >> 16;
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vc4_state->src_w = state->src_w >> 16;
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vc4_state->src_h = state->src_h >> 16;
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@@ -206,6 +276,23 @@ static int vc4_plane_setup_clipping_and_
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vc4_state->crtc_w = state->crtc_w;
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vc4_state->crtc_h = state->crtc_h;
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+ vc4_state->x_scaling = vc4_get_scaling_mode(vc4_state->src_w,
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+ vc4_state->crtc_w);
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+ vc4_state->y_scaling = vc4_get_scaling_mode(vc4_state->src_h,
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+ vc4_state->crtc_h);
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+ vc4_state->is_unity = (vc4_state->x_scaling == VC4_SCALING_NONE &&
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+ vc4_state->y_scaling == VC4_SCALING_NONE);
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+
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+ /* No configuring scaling on the cursor plane, since it gets
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+ non-vblank-synced updates, and scaling requires requires
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+ LBM changes which have to be vblank-synced.
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+ */
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+ if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
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+ return -EINVAL;
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+
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+ /* Clamp the on-screen start x/y to 0. The hardware doesn't
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+ * support negative y, and negative x wastes bandwidth.
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+ */
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if (vc4_state->crtc_x < 0) {
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vc4_state->offset += (drm_format_plane_cpp(fb->pixel_format,
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0) *
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@@ -223,6 +310,87 @@ static int vc4_plane_setup_clipping_and_
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return 0;
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}
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+static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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+{
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+ u32 scale, recip;
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+
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+ scale = (1 << 16) * src / dst;
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+
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+ /* The specs note that while the reciprocal would be defined
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+ * as (1<<32)/scale, ~0 is close enough.
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+ */
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+ recip = ~0 / scale;
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+
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+ vc4_dlist_write(vc4_state,
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+ VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
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+ VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
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+ vc4_dlist_write(vc4_state,
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+ VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
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+}
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+
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+static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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+{
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+ u32 scale = (1 << 16) * src / dst;
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+
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+ vc4_dlist_write(vc4_state,
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+ SCALER_PPF_AGC |
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+ VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
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+ VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
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+}
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+
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+static u32 vc4_lbm_size(struct drm_plane_state *state)
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+{
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+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+ /* This is the worst case number. One of the two sizes will
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+ * be used depending on the scaling configuration.
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+ */
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+ u32 pix_per_line = max(vc4_state->src_w, (u32)vc4_state->crtc_w);
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+ u32 lbm;
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+
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+ if (vc4_state->is_unity)
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+ return 0;
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+ else if (vc4_state->y_scaling == VC4_SCALING_TPZ)
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+ lbm = pix_per_line * 8;
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+ else {
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+ /* In special cases, this multiplier might be 12. */
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+ lbm = pix_per_line * 16;
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+ }
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+
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+ lbm = roundup(lbm, 32);
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+
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+ return lbm;
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+}
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+
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+static void vc4_write_scaling_parameters(struct drm_plane_state *state)
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+{
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+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+
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+ /* Ch0 H-PPF Word 0: Scaling Parameters */
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+ if (vc4_state->x_scaling == VC4_SCALING_PPF) {
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+ vc4_write_ppf(vc4_state,
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+ vc4_state->src_w, vc4_state->crtc_w);
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+ }
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+
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+ /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
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+ if (vc4_state->y_scaling == VC4_SCALING_PPF) {
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+ vc4_write_ppf(vc4_state,
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+ vc4_state->src_h, vc4_state->crtc_h);
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+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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+ }
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+
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+ /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
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+ if (vc4_state->x_scaling == VC4_SCALING_TPZ) {
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+ vc4_write_tpz(vc4_state,
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+ vc4_state->src_w, vc4_state->crtc_w);
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+ }
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+
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+ /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
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+ if (vc4_state->y_scaling == VC4_SCALING_TPZ) {
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+ vc4_write_tpz(vc4_state,
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+ vc4_state->src_h, vc4_state->crtc_h);
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+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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+ }
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+}
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/* Writes out a full display list for an active plane to the plane's
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* private dlist state.
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@@ -230,22 +398,50 @@ static int vc4_plane_setup_clipping_and_
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static int vc4_plane_mode_set(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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+ struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
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u32 ctl0_offset = vc4_state->dlist_count;
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const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
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+ u32 scl;
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+ u32 lbm_size;
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+ unsigned long irqflags;
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int ret;
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ret = vc4_plane_setup_clipping_and_scaling(state);
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if (ret)
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return ret;
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+ /* Allocate the LBM memory that the HVS will use for temporary
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+ * storage due to our scaling/format conversion.
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+ */
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+ lbm_size = vc4_lbm_size(state);
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+ if (lbm_size) {
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+ if (!vc4_state->lbm.allocated) {
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+ spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
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+ ret = drm_mm_insert_node(&vc4->hvs->lbm_mm,
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+ &vc4_state->lbm,
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+ lbm_size, 32, 0);
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+ spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
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+ } else {
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+ WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
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+ }
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+ }
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+
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+ if (ret)
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+ return ret;
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+
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+ scl = vc4_get_scl_field(state);
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+
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+ /* Control word */
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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(format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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- SCALER_CTL0_UNITY);
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+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
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+ VC4_SET_FIELD(scl, SCALER_CTL0_SCL0) |
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+ VC4_SET_FIELD(scl, SCALER_CTL0_SCL1));
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/* Position Word 0: Image Positions and Alpha Value */
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vc4_state->pos0_offset = vc4_state->dlist_count;
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@@ -254,9 +450,14 @@ static int vc4_plane_mode_set(struct drm
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VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
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VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
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- /* Position Word 1: Scaled Image Dimensions.
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- * Skipped due to SCALER_CTL0_UNITY scaling.
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- */
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+ /* Position Word 1: Scaled Image Dimensions. */
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+ if (!vc4_state->is_unity) {
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+ vc4_dlist_write(vc4_state,
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+ VC4_SET_FIELD(vc4_state->crtc_w,
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+ SCALER_POS1_SCL_WIDTH) |
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+ VC4_SET_FIELD(vc4_state->crtc_h,
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+ SCALER_POS1_SCL_HEIGHT));
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+ }
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/* Position Word 2: Source Image Size, Alpha Mode */
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vc4_state->pos2_offset = vc4_state->dlist_count;
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@@ -282,6 +483,32 @@ static int vc4_plane_mode_set(struct drm
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH));
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+ if (!vc4_state->is_unity) {
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+ /* LBM Base Address. */
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+ if (vc4_state->y_scaling != VC4_SCALING_NONE)
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+ vc4_dlist_write(vc4_state, vc4_state->lbm.start);
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+
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+ vc4_write_scaling_parameters(state);
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+
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+ /* If any PPF setup was done, then all the kernel
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+ * pointers get uploaded.
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+ */
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+ if (vc4_state->x_scaling == VC4_SCALING_PPF ||
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+ vc4_state->y_scaling == VC4_SCALING_PPF) {
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+ u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
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+ SCALER_PPF_KERNEL_OFFSET);
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+
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+ /* HPPF plane 0 */
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+ vc4_dlist_write(vc4_state, kernel);
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+ /* VPPF plane 0 */
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+ vc4_dlist_write(vc4_state, kernel);
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+ /* HPPF plane 1 */
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+ vc4_dlist_write(vc4_state, kernel);
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+ /* VPPF plane 1 */
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+ vc4_dlist_write(vc4_state, kernel);
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+ }
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+ }
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+
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vc4_state->dlist[ctl0_offset] |=
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VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -536,6 +536,21 @@ enum hvs_pixel_format {
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#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
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#define SCALER_CTL0_ORDER_SHIFT 13
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+#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
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+#define SCALER_CTL0_SCL1_SHIFT 8
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+
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+#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
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+#define SCALER_CTL0_SCL0_SHIFT 5
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+
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+#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
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+#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
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+#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
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+#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
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+#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
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+#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
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+#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
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+#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
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+
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/* Set to indicate no scaling. */
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#define SCALER_CTL0_UNITY BIT(4)
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@@ -551,6 +566,12 @@ enum hvs_pixel_format {
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#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
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#define SCALER_POS0_START_X_SHIFT 0
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+#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
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+#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
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+
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+#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
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+#define SCALER_POS1_SCL_WIDTH_SHIFT 0
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+
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#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
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#define SCALER_POS2_ALPHA_MODE_SHIFT 30
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#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
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@@ -564,6 +585,31 @@ enum hvs_pixel_format {
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#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
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#define SCALER_POS2_WIDTH_SHIFT 0
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+#define SCALER_TPZ0_VERT_RECALC BIT(31)
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+#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
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+#define SCALER_TPZ0_SCALE_SHIFT 8
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+#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
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+#define SCALER_TPZ0_IPHASE_SHIFT 0
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+#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
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+#define SCALER_TPZ1_RECIP_SHIFT 0
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+
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+/* Skips interpolating coefficients to 64 phases, so just 8 are used.
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+ * Required for nearest neighbor.
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+ */
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+#define SCALER_PPF_NOINTERP BIT(31)
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+/* Replaes the highest valued coefficient with one that makes all 4
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+ * sum to unity.
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+ */
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+#define SCALER_PPF_AGC BIT(30)
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+#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
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+#define SCALER_PPF_SCALE_SHIFT 8
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+#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
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+#define SCALER_PPF_IPHASE_SHIFT 0
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+
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+#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
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+#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
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+#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
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+
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#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
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#define SCALER_SRC_PITCH_SHIFT 0
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