mirror of https://github.com/hak5/openwrt.git
197 lines
5.8 KiB
Diff
197 lines
5.8 KiB
Diff
From c93c613214ac70c87beab5422a60077bf126b855 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Wed, 28 Nov 2018 21:07:25 +0800
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Subject: [PATCH 3/8] mtd: spinand: add support for GigaDevice GD5FxGQ4xA
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Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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---
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drivers/mtd/nand/spi/Makefile | 2 +-
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drivers/mtd/nand/spi/core.c | 1 +
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drivers/mtd/nand/spi/gigadevice.c | 148 ++++++++++++++++++++++++++++++
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include/linux/mtd/spinand.h | 1 +
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4 files changed, 151 insertions(+), 1 deletion(-)
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create mode 100644 drivers/mtd/nand/spi/gigadevice.c
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--- a/drivers/mtd/nand/spi/Makefile
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+++ b/drivers/mtd/nand/spi/Makefile
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@@ -1,3 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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-spinand-objs := core.o macronix.o micron.o toshiba.o winbond.o
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+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
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obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
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--- a/drivers/mtd/nand/spi/core.c
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+++ b/drivers/mtd/nand/spi/core.c
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@@ -762,6 +762,7 @@ static const struct nand_ops spinand_ops
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};
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static const struct spinand_manufacturer *spinand_manufacturers[] = {
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+ &gigadevice_spinand_manufacturer,
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¯onix_spinand_manufacturer,
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µn_spinand_manufacturer,
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&toshiba_spinand_manufacturer,
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--- /dev/null
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -0,0 +1,148 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Author:
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+ * Chuanhong Guo <gch981213@gmail.com>
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/kernel.h>
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+#include <linux/mtd/spinand.h>
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+
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+#define SPINAND_MFR_GIGADEVICE 0xC8
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+#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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+#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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+
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+static SPINAND_OP_VARIANTS(read_cache_variants,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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+static SPINAND_OP_VARIANTS(write_cache_variants,
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+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
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+
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+static SPINAND_OP_VARIANTS(update_cache_variants,
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+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
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+
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+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ region->offset = (16 * section) + 8;
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+ region->length = 8;
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+
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+ return 0;
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+}
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+
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+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ if (section) {
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+ region->offset = 16 * section;
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+ region->length = 8;
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+ } else {
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+ /* section 0 has one byte reserved for bad block mark */
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+ region->offset = 1;
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+ region->length = 7;
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+ }
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+ return 0;
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+}
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+
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+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ switch (status & STATUS_ECC_MASK) {
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+ case STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
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+ /* 1-7 bits are flipped. return the maximum. */
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+ return 7;
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+
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+ case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
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+ return 8;
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+
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+ case STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
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+ .ecc = gd5fxgq4xa_ooblayout_ecc,
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+ .free = gd5fxgq4xa_ooblayout_free,
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+};
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+
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+static const struct spinand_info gigadevice_spinand_table[] = {
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+ SPINAND_INFO("GD5F1GQ4xA", 0xF1,
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+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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+ gd5fxgq4xa_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ4xA", 0xF2,
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+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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+ gd5fxgq4xa_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ4xA", 0xF4,
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+ NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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+ gd5fxgq4xa_ecc_get_status)),
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+};
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+
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+static int gigadevice_spinand_detect(struct spinand_device *spinand)
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+{
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+ u8 *id = spinand->id.data;
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+ int ret;
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+
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+ /*
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+ * For GD NANDs, There is an address byte needed to shift in before IDs
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+ * are read out, so the first byte in raw_id is dummy.
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+ */
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+ if (id[1] != SPINAND_MFR_GIGADEVICE)
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+ return 0;
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+
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+ ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
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+ ARRAY_SIZE(gigadevice_spinand_table),
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+ id[2]);
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+ if (ret)
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+ return ret;
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+
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+ return 1;
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+}
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+
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+static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
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+ .detect = gigadevice_spinand_detect,
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+};
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+
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+const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
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+ .id = SPINAND_MFR_GIGADEVICE,
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+ .name = "GigaDevice",
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+ .ops = &gigadevice_spinand_manuf_ops,
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+};
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--- a/include/linux/mtd/spinand.h
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+++ b/include/linux/mtd/spinand.h
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@@ -194,6 +194,7 @@ struct spinand_manufacturer {
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};
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/* SPI NAND manufacturers */
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+extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
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extern const struct spinand_manufacturer macronix_spinand_manufacturer;
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extern const struct spinand_manufacturer micron_spinand_manufacturer;
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extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
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