mirror of https://github.com/hak5/openwrt.git
158 lines
5.1 KiB
Diff
158 lines
5.1 KiB
Diff
From a761ae710d6395af0d8d17a0b4b8f93a816ead46 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Tue, 17 Jan 2017 17:32:43 +0800
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Subject: [PATCH 12/13] irqchip/ls-scfg-msi: add MSI affinity support
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Cherry-pick patchwork patch.
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For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC
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SPI interrupts which can be associated with different Core.
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So we can support affinity to improve the performance.
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The MSI message data is a byte for Layerscape MSI.
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7 6 5 4 3 2 1 0
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| - | IBS | SRS |
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SRS bit0-1 is to select a MSIR which is associated with a CPU.
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IBS bit2-6 of ls1046, bit2-4 of ls1043a v1.1 is to select bit of the
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MSIR. With affinity, only bits of MSIR0(srs=0 cpu0) are available.
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All other bits of the MSIR1-3(cpu1-3) are reserved. The MSI hwirq
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always equals bit index of the MSIR0. When changing affinity, MSI
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message data will be appended corresponding SRS then MSI will be
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moved to the corresponding core.
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But in affinity mode, there is only 8 MSI interrupts for a controller
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of LS1043a v1.1. It cannot meet the requirement of the some PCIe
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devices such as 4 ports Ethernet card. In contrast, without affinity,
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all MSIRs can be used for core 0, the MSI interrupts can up to 32.
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So the parameter is added to control affinity mode.
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"lsmsi=no-affinity" will disable affinity and increase MSI
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interrupt number.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/irqchip/irq-ls-scfg-msi.c | 68 ++++++++++++++++++++++++++++++++++++---
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1 file changed, 63 insertions(+), 5 deletions(-)
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diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
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index 71a2050..57e3d90 100644
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--- a/drivers/irqchip/irq-ls-scfg-msi.c
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+++ b/drivers/irqchip/irq-ls-scfg-msi.c
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@@ -40,6 +40,7 @@ struct ls_scfg_msir {
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unsigned int gic_irq;
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unsigned int bit_start;
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unsigned int bit_end;
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+ unsigned int srs; /* Shared interrupt register select */
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void __iomem *reg;
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};
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@@ -70,6 +71,19 @@ static struct msi_domain_info ls_scfg_msi_domain_info = {
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.chip = &ls_scfg_msi_irq_chip,
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};
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+static int msi_affinity_flag = 1;
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+
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+static int __init early_parse_ls_scfg_msi(char *p)
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+{
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+ if (p && strncmp(p, "no-affinity", 11) == 0)
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+ msi_affinity_flag = 0;
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+ else
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+ msi_affinity_flag = 1;
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+
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+ return 0;
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+}
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+early_param("lsmsi", early_parse_ls_scfg_msi);
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+
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static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
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@@ -77,12 +91,36 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
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msg->address_hi = upper_32_bits(msi_data->msiir_addr);
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msg->address_lo = lower_32_bits(msi_data->msiir_addr);
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msg->data = data->hwirq;
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+
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+ if (msi_affinity_flag)
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+ msg->data |= cpumask_first(data->common->affinity);
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}
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static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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- return -EINVAL;
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+ struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
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+ u32 cpu;
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+
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+ if (!msi_affinity_flag)
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+ return -EINVAL;
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+
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+ if (!force)
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+ cpu = cpumask_any_and(mask, cpu_online_mask);
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+ else
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+ cpu = cpumask_first(mask);
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+
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+ if (cpu >= msi_data->msir_num)
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+ return -EINVAL;
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+
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+ if (msi_data->msir[cpu].gic_irq <= 0) {
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+ pr_warn("cannot bind the irq to cpu%d\n", cpu);
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+ return -EINVAL;
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+ }
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+
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+ cpumask_copy(irq_data->common->affinity, mask);
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+
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+ return IRQ_SET_MASK_OK;
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}
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static struct irq_chip ls_scfg_msi_parent_chip = {
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@@ -158,7 +196,7 @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
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for_each_set_bit_from(pos, &val, size) {
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hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
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- msir->index;
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+ msir->srs;
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virq = irq_find_mapping(msi_data->parent, hwirq);
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if (virq)
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generic_handle_irq(virq);
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@@ -221,10 +259,19 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
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ls_scfg_msi_irq_handler,
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msir);
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+ if (msi_affinity_flag) {
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+ /* Associate MSIR interrupt to the cpu */
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+ irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
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+ msir->srs = 0; /* This value is determined by the CPU */
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+ } else
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+ msir->srs = index;
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+
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/* Release the hwirqs corresponding to this MSIR */
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- for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
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- hwirq = i << msi_data->cfg->ibs_shift | msir->index;
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- bitmap_clear(msi_data->used, hwirq, 1);
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+ if (!msi_affinity_flag || msir->index == 0) {
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+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
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+ hwirq = i << msi_data->cfg->ibs_shift | msir->index;
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+ bitmap_clear(msi_data->used, hwirq, 1);
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+ }
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}
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return 0;
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@@ -321,6 +368,17 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
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bitmap_set(msi_data->used, 0, msi_data->irqs_num);
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msi_data->msir_num = of_irq_count(pdev->dev.of_node);
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+
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+ if (msi_affinity_flag) {
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+ u32 cpu_num;
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+
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+ cpu_num = num_possible_cpus();
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+ if (msi_data->msir_num >= cpu_num)
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+ msi_data->msir_num = cpu_num;
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+ else
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+ msi_affinity_flag = 0;
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+ }
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+
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msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
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sizeof(*msi_data->msir),
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GFP_KERNEL);
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--
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2.1.0.27.g96db324
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