mirror of https://github.com/hak5/openwrt.git
228 lines
5.9 KiB
Diff
228 lines
5.9 KiB
Diff
From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Thu, 3 May 2012 14:36:11 +0200
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Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices
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---
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arch/mips/bcm63xx/Makefile | 3 +-
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arch/mips/bcm63xx/pci-ath9k-fixup.c | 190 ++++++++++++++++++++
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.../include/asm/mach-bcm63xx/pci_ath9k_fixup.h | 7 +
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3 files changed, 199 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c
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create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
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--- a/arch/mips/bcm63xx/Makefile
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+++ b/arch/mips/bcm63xx/Makefile
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@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o
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setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
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dev-hsspi.o dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o \
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dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \
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- usb-common.o
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+ pci-ath9k-fixup.o usb-common.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += boards/
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--- /dev/null
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+++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c
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@@ -0,0 +1,190 @@
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+/*
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+ * Broadcom BCM63XX Ath9k EEPROM fixup helper.
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+ *
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+ * Copytight (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
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+ *
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+ * Based on
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+ *
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+ * Atheros AP94 reference board PCI initialization
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+ *
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+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/pci.h>
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+#include <linux/delay.h>
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+#include <linux/ath9k_platform.h>
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+
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+#include <bcm63xx_cpu.h>
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+#include <bcm63xx_io.h>
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+#include <bcm63xx_nvram.h>
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+#include <bcm63xx_dev_pci.h>
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+#include <bcm63xx_dev_flash.h>
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+#include <bcm63xx_dev_hsspi.h>
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+#include <pci_ath9k_fixup.h>
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+
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+struct ath9k_fixup {
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+ unsigned slot;
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+ u8 mac[ETH_ALEN];
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+ struct ath9k_platform_data pdata;
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+};
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+
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+static int ath9k_num_fixups;
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+static struct ath9k_fixup ath9k_fixups[2] = {
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+ {
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+ .slot = 255,
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+ .pdata = {
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+ .led_pin = -1,
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+ },
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+ },
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+ {
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+ .slot = 255,
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+ .pdata = {
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+ .led_pin = -1,
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+ },
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+ },
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+};
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+
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+static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset)
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+{
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+ u32 addr;
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+
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+ if (BCMCPU_IS_6328()) {
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+ addr = 0x18000000;
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+ } else {
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+ addr = bcm_mpi_readl(MPI_CSBASE_REG(0));
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+ addr &= MPI_CSBASE_BASE_MASK;
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+ }
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+
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+ switch (bcm63xx_attached_flash) {
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+ case BCM63XX_FLASH_TYPE_PARALLEL:
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+ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
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+ return eeprom;
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+ case BCM63XX_FLASH_TYPE_SERIAL:
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+ /* the first megabyte is memory mapped */
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+ if (offset < 0x100000) {
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+ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
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+ return eeprom;
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+ }
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+
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+ if (BCMCPU_IS_6328()) {
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+ /* we can change the memory mapped megabyte */
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+ bcm_hsspi_writel(offset & 0xf00000, 0x18);
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+ memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
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+ bcm_hsspi_writel(0, 0x18);
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+ return eeprom;
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+ }
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+ /* can't do anything here without talking to the SPI controller. */
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+ case BCM63XX_FLASH_TYPE_NAND:
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+ default:
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+ return NULL;
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+ }
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+}
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+
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+static void ath9k_pci_fixup(struct pci_dev *dev)
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+{
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+ void __iomem *mem;
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+ struct ath9k_platform_data *pdata = NULL;
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+ u16 *cal_data = NULL;
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+ u16 cmd;
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+ u32 bar0;
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+ u32 val;
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+ unsigned i;
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+
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+ for (i = 0; i < ath9k_num_fixups; i++) {
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+ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))
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+ continue;
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+
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+ cal_data = ath9k_fixups[i].pdata.eeprom_data;
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+ pdata = &ath9k_fixups[i].pdata;
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+ break;
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+ }
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+
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+ if (cal_data == NULL)
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+ return;
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+
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+ if (*cal_data != 0xa55a) {
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+ pr_err("pci %s: invalid calibration data\n", pci_name(dev));
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+ return;
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+ }
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+
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+ pr_info("pci %s: fixup device configuration\n", pci_name(dev));
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+
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+ switch (bcm63xx_get_cpu_id()) {
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+ case BCM6328_CPU_ID:
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+ val = BCM_PCIE_MEM_BASE_PA;
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+ break;
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+ case BCM6348_CPU_ID:
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+ case BCM6358_CPU_ID:
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+ case BCM6368_CPU_ID:
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+ val = BCM_PCI_MEM_BASE_PA;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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+ mem = ioremap(val, 0x10000);
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+ if (!mem) {
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+ pr_err("pci %s: ioremap error\n", pci_name(dev));
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+ return;
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+ }
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+
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+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
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+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val);
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+
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+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
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+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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+ pci_write_config_word(dev, PCI_COMMAND, cmd);
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+
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+ /* set offset to first reg address */
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+ cal_data += 3;
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+ while(*cal_data != 0xffff) {
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+ u32 reg;
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+ reg = *cal_data++;
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+ val = *cal_data++;
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+ val |= (*cal_data++) << 16;
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+
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+ writel(val, mem + reg);
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+ udelay(100);
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+ }
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+
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+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
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+ dev->vendor = val & 0xffff;
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+ dev->device = (val >> 16) & 0xffff;
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+
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+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
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+ dev->revision = val & 0xff;
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+ dev->class = val >> 8; /* upper 3 bytes */
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+
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+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
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+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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+ pci_write_config_word(dev, PCI_COMMAND, cmd);
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+
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
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+
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+ iounmap(mem);
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+
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+ dev->dev.platform_data = pdata;
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+}
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
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+
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+void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset)
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+{
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+ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
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+ return;
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+
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+ ath9k_fixups[ath9k_num_fixups].slot = slot;
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+
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+ if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))
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+ return;
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+
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+ if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac))
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+ return;
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+
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+ ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac;
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+ ath9k_num_fixups++;
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+}
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
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@@ -0,0 +1,7 @@
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+#ifndef _PCI_ATH9K_FIXUP
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+#define _PCI_ATH9K_FIXUP
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+
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+
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+void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init;
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+
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+#endif /* _PCI_ATH9K_FIXUP */
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