openwrt/target/linux/ramips/dts/mt7628an_cudy_wr1000.dts

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7628an.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "cudy,wr1000", "mediatek,mt7628an-soc";
model = "Cudy WR1000";
aliases {
led-boot = &led_wps;
led-failsafe = &led_wps;
led-upgrade = &led_wps;
label-mac-device = &wmac;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "rfkill";
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
lan1 {
label = "wr1000:blue:lan1";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "wr1000:blue:lan2";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
wan {
label = "wr1000:blue:wan";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "wr1000:blue:wlan2g";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
led_wps: wps {
label = "wr1000:blue:wps";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x7b0000>;
};
};
};
};
&state_default {
gpio {
ralink,group = "i2s", "refclk", "wdt", "p4led_an",
"p3led_an", "p2led_an", "wled_an";
ralink,function = "gpio";
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
led {
led-sources = <2>;
led-active-low;
};
};
};
&wmac {
status = "okay";
};
&ethernet {
mtd-mac-address = <&factory 0x28>;
};
&esw {
mediatek,portmap = <0x2f>;
};