mirror of https://github.com/hak5/openwrt.git
46 lines
1.5 KiB
Diff
46 lines
1.5 KiB
Diff
From e6d9c3121f2a8b92bd6202d6a32e7d428990d7d7 Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Tue, 6 Mar 2018 17:09:29 +0800
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Subject: [PATCH 206/224] dt-bindings: clock: mediatek: update audsys
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documentation to adapt MFD device
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The MediaTek audio hardware block that exposes functionalities that are
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handled by separate subsystems in the kernel. These functions are all
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mapped somewhere at 0x112xxxxx, and there are some control bits are mixed
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up with other functions within the same registers.
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This patch modifies example to illustrate child nodes.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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---
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.../bindings/arm/mediatek/mediatek,audsys.txt | 19 ++++++++++++++-----
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1 file changed, 14 insertions(+), 5 deletions(-)
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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@@ -13,10 +13,19 @@ The AUDSYS controller uses the common cl
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+Required sub-nodes:
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+-------
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+For common binding part and usage, refer to
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+../sonud/mt2701-afe-pcm.txt.
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+
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Example:
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-audsys: audsys@11220000 {
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- compatible = "mediatek,mt7622-audsys", "syscon";
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- reg = <0 0x11220000 0 0x1000>;
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- #clock-cells = <1>;
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-};
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+ audsys: clock-controller@11220000 {
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+ compatible = "mediatek,mt7622-audsys", "syscon";
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+ reg = <0 0x11220000 0 0x2000>;
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+ #clock-cells = <1>;
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+
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+ afe: audio-controller {
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+ ...
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+ };
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+ };
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