mirror of https://github.com/hak5/openwrt.git
879 lines
25 KiB
Diff
879 lines
25 KiB
Diff
From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 9 Sep 2014 22:45:34 +0200
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Subject: [PATCH 28/36] NET: lantiq: various etop fixes
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
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1 file changed, 389 insertions(+), 166 deletions(-)
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--- a/drivers/net/ethernet/lantiq_etop.c
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+++ b/drivers/net/ethernet/lantiq_etop.c
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@@ -11,7 +11,7 @@
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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@@ -30,11 +30,16 @@
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#include <linux/mm.h>
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#include <linux/platform_device.h>
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#include <linux/ethtool.h>
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+#include <linux/if_vlan.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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+#include <linux/clk.h>
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+#include <linux/of_net.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_platform.h>
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#include <asm/checksum.h>
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@@ -42,7 +47,7 @@
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#include <xway_dma.h>
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#include <lantiq_platform.h>
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-#define LTQ_ETOP_MDIO 0x11804
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+#define LTQ_ETOP_MDIO_ACC 0x11804
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#define MDIO_REQUEST 0x80000000
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#define MDIO_READ 0x40000000
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#define MDIO_ADDR_MASK 0x1f
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@@ -51,44 +56,91 @@
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#define MDIO_REG_OFFSET 0x10
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#define MDIO_VAL_MASK 0xffff
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-#define PPE32_CGEN 0x800
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-#define LQ_PPE32_ENET_MAC_CFG 0x1840
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+#define LTQ_ETOP_MDIO_CFG 0x11800
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+#define MDIO_CFG_MASK 0x6
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+
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+#define LTQ_ETOP_CFG 0x11808
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+#define LTQ_ETOP_IGPLEN 0x11820
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+#define LTQ_ETOP_MAC_CFG 0x11840
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#define LTQ_ETOP_ENETS0 0x11850
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#define LTQ_ETOP_MAC_DA0 0x1186C
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#define LTQ_ETOP_MAC_DA1 0x11870
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-#define LTQ_ETOP_CFG 0x16020
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-#define LTQ_ETOP_IGPLEN 0x16080
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+
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+#define MAC_CFG_MASK 0xfff
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+#define MAC_CFG_CGEN (1 << 11)
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+#define MAC_CFG_DUPLEX (1 << 2)
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+#define MAC_CFG_SPEED (1 << 1)
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+#define MAC_CFG_LINK (1 << 0)
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#define MAX_DMA_CHAN 0x8
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#define MAX_DMA_CRC_LEN 0x4
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#define MAX_DMA_DATA_LEN 0x600
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#define ETOP_FTCU BIT(28)
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-#define ETOP_MII_MASK 0xf
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-#define ETOP_MII_NORMAL 0xd
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-#define ETOP_MII_REVERSE 0xe
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#define ETOP_PLEN_UNDER 0x40
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-#define ETOP_CGEN 0x800
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+#define ETOP_CFG_MII0 0x01
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-/* use 2 static channels for TX/RX */
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-#define LTQ_ETOP_TX_CHANNEL 1
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-#define LTQ_ETOP_RX_CHANNEL 6
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-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
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-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
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+#define ETOP_CFG_MASK 0xfff
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+#define ETOP_CFG_FEN0 (1 << 8)
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+#define ETOP_CFG_SEN0 (1 << 6)
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+#define ETOP_CFG_OFF1 (1 << 3)
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+#define ETOP_CFG_REMII0 (1 << 1)
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+#define ETOP_CFG_OFF0 (1 << 0)
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+
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+#define LTQ_GBIT_MDIO_CTL 0xCC
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+#define LTQ_GBIT_MDIO_DATA 0xd0
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+#define LTQ_GBIT_GCTL0 0x68
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+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
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+#define LTQ_GBIT_P0_CTL 0x4
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+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
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+#define LTQ_GBIT_RGMII_CTL 0x78
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+
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+#define PMAC_HD_CTL_AS (1 << 19)
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+#define PMAC_HD_CTL_RXSH (1 << 22)
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+
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+/* Switch Enable (0=disable, 1=enable) */
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+#define GCTL0_SE 0x80000000
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+/* Disable MDIO auto polling (0=disable, 1=enable) */
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+#define PX_CTL_DMDIO 0x00400000
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+
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+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
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+#define MDC_CLOCK_MASK 0xff000000
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+#define MDC_CLOCK_OFFSET 24
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+
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+/* register information for the gbit's MDIO bus */
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+#define MDIO_XR9_REQUEST 0x00008000
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+#define MDIO_XR9_READ 0x00000800
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+#define MDIO_XR9_WRITE 0x00000400
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+#define MDIO_XR9_REG_MASK 0x1f
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+#define MDIO_XR9_ADDR_MASK 0x1f
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+#define MDIO_XR9_RD_MASK 0xffff
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+#define MDIO_XR9_REG_OFFSET 0
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+#define MDIO_XR9_ADDR_OFFSET 5
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+#define MDIO_XR9_WR_OFFSET 16
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+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
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+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
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+
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+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
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#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
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#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
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#define ltq_etop_w32_mask(x, y, z) \
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ltq_w32_mask(x, y, ltq_etop_membase + (z))
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-#define DRV_VERSION "1.0"
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+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
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+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
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+#define ltq_gbit_w32_mask(x, y, z) \
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+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
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+
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+#define DRV_VERSION "1.2"
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static void __iomem *ltq_etop_membase;
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+static void __iomem *ltq_gbit_membase;
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struct ltq_etop_chan {
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- int idx;
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int tx_free;
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+ int irq;
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struct net_device *netdev;
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struct napi_struct napi;
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struct ltq_dma_channel dma;
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@@ -98,23 +150,36 @@ struct ltq_etop_chan {
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struct ltq_etop_priv {
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struct net_device *netdev;
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struct platform_device *pdev;
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- struct ltq_eth_data *pldata;
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struct resource *res;
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struct mii_bus *mii_bus;
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- struct ltq_etop_chan ch[MAX_DMA_CHAN];
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- int tx_free[MAX_DMA_CHAN >> 1];
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+ struct ltq_etop_chan txch;
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+ struct ltq_etop_chan rxch;
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- spinlock_t lock;
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+ int tx_irq;
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+ int rx_irq;
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+
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+ unsigned char mac[6];
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+ int mii_mode;
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+
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+ spinlock_t lock;
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+
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+ struct clk *clk_ppe;
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+ struct clk *clk_switch;
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+ struct clk *clk_ephy;
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+ struct clk *clk_ephycgu;
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};
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+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
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+ int phy_reg, u16 phy_data);
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+
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static int
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ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
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{
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struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
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+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
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if (!ch->skb[ch->dma.desc])
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return -ENOMEM;
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ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
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@@ -149,8 +214,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
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spin_unlock_irqrestore(&priv->lock, flags);
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skb_put(skb, len);
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+ skb->dev = ch->netdev;
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skb->protocol = eth_type_trans(skb, ch->netdev);
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netif_receive_skb(skb);
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+ ch->netdev->stats.rx_packets++;
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+ ch->netdev->stats.rx_bytes += len;
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}
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static int
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@@ -158,7 +226,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
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{
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struct ltq_etop_chan *ch = container_of(napi,
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struct ltq_etop_chan, napi);
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+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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int work_done = 0;
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+ unsigned long flags;
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while (work_done < budget) {
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struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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@@ -170,7 +240,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
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}
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if (work_done < budget) {
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napi_complete_done(&ch->napi, work_done);
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+ spin_lock_irqsave(&priv->lock, flags);
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ltq_dma_ack_irq(&ch->dma);
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+ spin_unlock_irqrestore(&priv->lock, flags);
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}
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return work_done;
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}
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@@ -182,12 +254,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
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container_of(napi, struct ltq_etop_chan, napi);
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struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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struct netdev_queue *txq =
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- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
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+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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while ((ch->dma.desc_base[ch->tx_free].ctl &
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(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
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+ ch->netdev->stats.tx_packets++;
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+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
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dev_kfree_skb_any(ch->skb[ch->tx_free]);
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ch->skb[ch->tx_free] = NULL;
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memset(&ch->dma.desc_base[ch->tx_free], 0,
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@@ -200,7 +274,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
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if (netif_tx_queue_stopped(txq))
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netif_tx_start_queue(txq);
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napi_complete(&ch->napi);
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+ spin_lock_irqsave(&priv->lock, flags);
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ltq_dma_ack_irq(&ch->dma);
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+ spin_unlock_irqrestore(&priv->lock, flags);
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return 1;
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}
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@@ -208,9 +284,10 @@ static irqreturn_t
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ltq_etop_dma_irq(int irq, void *_priv)
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{
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struct ltq_etop_priv *priv = _priv;
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- int ch = irq - LTQ_DMA_CH0_INT;
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-
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- napi_schedule(&priv->ch[ch].napi);
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+ if (irq == priv->txch.dma.irq)
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+ napi_schedule(&priv->txch.napi);
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+ else
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+ napi_schedule(&priv->rxch.napi);
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return IRQ_HANDLED;
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}
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@@ -222,7 +299,7 @@ ltq_etop_free_channel(struct net_device
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ltq_dma_free(&ch->dma);
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if (ch->dma.irq)
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free_irq(ch->dma.irq, priv);
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- if (IS_RX(ch->idx)) {
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+ if (ch == &priv->txch) {
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int desc;
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for (desc = 0; desc < LTQ_DESC_NUM; desc++)
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dev_kfree_skb_any(ch->skb[ch->dma.desc]);
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@@ -233,66 +310,135 @@ static void
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ltq_etop_hw_exit(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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- int i;
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- ltq_pmu_disable(PMU_PPE);
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- for (i = 0; i < MAX_DMA_CHAN; i++)
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- if (IS_TX(i) || IS_RX(i))
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- ltq_etop_free_channel(dev, &priv->ch[i]);
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+ clk_disable(priv->clk_ppe);
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+
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+ if (of_machine_is_compatible("lantiq,ar9"))
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+ clk_disable(priv->clk_switch);
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+
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+ if (of_machine_is_compatible("lantiq,ase")) {
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+ clk_disable(priv->clk_ephy);
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+ clk_disable(priv->clk_ephycgu);
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+ }
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+
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+ ltq_etop_free_channel(dev, &priv->txch);
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+ ltq_etop_free_channel(dev, &priv->rxch);
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+}
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+
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+static void
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+ltq_etop_gbit_init(struct net_device *dev)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+
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+ clk_enable(priv->clk_switch);
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+
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+ /* enable gbit port0 on the SoC */
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+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
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+
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+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
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+ /* disable MDIO auto polling mode */
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+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
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+ /* set 1522 packet size */
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+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
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+ /* disable pmac & dmac headers */
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+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
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+ LTQ_GBIT_PMAC_HD_CTL);
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+ /* Due to traffic halt when burst length 8,
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+ replace default IPG value with 0x3B */
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+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
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+ /* set mdc clock to 2.5 MHz */
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+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
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+ LTQ_GBIT_RGMII_CTL);
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}
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static int
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ltq_etop_hw_init(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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- int i;
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+ int mii_mode = priv->mii_mode;
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+
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+ clk_enable(priv->clk_ppe);
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- ltq_pmu_enable(PMU_PPE);
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+ if (of_machine_is_compatible("lantiq,ar9")) {
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+ ltq_etop_gbit_init(dev);
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+ /* force the etops link to the gbit to MII */
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+ mii_mode = PHY_INTERFACE_MODE_MII;
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+ }
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+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
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+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
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+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
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- switch (priv->pldata->mii_mode) {
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+ switch (mii_mode) {
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case PHY_INTERFACE_MODE_RMII:
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- ltq_etop_w32_mask(ETOP_MII_MASK,
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- ETOP_MII_REVERSE, LTQ_ETOP_CFG);
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+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
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+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
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break;
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case PHY_INTERFACE_MODE_MII:
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- ltq_etop_w32_mask(ETOP_MII_MASK,
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- ETOP_MII_NORMAL, LTQ_ETOP_CFG);
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+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
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+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
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break;
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default:
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+ if (of_machine_is_compatible("lantiq,ase")) {
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+ clk_enable(priv->clk_ephy);
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+ /* disable external MII */
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+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
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+ /* enable clock for internal PHY */
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+ clk_enable(priv->clk_ephycgu);
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+ /* we need to write this magic to the internal phy to
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+ make it work */
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+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
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+ pr_info("Selected EPHY mode\n");
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+ break;
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+ }
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netdev_err(dev, "unknown mii mode %d\n",
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- priv->pldata->mii_mode);
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+ mii_mode);
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return -ENOTSUPP;
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}
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- /* enable crc generation */
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- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
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+ return 0;
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+}
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+
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+static int
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+ltq_etop_dma_init(struct net_device *dev)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+ int tx = priv->tx_irq - LTQ_DMA_ETOP;
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+ int rx = priv->rx_irq - LTQ_DMA_ETOP;
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+ int err;
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ltq_dma_init_port(DMA_PORT_ETOP);
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- for (i = 0; i < MAX_DMA_CHAN; i++) {
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- int irq = LTQ_DMA_CH0_INT + i;
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- struct ltq_etop_chan *ch = &priv->ch[i];
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-
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- ch->idx = ch->dma.nr = i;
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- ch->dma.dev = &priv->pdev->dev;
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-
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- if (IS_TX(i)) {
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- ltq_dma_alloc_tx(&ch->dma);
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- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
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- } else if (IS_RX(i)) {
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- ltq_dma_alloc_rx(&ch->dma);
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- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
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- ch->dma.desc++)
|
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- if (ltq_etop_alloc_skb(ch))
|
|
- return -ENOMEM;
|
|
- ch->dma.desc = 0;
|
|
- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
|
|
+ priv->txch.dma.nr = tx;
|
|
+ priv->txch.dma.dev = &priv->pdev->dev;
|
|
+ ltq_dma_alloc_tx(&priv->txch.dma);
|
|
+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
|
|
+ if (err) {
|
|
+ netdev_err(dev, "failed to allocate tx irq\n");
|
|
+ goto err_out;
|
|
+ }
|
|
+ priv->txch.dma.irq = priv->tx_irq;
|
|
+
|
|
+ priv->rxch.dma.nr = rx;
|
|
+ priv->rxch.dma.dev = &priv->pdev->dev;
|
|
+ ltq_dma_alloc_rx(&priv->rxch.dma);
|
|
+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
|
|
+ priv->rxch.dma.desc++) {
|
|
+ if (ltq_etop_alloc_skb(&priv->rxch)) {
|
|
+ netdev_err(dev, "failed to allocate skbs\n");
|
|
+ err = -ENOMEM;
|
|
+ goto err_out;
|
|
}
|
|
- ch->dma.irq = irq;
|
|
}
|
|
- return 0;
|
|
+ priv->rxch.dma.desc = 0;
|
|
+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
|
|
+ if (err)
|
|
+ netdev_err(dev, "failed to allocate rx irq\n");
|
|
+ else
|
|
+ priv->rxch.dma.irq = priv->rx_irq;
|
|
+err_out:
|
|
+ return err;
|
|
}
|
|
|
|
static void
|
|
@@ -311,6 +457,39 @@ static const struct ethtool_ops ltq_etop
|
|
};
|
|
|
|
static int
|
|
+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
|
|
+ int phy_reg, u16 phy_data)
|
|
+{
|
|
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
|
|
+ (phy_data << MDIO_XR9_WR_OFFSET) |
|
|
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
|
|
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
|
|
+
|
|
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
|
+ ;
|
|
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
|
|
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
|
+ ;
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
|
|
+{
|
|
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
|
|
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
|
|
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
|
|
+
|
|
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
|
+ ;
|
|
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
|
|
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
|
|
+ ;
|
|
+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
|
|
+ return val;
|
|
+}
|
|
+
|
|
+static int
|
|
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
|
|
{
|
|
u32 val = MDIO_REQUEST |
|
|
@@ -318,9 +497,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
|
|
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
|
|
phy_data;
|
|
|
|
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
|
;
|
|
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
|
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
|
|
return 0;
|
|
}
|
|
|
|
@@ -331,12 +510,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
|
|
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
|
|
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
|
|
|
|
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
|
;
|
|
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
|
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
|
|
;
|
|
- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
|
|
+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
|
|
return val;
|
|
}
|
|
|
|
@@ -351,8 +530,18 @@ ltq_etop_mdio_probe(struct net_device *d
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
struct phy_device *phydev;
|
|
+ u32 phy_supported = (SUPPORTED_10baseT_Half
|
|
+ | SUPPORTED_10baseT_Full
|
|
+ | SUPPORTED_100baseT_Half
|
|
+ | SUPPORTED_100baseT_Full
|
|
+ | SUPPORTED_Autoneg
|
|
+ | SUPPORTED_MII
|
|
+ | SUPPORTED_TP);
|
|
|
|
- phydev = phy_find_first(priv->mii_bus);
|
|
+ if (of_machine_is_compatible("lantiq,ase"))
|
|
+ phydev = mdiobus_get_phy(priv->mii_bus, 8);
|
|
+ else
|
|
+ phydev = mdiobus_get_phy(priv->mii_bus, 0);
|
|
|
|
if (!phydev) {
|
|
netdev_err(dev, "no PHY found\n");
|
|
@@ -360,21 +549,18 @@ ltq_etop_mdio_probe(struct net_device *d
|
|
}
|
|
|
|
phydev = phy_connect(dev, phydev_name(phydev),
|
|
- <q_etop_mdio_link, priv->pldata->mii_mode);
|
|
+ <q_etop_mdio_link, priv->mii_mode);
|
|
|
|
if (IS_ERR(phydev)) {
|
|
netdev_err(dev, "Could not attach to PHY\n");
|
|
return PTR_ERR(phydev);
|
|
}
|
|
|
|
- phydev->supported &= (SUPPORTED_10baseT_Half
|
|
- | SUPPORTED_10baseT_Full
|
|
- | SUPPORTED_100baseT_Half
|
|
- | SUPPORTED_100baseT_Full
|
|
- | SUPPORTED_Autoneg
|
|
- | SUPPORTED_MII
|
|
- | SUPPORTED_TP);
|
|
+ if (of_machine_is_compatible("lantiq,ar9"))
|
|
+ phy_supported |= SUPPORTED_1000baseT_Half
|
|
+ | SUPPORTED_1000baseT_Full;
|
|
|
|
+ phydev->supported &= phy_supported;
|
|
phydev->advertising = phydev->supported;
|
|
phy_attached_info(phydev);
|
|
|
|
@@ -395,8 +581,13 @@ ltq_etop_mdio_init(struct net_device *de
|
|
}
|
|
|
|
priv->mii_bus->priv = dev;
|
|
- priv->mii_bus->read = ltq_etop_mdio_rd;
|
|
- priv->mii_bus->write = ltq_etop_mdio_wr;
|
|
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
|
+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
|
|
+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
|
|
+ } else {
|
|
+ priv->mii_bus->read = ltq_etop_mdio_rd;
|
|
+ priv->mii_bus->write = ltq_etop_mdio_wr;
|
|
+ }
|
|
priv->mii_bus->name = "ltq_mii";
|
|
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
|
|
priv->pdev->name, priv->pdev->id);
|
|
@@ -433,17 +624,19 @@ static int
|
|
ltq_etop_open(struct net_device *dev)
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
- int i;
|
|
+ unsigned long flags;
|
|
|
|
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
- struct ltq_etop_chan *ch = &priv->ch[i];
|
|
+ napi_enable(&priv->txch.napi);
|
|
+ napi_enable(&priv->rxch.napi);
|
|
+
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ ltq_dma_open(&priv->txch.dma);
|
|
+ ltq_dma_open(&priv->rxch.dma);
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+
|
|
+ if (dev->phydev)
|
|
+ phy_start(dev->phydev);
|
|
|
|
- if (!IS_TX(i) && (!IS_RX(i)))
|
|
- continue;
|
|
- ltq_dma_open(&ch->dma);
|
|
- napi_enable(&ch->napi);
|
|
- }
|
|
- phy_start(dev->phydev);
|
|
netif_tx_start_all_queues(dev);
|
|
return 0;
|
|
}
|
|
@@ -452,18 +645,19 @@ static int
|
|
ltq_etop_stop(struct net_device *dev)
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
- int i;
|
|
+ unsigned long flags;
|
|
|
|
netif_tx_stop_all_queues(dev);
|
|
- phy_stop(dev->phydev);
|
|
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
- struct ltq_etop_chan *ch = &priv->ch[i];
|
|
-
|
|
- if (!IS_RX(i) && !IS_TX(i))
|
|
- continue;
|
|
- napi_disable(&ch->napi);
|
|
- ltq_dma_close(&ch->dma);
|
|
- }
|
|
+ if (dev->phydev)
|
|
+ phy_stop(dev->phydev);
|
|
+ napi_disable(&priv->txch.napi);
|
|
+ napi_disable(&priv->rxch.napi);
|
|
+
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ ltq_dma_close(&priv->txch.dma);
|
|
+ ltq_dma_close(&priv->rxch.dma);
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -473,16 +667,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
|
int queue = skb_get_queue_mapping(skb);
|
|
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
|
|
- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
|
|
- int len;
|
|
+ struct ltq_dma_desc *desc =
|
|
+ &priv->txch.dma.desc_base[priv->txch.dma.desc];
|
|
unsigned long flags;
|
|
u32 byte_offset;
|
|
+ int len;
|
|
|
|
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
|
|
|
|
- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
|
|
- dev_kfree_skb_any(skb);
|
|
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
|
|
+ priv->txch.skb[priv->txch.dma.desc]) {
|
|
netdev_err(dev, "tx ring full\n");
|
|
netif_tx_stop_queue(txq);
|
|
return NETDEV_TX_BUSY;
|
|
@@ -490,7 +684,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
|
|
|
/* dma needs to start on a 16 byte aligned address */
|
|
byte_offset = CPHYSADDR(skb->data) % 16;
|
|
- ch->skb[ch->dma.desc] = skb;
|
|
+ priv->txch.skb[priv->txch.dma.desc] = skb;
|
|
|
|
netif_trans_update(dev);
|
|
|
|
@@ -500,11 +694,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
|
wmb();
|
|
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
|
|
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
|
|
- ch->dma.desc++;
|
|
- ch->dma.desc %= LTQ_DESC_NUM;
|
|
+ priv->txch.dma.desc++;
|
|
+ priv->txch.dma.desc %= LTQ_DESC_NUM;
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
|
|
+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
|
|
netif_tx_stop_queue(txq);
|
|
|
|
return NETDEV_TX_OK;
|
|
@@ -515,11 +709,14 @@ ltq_etop_change_mtu(struct net_device *d
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
unsigned long flags;
|
|
+ int max;
|
|
|
|
dev->mtu = new_mtu;
|
|
|
|
+ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
|
|
+
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
|
|
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
return 0;
|
|
@@ -579,6 +776,9 @@ ltq_etop_init(struct net_device *dev)
|
|
if (err)
|
|
goto err_hw;
|
|
ltq_etop_change_mtu(dev, 1500);
|
|
+ err = ltq_etop_dma_init(dev);
|
|
+ if (err)
|
|
+ goto err_hw;
|
|
|
|
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
|
|
if (!is_valid_ether_addr(mac.sa_data)) {
|
|
@@ -596,9 +796,10 @@ ltq_etop_init(struct net_device *dev)
|
|
dev->addr_assign_type = NET_ADDR_RANDOM;
|
|
|
|
ltq_etop_set_multicast_list(dev);
|
|
- err = ltq_etop_mdio_init(dev);
|
|
- if (err)
|
|
- goto err_netdev;
|
|
+ if (!ltq_etop_mdio_init(dev))
|
|
+ dev->ethtool_ops = <q_etop_ethtool_ops;
|
|
+ else
|
|
+ pr_warn("etop: mdio probe failed\n");;
|
|
return 0;
|
|
|
|
err_netdev:
|
|
@@ -618,6 +819,9 @@ ltq_etop_tx_timeout(struct net_device *d
|
|
err = ltq_etop_hw_init(dev);
|
|
if (err)
|
|
goto err_hw;
|
|
+ err = ltq_etop_dma_init(dev);
|
|
+ if (err)
|
|
+ goto err_hw;
|
|
netif_trans_update(dev);
|
|
netif_wake_queue(dev);
|
|
return;
|
|
@@ -641,14 +845,19 @@ static const struct net_device_ops ltq_e
|
|
.ndo_tx_timeout = ltq_etop_tx_timeout,
|
|
};
|
|
|
|
-static int __init
|
|
-ltq_etop_probe(struct platform_device *pdev)
|
|
+static int ltq_etop_probe(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev;
|
|
struct ltq_etop_priv *priv;
|
|
- struct resource *res;
|
|
+ struct resource *res, *gbit_res, irqres[2];
|
|
+ const u8 *mac;
|
|
int err;
|
|
- int i;
|
|
+
|
|
+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
|
|
+ if (err != 2) {
|
|
+ dev_err(&pdev->dev, "failed to get etop irqs\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
@@ -674,31 +883,62 @@ ltq_etop_probe(struct platform_device *p
|
|
goto err_out;
|
|
}
|
|
|
|
- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
|
- if (!dev) {
|
|
- err = -ENOMEM;
|
|
- goto err_out;
|
|
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
|
+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
+ if (!gbit_res) {
|
|
+ dev_err(&pdev->dev, "failed to get gbit resource\n");
|
|
+ err = -ENOENT;
|
|
+ goto err_out;
|
|
+ }
|
|
+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
|
|
+ gbit_res->start, resource_size(gbit_res));
|
|
+ if (!ltq_gbit_membase) {
|
|
+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
|
|
+ pdev->id);
|
|
+ err = -ENOMEM;
|
|
+ goto err_out;
|
|
+ }
|
|
}
|
|
+
|
|
+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
|
strcpy(dev->name, "eth%d");
|
|
dev->netdev_ops = <q_eth_netdev_ops;
|
|
- dev->ethtool_ops = <q_etop_ethtool_ops;
|
|
priv = netdev_priv(dev);
|
|
priv->res = res;
|
|
priv->pdev = pdev;
|
|
- priv->pldata = dev_get_platdata(&pdev->dev);
|
|
priv->netdev = dev;
|
|
+ priv->tx_irq = irqres[0].start;
|
|
+ priv->rx_irq = irqres[1].start;
|
|
+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
|
|
+
|
|
+ mac = of_get_mac_address(pdev->dev.of_node);
|
|
+ if (mac)
|
|
+ memcpy(priv->mac, mac, ETH_ALEN);
|
|
+
|
|
+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
|
|
+ if (IS_ERR(priv->clk_ppe))
|
|
+ return PTR_ERR(priv->clk_ppe);
|
|
+ if (of_machine_is_compatible("lantiq,ar9")) {
|
|
+ priv->clk_switch = clk_get(&pdev->dev, "switch");
|
|
+ if (IS_ERR(priv->clk_switch))
|
|
+ return PTR_ERR(priv->clk_switch);
|
|
+ }
|
|
+ if (of_machine_is_compatible("lantiq,ase")) {
|
|
+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
|
|
+ if (IS_ERR(priv->clk_ephy))
|
|
+ return PTR_ERR(priv->clk_ephy);
|
|
+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
|
|
+ if (IS_ERR(priv->clk_ephycgu))
|
|
+ return PTR_ERR(priv->clk_ephycgu);
|
|
+ }
|
|
+
|
|
spin_lock_init(&priv->lock);
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
- for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
- if (IS_TX(i))
|
|
- netif_napi_add(dev, &priv->ch[i].napi,
|
|
- ltq_etop_poll_tx, 8);
|
|
- else if (IS_RX(i))
|
|
- netif_napi_add(dev, &priv->ch[i].napi,
|
|
- ltq_etop_poll_rx, 32);
|
|
- priv->ch[i].netdev = dev;
|
|
- }
|
|
+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
|
|
+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
|
|
+ priv->txch.netdev = dev;
|
|
+ priv->rxch.netdev = dev;
|
|
|
|
err = register_netdev(dev);
|
|
if (err)
|
|
@@ -727,31 +967,22 @@ ltq_etop_remove(struct platform_device *
|
|
return 0;
|
|
}
|
|
|
|
+static const struct of_device_id ltq_etop_match[] = {
|
|
+ { .compatible = "lantiq,etop-xway" },
|
|
+ {},
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, ltq_etop_match);
|
|
+
|
|
static struct platform_driver ltq_mii_driver = {
|
|
+ .probe = ltq_etop_probe,
|
|
.remove = ltq_etop_remove,
|
|
.driver = {
|
|
.name = "ltq_etop",
|
|
+ .of_match_table = ltq_etop_match,
|
|
},
|
|
};
|
|
|
|
-int __init
|
|
-init_ltq_etop(void)
|
|
-{
|
|
- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
|
|
-
|
|
- if (ret)
|
|
- pr_err("ltq_etop: Error registering platform driver!");
|
|
- return ret;
|
|
-}
|
|
-
|
|
-static void __exit
|
|
-exit_ltq_etop(void)
|
|
-{
|
|
- platform_driver_unregister(<q_mii_driver);
|
|
-}
|
|
-
|
|
-module_init(init_ltq_etop);
|
|
-module_exit(exit_ltq_etop);
|
|
+module_platform_driver(ltq_mii_driver);
|
|
|
|
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
|
MODULE_DESCRIPTION("Lantiq SoC ETOP");
|