mirror of https://github.com/hak5/openwrt.git
468 lines
16 KiB
Diff
468 lines
16 KiB
Diff
--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -384,6 +384,35 @@ static int ssb_device_uevent(struct devi
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ssb_dev->id.revision);
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}
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+#define ssb_config_attr(attrib, field, format_string) \
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+static ssize_t \
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+attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
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+{ \
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+ return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
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+}
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+
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+ssb_config_attr(core_num, core_index, "%u\n")
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+ssb_config_attr(coreid, id.coreid, "0x%04x\n")
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+ssb_config_attr(vendor, id.vendor, "0x%04x\n")
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+ssb_config_attr(revision, id.revision, "%u\n")
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+ssb_config_attr(irq, irq, "%u\n")
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+static ssize_t
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+name_show(struct device *dev, struct device_attribute *attr, char *buf)
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+{
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+ return sprintf(buf, "%s\n",
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+ ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
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+}
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+
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+static struct device_attribute ssb_device_attrs[] = {
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+ __ATTR_RO(name),
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+ __ATTR_RO(core_num),
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+ __ATTR_RO(coreid),
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+ __ATTR_RO(vendor),
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+ __ATTR_RO(revision),
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+ __ATTR_RO(irq),
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+ __ATTR_NULL,
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+};
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+
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static struct bus_type ssb_bustype = {
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.name = "ssb",
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.match = ssb_bus_match,
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@@ -393,6 +422,7 @@ static struct bus_type ssb_bustype = {
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.suspend = ssb_device_suspend,
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.resume = ssb_device_resume,
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.uevent = ssb_device_uevent,
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+ .dev_attrs = ssb_device_attrs,
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};
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static void ssb_buses_lock(void)
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@@ -1163,10 +1193,10 @@ void ssb_device_enable(struct ssb_device
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}
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EXPORT_SYMBOL(ssb_device_enable);
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-/* Wait for a bit in a register to get set or unset.
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+/* Wait for bitmask in a register to get set or cleared.
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* timeout is in units of ten-microseconds */
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-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
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- int timeout, int set)
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+static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
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+ int timeout, int set)
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{
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int i;
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u32 val;
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@@ -1174,7 +1204,7 @@ static int ssb_wait_bit(struct ssb_devic
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for (i = 0; i < timeout; i++) {
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val = ssb_read32(dev, reg);
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if (set) {
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- if (val & bitmask)
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+ if ((val & bitmask) == bitmask)
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return 0;
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} else {
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if (!(val & bitmask))
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@@ -1191,20 +1221,38 @@ static int ssb_wait_bit(struct ssb_devic
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void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
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{
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- u32 reject;
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+ u32 reject, val;
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if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
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return;
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reject = ssb_tmslow_reject_bitmask(dev);
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- ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
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- ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
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- ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
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- ssb_write32(dev, SSB_TMSLOW,
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- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
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- reject | SSB_TMSLOW_RESET |
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- core_specific_flags);
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- ssb_flush_tmslow(dev);
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+
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+ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
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+ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
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+ ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
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+ ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
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+
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+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
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+ val = ssb_read32(dev, SSB_IMSTATE);
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+ val |= SSB_IMSTATE_REJECT;
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+ ssb_write32(dev, SSB_IMSTATE, val);
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+ ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
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+ 0);
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+ }
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+
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+ ssb_write32(dev, SSB_TMSLOW,
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+ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
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+ reject | SSB_TMSLOW_RESET |
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+ core_specific_flags);
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+ ssb_flush_tmslow(dev);
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+
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+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
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+ val = ssb_read32(dev, SSB_IMSTATE);
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+ val &= ~SSB_IMSTATE_REJECT;
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+ ssb_write32(dev, SSB_IMSTATE, val);
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+ }
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+ }
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ssb_write32(dev, SSB_TMSLOW,
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reject | SSB_TMSLOW_RESET |
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
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out->antenna_gain.ghz5.a3 = gain;
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}
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+/* Revs 4 5 and 8 have partially shared layout */
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+static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
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+{
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+ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
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+ SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
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+ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
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+ SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
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+ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
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+ SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
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+ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
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+ SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
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+
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+ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
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+ SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
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+ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
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+ SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
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+ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
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+ SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
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+ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
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+ SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
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+
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+ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
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+ SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
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+ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
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+ SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
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+ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
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+ SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
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+ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
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+ SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
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+
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+ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
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+ SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
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+ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
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+ SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
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+ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
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+ SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
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+ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
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+ SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
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+}
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+
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static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
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SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
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SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
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+ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
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+ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
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} else {
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SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
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SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
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+ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
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+ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
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}
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SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
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SSB_SPROM4_ANTAVAIL_A_SHIFT);
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@@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
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memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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sizeof(out->antenna_gain.ghz5));
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+ sprom_extract_r458(out, in);
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+
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/* TODO - get remaining rev 4 stuff needed */
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}
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@@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
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memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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sizeof(out->antenna_gain.ghz5));
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+ sprom_extract_r458(out, in);
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+
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/* TODO - get remaining rev 8 stuff needed */
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}
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@@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus
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ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
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memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
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memset(out->et1mac, 0xFF, 6);
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+
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if ((bus->chip_id & 0xFF00) == 0x4400) {
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/* Workaround: The BCM44XX chip has a stupid revision
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* number stored in the SPROM.
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* Always extract r1. */
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out->revision = 1;
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+ ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
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+ }
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+
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+ switch (out->revision) {
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+ case 1:
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+ case 2:
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+ case 3:
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sprom_extract_r123(out, in);
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- } else if (bus->chip_id == 0x4321) {
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- /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
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- out->revision = 4;
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+ break;
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+ case 4:
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+ case 5:
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sprom_extract_r45(out, in);
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- } else {
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- switch (out->revision) {
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- case 1:
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- case 2:
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- case 3:
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- sprom_extract_r123(out, in);
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- break;
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- case 4:
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- case 5:
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- sprom_extract_r45(out, in);
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- break;
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- case 8:
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- sprom_extract_r8(out, in);
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- break;
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- default:
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- ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
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- " revision %d detected. Will extract"
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- " v1\n", out->revision);
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- out->revision = 1;
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- sprom_extract_r123(out, in);
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- }
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+ break;
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+ case 8:
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+ sprom_extract_r8(out, in);
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+ break;
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+ default:
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+ ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
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+ " revision %d detected. Will extract"
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+ " v1\n", out->revision);
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+ out->revision = 1;
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+ sprom_extract_r123(out, in);
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}
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if (out->boardflags_lo == 0xFFFF)
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@@ -618,7 +663,7 @@ static int ssb_pci_sprom_get(struct ssb_
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struct ssb_sprom *sprom)
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{
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const struct ssb_sprom *fallback;
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- int err = -ENOMEM;
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+ int err;
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u16 *buf;
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if (!ssb_is_sprom_available(bus)) {
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@@ -645,7 +690,7 @@ static int ssb_pci_sprom_get(struct ssb_
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buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
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if (!buf)
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- goto out;
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+ return -ENOMEM;
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bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
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sprom_do_read(bus, buf);
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err = sprom_check_crc(buf, bus->sprom_size);
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@@ -655,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_
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buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
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GFP_KERNEL);
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if (!buf)
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- goto out;
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+ return -ENOMEM;
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bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
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sprom_do_read(bus, buf);
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err = sprom_check_crc(buf, bus->sprom_size);
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@@ -677,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_
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out_free:
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kfree(buf);
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-out:
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return err;
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}
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--- a/drivers/ssb/pcihost_wrapper.c
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+++ b/drivers/ssb/pcihost_wrapper.c
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@@ -59,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_
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struct ssb_bus *ssb;
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int err = -ENOMEM;
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const char *name;
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+ u32 val;
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ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
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if (!ssb)
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@@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
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goto err_pci_disable;
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pci_set_master(dev);
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+ /* Disable the RETRY_TIMEOUT register (0x41) to keep
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+ * PCI Tx retries from interfering with C3 CPU state */
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+ pci_read_config_dword(dev, 0x40, &val);
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+ if ((val & 0x0000ff00) != 0)
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+ pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
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+
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err = ssb_bus_pcibus_register(ssb, dev);
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if (err)
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goto err_pci_release_regions;
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--- a/drivers/ssb/scan.c
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+++ b/drivers/ssb/scan.c
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@@ -406,10 +406,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
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/* Ignore PCI cores on PCI-E cards.
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* Ignore PCI-E cores on PCI cards. */
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if (dev->id.coreid == SSB_DEV_PCI) {
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- if (bus->host_pci->is_pcie)
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+ if (pci_is_pcie(bus->host_pci))
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continue;
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} else {
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- if (!bus->host_pci->is_pcie)
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+ if (!pci_is_pcie(bus->host_pci))
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continue;
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}
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}
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@@ -421,6 +421,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
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bus->pcicore.dev = dev;
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#endif /* CONFIG_SSB_DRIVER_PCICORE */
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break;
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+ case SSB_DEV_ETHERNET:
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+ if (bus->bustype == SSB_BUSTYPE_PCI) {
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+ if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
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+ (bus->host_pci->device & 0xFF00) == 0x4300) {
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+ /* This is a dangling ethernet core on a
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+ * wireless device. Ignore it. */
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+ continue;
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+ }
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+ }
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+ break;
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default:
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break;
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}
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--- a/include/linux/ssb/ssb.h
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+++ b/include/linux/ssb/ssb.h
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@@ -55,6 +55,10 @@ struct ssb_sprom {
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u8 tri5gl; /* 5.2GHz TX isolation */
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u8 tri5g; /* 5.3GHz TX isolation */
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u8 tri5gh; /* 5.8GHz TX isolation */
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+ u8 txpid2g[4]; /* 2GHz TX power index */
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+ u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
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+ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
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+ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
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u8 rxpo2g; /* 2GHz RX power offset */
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u8 rxpo5g; /* 5GHz RX power offset */
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u8 rssisav2g; /* 2GHz RSSI params */
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--- a/include/linux/ssb/ssb_driver_gige.h
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+++ b/include/linux/ssb/ssb_driver_gige.h
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@@ -96,16 +96,21 @@ static inline bool ssb_gige_must_flush_p
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return 0;
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}
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-extern char * nvram_get(const char *name);
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+#ifdef CONFIG_BCM47XX
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+#include <asm/mach-bcm47xx/nvram.h>
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/* Get the device MAC address */
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static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
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{
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-#ifdef CONFIG_BCM47XX
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- char *res = nvram_get("et0macaddr");
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- if (res)
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- memcpy(macaddr, res, 6);
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-#endif
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+ char buf[20];
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+ if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
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+ return;
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+ nvram_parse_macaddr(buf, macaddr);
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}
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+#else
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+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
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+{
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+}
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+#endif
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extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
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struct pci_dev *pdev);
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -85,6 +85,8 @@
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#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
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#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
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#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
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+#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
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+#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
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#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
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#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
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#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
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@@ -267,6 +269,8 @@
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/* SPROM Revision 4 */
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#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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+#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
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+#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
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#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
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#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
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@@ -298,6 +302,46 @@
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#define SSB_SPROM4_AGAIN2_SHIFT 0
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#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM4_AGAIN3_SHIFT 8
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+#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
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+#define SSB_SPROM4_TXPID2G0 0x00FF
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+#define SSB_SPROM4_TXPID2G0_SHIFT 0
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+#define SSB_SPROM4_TXPID2G1 0xFF00
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+#define SSB_SPROM4_TXPID2G1_SHIFT 8
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+#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
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+#define SSB_SPROM4_TXPID2G2 0x00FF
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+#define SSB_SPROM4_TXPID2G2_SHIFT 0
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+#define SSB_SPROM4_TXPID2G3 0xFF00
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+#define SSB_SPROM4_TXPID2G3_SHIFT 8
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+#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
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+#define SSB_SPROM4_TXPID5G0 0x00FF
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+#define SSB_SPROM4_TXPID5G0_SHIFT 0
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+#define SSB_SPROM4_TXPID5G1 0xFF00
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+#define SSB_SPROM4_TXPID5G1_SHIFT 8
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+#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
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+#define SSB_SPROM4_TXPID5G2 0x00FF
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+#define SSB_SPROM4_TXPID5G2_SHIFT 0
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+#define SSB_SPROM4_TXPID5G3 0xFF00
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+#define SSB_SPROM4_TXPID5G3_SHIFT 8
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+#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
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+#define SSB_SPROM4_TXPID5GL0 0x00FF
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+#define SSB_SPROM4_TXPID5GL0_SHIFT 0
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+#define SSB_SPROM4_TXPID5GL1 0xFF00
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+#define SSB_SPROM4_TXPID5GL1_SHIFT 8
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+#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
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+#define SSB_SPROM4_TXPID5GL2 0x00FF
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+#define SSB_SPROM4_TXPID5GL2_SHIFT 0
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+#define SSB_SPROM4_TXPID5GL3 0xFF00
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+#define SSB_SPROM4_TXPID5GL3_SHIFT 8
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+#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
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+#define SSB_SPROM4_TXPID5GH0 0x00FF
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+#define SSB_SPROM4_TXPID5GH0_SHIFT 0
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+#define SSB_SPROM4_TXPID5GH1 0xFF00
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+#define SSB_SPROM4_TXPID5GH1_SHIFT 8
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+#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
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+#define SSB_SPROM4_TXPID5GH2 0x00FF
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+#define SSB_SPROM4_TXPID5GH2_SHIFT 0
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+#define SSB_SPROM4_TXPID5GH3 0xFF00
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+#define SSB_SPROM4_TXPID5GH3_SHIFT 8
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#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
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#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
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#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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@@ -317,6 +361,8 @@
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#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
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#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
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#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
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+#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
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+#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
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#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
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