mirror of https://github.com/hak5/openwrt.git
145 lines
4.1 KiB
Diff
145 lines
4.1 KiB
Diff
From 9a3055dad80db43aeb22b247512e18e8f06bf54c Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 22 Apr 2013 23:11:42 +0200
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Subject: [PATCH 02/33] MIPS: ralink: add pinmux driver
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Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
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for this functionality with simple on/off bits. Building a full featured pinctrl
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driver would be overkill.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/Makefile | 2 +-
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arch/mips/ralink/common.h | 2 ++
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arch/mips/ralink/of.c | 2 ++
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arch/mips/ralink/pinmux.c | 77 +++++++++++++++++++++++++++++++++++++++++++++
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4 files changed, 82 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/ralink/pinmux.c
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--- a/arch/mips/ralink/Makefile
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+++ b/arch/mips/ralink/Makefile
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@@ -6,7 +6,7 @@
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# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
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+obj-y := prom.o of.o reset.o clk.o irq.o timer.o pinmux.o
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obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
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--- a/arch/mips/ralink/common.h
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+++ b/arch/mips/ralink/common.h
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@@ -52,4 +52,6 @@ extern void prom_soc_init(struct ralink_
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__iomem void *plat_of_remap_node(const char *node);
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+void ralink_pinmux(void);
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+
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#endif /* _RALINK_COMMON_H__ */
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--- a/arch/mips/ralink/of.c
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+++ b/arch/mips/ralink/of.c
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@@ -113,6 +113,8 @@ static int __init plat_of_setup(void)
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/* make sure ithat the reset controller is setup early */
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ralink_rst_init();
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+ ralink_pinmux();
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+
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return 0;
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}
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--- /dev/null
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+++ b/arch/mips/ralink/pinmux.c
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@@ -0,0 +1,92 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/of.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#include "common.h"
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+
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+#define SYSC_REG_GPIO_MODE 0x60
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+
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+static int ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps, u32* mask)
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+{
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+ for (; grps && grps->name; grps++)
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+ if (!strcmp(grps->name, name)) {
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+ *mask = grps->mask;
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+ return 0;
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+ }
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+
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+ return -1;
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+}
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+
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+void ralink_pinmux(void)
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+{
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+ const __be32 *wdt;
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+ struct device_node *np;
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+ struct property *prop;
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+ const char *uart, *pci, *pin;
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+ u32 mode = 0;
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+ int m;
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+
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+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
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+ if (!np)
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+ return;
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+
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+ of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
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+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
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+ mode |= m;
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+ pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
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+ } else {
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+ pr_err("pinmux: failed to load \"%s\"\n", pin);
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+ }
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+ }
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+
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+ of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
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+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
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+ mode &= ~m;
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+ pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
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+ } else {
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+ pr_err("pinmux: failed to load group \"%s\"\n", pin);
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+ }
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+ }
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+
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+ of_property_read_string(np, "ralink,uartmux", &uart);
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+ if (uart) {
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+ mode &= ~(rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift);
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+ if (ralink_mux_mask(uart, rt_gpio_pinmux.uart, &m)) {
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+ pr_err("pinmux: failed to load uartmux \"%s\"\n", uart);
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+ mode |= rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift;
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+ } else {
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+ mode |= m << rt_gpio_pinmux.uart_shift;
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+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
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+ }
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+ }
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+
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+ wdt = of_get_property(np, "ralink,wdtmux", NULL);
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+ if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
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+ rt_gpio_pinmux.wdt_reset();
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+
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+ pci = NULL;
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+ if (rt_gpio_pinmux.pci)
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+ of_property_read_string(np, "ralink,pcimux", &pci);
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+
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+ if (pci) {
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+ mode &= ~(rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift);
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+ if (ralink_mux_mask(pci, rt_gpio_pinmux.pci, &m)) {
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+ mode |= rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift;
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+ pr_debug("pinmux: failed to load pcimux \"%s\"\n", pci);
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+ } else {
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+ mode |= m << rt_gpio_pinmux.pci_shift;
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+ pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
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+ }
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+ }
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+
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+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
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+}
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