mirror of https://github.com/hak5/openwrt.git
500 lines
13 KiB
C
500 lines
13 KiB
C
/*
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* Copyright (c) 2018 Jianhui Zhao <jianhuizhao329@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/of_platform.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#define S5P_NFCONF 0x00
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#define S5P_NFCONT 0x04
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#define S5P_NFCMD 0x08
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#define S5P_NFADDR 0x0c
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#define S5P_NFDATA 0x10
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#define S5P_NFMECCDATA0 0x14
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#define S5P_NFMECCDATA1 0x18
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#define S5P_NFSECCDATA 0x1c
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#define S5P_NFSBLK 0x20
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#define S5P_NFEBLK 0x24
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#define S5P_NFSTAT 0x28
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#define S5P_NFMECCERR0 0x2c
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#define S5P_NFMECCERR1 0x30
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#define S5P_NFMECC0 0x34
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#define S5P_NFMECC1 0x38
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#define S5P_NFSECC 0x3c
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#define S5P_NFMLCBITPT 0x40
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#define S5P_NF8ECCERR0 0x44
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#define S5P_NF8ECCERR1 0x48
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#define S5P_NF8ECCERR2 0x4C
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#define S5P_NFM8ECC0 0x50
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#define S5P_NFM8ECC1 0x54
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#define S5P_NFM8ECC2 0x58
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#define S5P_NFM8ECC3 0x5C
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#define S5P_NFMLC8BITPT0 0x60
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#define S5P_NFMLC8BITPT1 0x64
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#define S5P_NFECCCONF 0x00
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#define S5P_NFECCCONT 0x20
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#define S5P_NFECCSTAT 0x30
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#define S5P_NFECCSECSTAT 0x40
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#define S5P_NFECCPRGECC 0x90
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#define S5P_NFECCERL 0xC0
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#define S5P_NFECCERP 0xF0
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#define S5P_NFCONF_NANDBOOT (1 << 31)
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#define S5P_NFCONF_ECCCLKCON (1 << 30)
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#define S5P_NFCONF_ECC_MLC (1 << 24)
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#define S5P_NFCONF_ECC_1BIT (0 << 23)
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#define S5P_NFCONF_ECC_4BIT (2 << 23)
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#define S5P_NFCONF_ECC_8BIT (1 << 23)
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#define S5P_NFCONF_TACLS(x) ((x) << 12)
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#define S5P_NFCONF_TWRPH0(x) ((x) << 8)
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#define S5P_NFCONF_TWRPH1(x) ((x) << 4)
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#define S5P_NFCONF_MLC (1 << 3)
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#define S5P_NFCONF_PAGESIZE (1 << 2)
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#define S5P_NFCONF_ADDRCYCLE (1 << 1)
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#define S5P_NFCONF_BUSWIDTH (1 << 0)
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#define S5P_NFCONT_ECC_ENC (1 << 18)
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#define S5P_NFCONT_LOCKTGHT (1 << 17)
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#define S5P_NFCONT_LOCKSOFT (1 << 16)
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#define S5P_NFCONT_MECCLOCK (1 << 7)
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#define S5P_NFCONT_SECCLOCK (1 << 6)
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#define S5P_NFCONT_INITMECC (1 << 5)
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#define S5P_NFCONT_INITSECC (1 << 4)
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#define S5P_NFCONT_nFCE1 (1 << 2)
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#define S5P_NFCONT_nFCE0 (1 << 1)
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#define S5P_NFCONT_MODE (1 << 0)
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#define S5P_NFSTAT_READY (1 << 0)
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#define S5P_NFECCCONT_MECCRESET (1 << 0)
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#define S5P_NFECCCONT_MECCINIT (1 << 2)
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#define S5P_NFECCCONT_ECCDIRWR (1 << 16)
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#define S5P_NFECCSTAT_ECCBUSY (1 << 31)
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enum s5p_cpu_type {
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TYPE_S5PV210,
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};
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struct s5p_nand_host {
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struct nand_chip nand_chip;
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void __iomem *nf_base;
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void __iomem *ecc_base;
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struct clk *clk[2];
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enum s5p_cpu_type cpu_type;
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};
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/*
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* See "S5PV210 iROM Application Note" for recommended ECC layout
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* ECC layout for 8-bit ECC (13 bytes/page)
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* Compatible with bl0 bootloader, see iROM appnote
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*/
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/* new oob placement block for use with hardware ecc generation
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*/
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static int s5pcxx_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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if (section)
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return -ERANGE;
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oobregion->offset = 12;
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oobregion->length = 52;
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return 0;
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}
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static int s5pcxx_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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if (section)
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return -ERANGE;
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oobregion->offset = 2;
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oobregion->length = 10;
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return 0;
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}
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static const struct mtd_ooblayout_ops s5pcxx_ooblayout_ops = {
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.ecc = s5pcxx_ooblayout_ecc,
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.free = s5pcxx_ooblayout_free,
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};
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static inline void rwl(void *reg, uint32_t rst, uint32_t set)
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{
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uint32_t r;
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r = readl(reg);
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r &= ~rst;
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r |= set;
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writel(r, reg);
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}
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/*
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* Hardware specific access to control-lines function
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*/
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static void s5p_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct s5p_nand_host *host = nand_chip->priv;
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if (dat == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(dat, host->nf_base + S5P_NFCMD);
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else
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writeb(dat, host->nf_base + S5P_NFADDR);
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}
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/*
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* Function for checking device ready pin
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*/
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static int s5p_nand_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct s5p_nand_host *host = nand_chip->priv;
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/* it's to check the RnB nand signal bit and
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* return to device ready condition in nand_base.c
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*/
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return readl(host->nf_base + S5P_NFSTAT) & S5P_NFSTAT_READY;
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}
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static void s3_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct s5p_nand_host *host = nand_chip->priv;
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u32 value = readl(host->nf_base + S5P_NFCONT);
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if (chip == -1)
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value |= S5P_NFCONT_nFCE0; /* deselect */
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else
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value &= ~S5P_NFCONT_nFCE0; /* select */
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writel(value, host->nf_base + S5P_NFCONT);
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}
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static void s5pcxx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct nand_chip *chip = mtd->priv;
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struct s5p_nand_host *host = chip->priv;
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uint32_t reg;
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/* Set ECC mode */
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reg = 3; /* 8-bit */
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reg |= (chip->ecc.size - 1) << 16;
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writel(reg, host->ecc_base + S5P_NFECCCONF);
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/* Set ECC direction */
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rwl(host->ecc_base + S5P_NFECCCONT, S5P_NFECCCONT_ECCDIRWR,
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(mode == NAND_ECC_WRITE) ? S5P_NFECCCONT_ECCDIRWR : 0);
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/* Reset status bits */
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rwl(host->ecc_base + S5P_NFECCSTAT, 0, (1 << 24) | (1 << 25));
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/* Unlock ECC */
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rwl(host->nf_base + S5P_NFCONT, S5P_NFCONT_MECCLOCK, 0);
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/* Initialize ECC */
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rwl(host->ecc_base +S5P_NFECCCONT, 0, S5P_NFECCCONT_MECCINIT);
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}
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static void readecc(void *eccbase, uint8_t *ecc_code, unsigned ecc_len)
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{
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uint32_t i, j, reg;
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for (i = 0; i < ecc_len; i += 4) {
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reg = readl(eccbase + i);
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for (j = 0; (j < 4) && (i + j < ecc_len); ++j) {
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ecc_code[i + j] = reg & 0xFF;
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reg >>= 8;
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}
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}
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}
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static int s5pcxx_nand_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code)
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{
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struct nand_chip *chip = mtd->priv;
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struct s5p_nand_host *host = chip->priv;
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/* Lock ECC */
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rwl(host->nf_base + S5P_NFCONT, 0, S5P_NFCONT_MECCLOCK);
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if (ecc_code) /* NAND_ECC_WRITE */ {
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/* ECC encoding is completed */
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while (!(readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 25)));
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readecc(host->ecc_base + S5P_NFECCPRGECC, ecc_code, chip->ecc.bytes);
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} else { /* NAND_ECC_READ */
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/* ECC decoding is completed */
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while (!(readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 24)));
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}
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return 0;
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}
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static int s5pcxx_nand_correct_data(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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int ret = 0;
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u32 errNo;
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u32 erl0, erl1, erl2, erl3, erp0, erp1;
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struct nand_chip *chip = mtd->priv;
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struct s5p_nand_host *host = chip->priv;
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/* Wait until the 8-bit ECC decoding engine is Idle */
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while (readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 31));
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errNo = readl(host->ecc_base + S5P_NFECCSECSTAT) & 0x1F;
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erl0 = readl(host->ecc_base + S5P_NFECCERL);
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erl1 = readl(host->ecc_base + S5P_NFECCERL + 0x04);
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erl2 = readl(host->ecc_base + S5P_NFECCERL + 0x08);
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erl3 = readl(host->ecc_base + S5P_NFECCERL + 0x0C);
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erp0 = readl(host->ecc_base + S5P_NFECCERP);
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erp1 = readl(host->ecc_base + S5P_NFECCERP + 0x04);
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switch (errNo) {
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case 8:
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dat[(erl3 >> 16) & 0x3FF] ^= (erp1 >> 24) & 0xFF;
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case 7:
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dat[erl3 & 0x3FF] ^= (erp1 >> 16) & 0xFF;
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case 6:
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dat[(erl2 >> 16) & 0x3FF] ^= (erp1 >> 8) & 0xFF;
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case 5:
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dat[erl2 & 0x3FF] ^= erp1 & 0xFF;
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case 4:
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dat[(erl1 >> 16) & 0x3FF] ^= (erp0 >> 24) & 0xFF;
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case 3:
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dat[erl1 & 0x3FF] ^= (erp0 >> 16) & 0xFF;
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case 2:
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dat[(erl0 >> 16) & 0x3FF] ^= (erp0 >> 8) & 0xFF;
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case 1:
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dat[erl0 & 0x3FF] ^= erp0 & 0xFF;
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case 0:
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break;
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default:
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ret = -1;
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printk("ECC uncorrectable error detected:%d\n", errNo);
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break;
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}
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return ret;
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}
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static int s5pcxx_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page)
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{
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struct mtd_oob_region oobregion = { };
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *oobecc;
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int col, stat;
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/* Read the OOB area first */
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chip->ecc.read_oob(mtd, chip, page);
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mtd_ooblayout_ecc(mtd, 0, &oobregion);
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oobecc = chip->oob_poi + oobregion.offset;
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for (i = 0, col = 0; eccsteps; eccsteps--, i += eccbytes, buf += eccsize, col += eccsize) {
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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chip->read_buf(mtd, buf, eccsize);
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chip->write_buf(mtd, oobecc + i, eccbytes);
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chip->ecc.calculate(mtd, NULL, NULL);
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stat = chip->ecc.correct(mtd, buf, NULL, NULL);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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}
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return 0;
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}
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static void s5p_nand_inithw_later(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct s5p_nand_host *host = chip->priv;
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u32 value;
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value = readl(host->nf_base + S5P_NFCONF);
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if (nand_is_slc(chip)) {
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value &= ~S5P_NFCONF_MLC;
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if (mtd->writesize == 512) {
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value |= S5P_NFCONF_PAGESIZE;
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} else {
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value &= ~S5P_NFCONF_PAGESIZE;
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}
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} else {
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value |= S5P_NFCONF_MLC;
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if (mtd->writesize == 4096)
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value &= ~S5P_NFCONF_PAGESIZE;
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else
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value |= S5P_NFCONF_PAGESIZE;
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}
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}
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static void s5p_nand_inithw(struct s5p_nand_host *host)
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{
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u32 value;
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/* Enable NAND Flash Controller */
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value = readl(host->nf_base + S5P_NFCONT);
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writel(value | S5P_NFCONT_MODE, host->nf_base + S5P_NFCONT);
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}
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static void s5p_nand_parse_dt(struct s5p_nand_host *host, struct device *dev)
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{
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host->cpu_type = (enum s5p_cpu_type)of_device_get_match_data(dev);
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}
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static int s5p_nand_probe(struct platform_device *pdev)
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{
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int ret;
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struct s5p_nand_host *host;
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struct nand_chip *nand_chip;
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struct mtd_info *mtd;
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struct resource *mem;
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/* Allocate memory for the device structure (and zero it) */
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host = devm_kzalloc(&pdev->dev, sizeof(struct s5p_nand_host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->nf_base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(host->nf_base))
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return PTR_ERR(host->nf_base);
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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host->ecc_base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(host->ecc_base))
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return PTR_ERR(host->ecc_base);
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nand_chip = &host->nand_chip;
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nand_chip->priv = host;
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nand_set_flash_node(nand_chip, pdev->dev.of_node);
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mtd = nand_to_mtd(nand_chip);
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mtd->dev.parent = &pdev->dev;
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mtd->priv = nand_chip;
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/* Disable chip select and Enable NAND Flash Controller */
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writel((0x1 << 1) | (0x1 << 0), host->nf_base + S5P_NFCONT);
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/* Set address of NAND IO lines */
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nand_chip->IO_ADDR_R = host->nf_base + S5P_NFDATA;
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nand_chip->IO_ADDR_W = host->nf_base + S5P_NFDATA;
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platform_set_drvdata(pdev, host);
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/* get the clock source and enable it */
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host->clk[0] = devm_clk_get(&pdev->dev, "nandxl");
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if (IS_ERR(host->clk[0])) {
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dev_err(&pdev->dev, "cannot get clock of nandxl\n");
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return -ENOENT;
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}
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clk_prepare_enable(host->clk[0]);
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host->clk[1] = devm_clk_get(&pdev->dev, "nand");
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if (IS_ERR(host->clk[1])) {
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dev_err(&pdev->dev, "cannot get clock of nand\n");
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return -ENOENT;
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}
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clk_prepare_enable(host->clk[1]);
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s5p_nand_parse_dt(host, &pdev->dev);
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nand_chip->select_chip = s3_nand_select_chip;
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nand_chip->cmd_ctrl = s5p_cmd_ctrl;
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nand_chip->dev_ready = s5p_nand_device_ready;
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s5p_nand_inithw(host);
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ret = nand_scan_ident(mtd, 1, NULL);
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if (ret)
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return ret;
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if (nand_chip->ecc.mode == NAND_ECC_HW) {
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nand_chip->ecc.correct = s5pcxx_nand_correct_data;
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nand_chip->ecc.calculate = s5pcxx_nand_calculate_ecc;
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nand_chip->ecc.hwctl = s5pcxx_nand_enable_hwecc;
|
|
nand_chip->ecc.read_page = s5pcxx_nand_read_page_hwecc;
|
|
|
|
nand_chip->ecc.size = 512;
|
|
nand_chip->ecc.bytes = 13;
|
|
|
|
mtd_set_ooblayout(nand_to_mtd(nand_chip), &s5pcxx_ooblayout_ops);
|
|
}
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* After you get the actual hardware information */
|
|
s5p_nand_inithw_later(mtd);
|
|
|
|
return mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
|
|
}
|
|
|
|
static int s5p_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct s5p_nand_host *host = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
|
|
|
|
nand_release(mtd);
|
|
clk_disable_unprepare(host->clk[0]); /* nandxl */
|
|
clk_disable_unprepare(host->clk[1]); /* nand */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id s5p_nand_match[] = {
|
|
{ .compatible = "samsung,s5pv210-nand", .data = TYPE_S5PV210 },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, s5p_nand_match);
|
|
|
|
static struct platform_driver s5p_nand_driver = {
|
|
.probe = s5p_nand_probe,
|
|
.remove = s5p_nand_remove,
|
|
.driver = {
|
|
.name = "s5p-nand",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = s5p_nand_match,
|
|
},
|
|
};
|
|
module_platform_driver(s5p_nand_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Jianhui Zhao <jianhuizhao329@gmail.com>");
|
|
MODULE_DESCRIPTION("S5Pxx MTD NAND driver");
|