mirror of https://github.com/hak5/openwrt.git
432 lines
11 KiB
Diff
432 lines
11 KiB
Diff
From 45444cb631555e2dc16b95d779b10aa075c7482e Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Fri, 24 Jun 2016 22:14:13 +0200
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Subject: [PATCH 05/16] pinctrl: add a pincontrol driver for BCM6348
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Add a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of
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up to ten gpios into fourteen potential functions. It does not allow
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muxing individual pins. Some functions require more than one group to be
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muxed to the same function.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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drivers/pinctrl/bcm63xx/Kconfig | 7 +
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drivers/pinctrl/bcm63xx/Makefile | 1 +
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drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 391 ++++++++++++++++++++++++++++++
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3 files changed, 399 insertions(+)
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create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
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--- a/drivers/pinctrl/bcm63xx/Kconfig
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+++ b/drivers/pinctrl/bcm63xx/Kconfig
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@@ -8,3 +8,10 @@ config PINCTRL_BCM6328
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select PINCONF
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select PINCTRL_BCM63XX
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select GENERIC_PINCONF
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+
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+config PINCTRL_BCM6348
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+ bool "BCM6348 pincontrol driver" if COMPILE_TEST
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+ select PINMUX
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+ select PINCONF
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+ select PINCTRL_BCM63XX
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+ select GENERIC_PINCONF
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--- a/drivers/pinctrl/bcm63xx/Makefile
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+++ b/drivers/pinctrl/bcm63xx/Makefile
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@@ -1,2 +1,3 @@
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obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
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obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
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+obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o
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--- /dev/null
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+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
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@@ -0,0 +1,391 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/spinlock.h>
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+#include <linux/bitops.h>
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+#include <linux/gpio.h>
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+#include <linux/of.h>
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+#include <linux/of_gpio.h>
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+#include <linux/slab.h>
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+#include <linux/platform_device.h>
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+
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+#include <linux/pinctrl/machine.h>
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+#include <linux/pinctrl/pinconf.h>
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+#include <linux/pinctrl/pinconf-generic.h>
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+#include <linux/pinctrl/pinmux.h>
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+
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+#include "../core.h"
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+#include "../pinctrl-utils.h"
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+
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+#include "pinctrl-bcm63xx.h"
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+
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+#define BCM6348_NGPIO 37
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+
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+#define MAX_GROUP 4
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+#define PINS_PER_GROUP 8
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+#define PIN_TO_GROUP(pin) (MAX_GROUP - ((pin) / PINS_PER_GROUP))
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+#define GROUP_SHIFT(pin) (PIN_TO_GROUP(pin) * 4)
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+#define GROUP_MASK(pin) (0xf << GROUP_SHIFT(pin))
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+
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+struct bcm6348_pingroup {
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+ const char *name;
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+ const unsigned * const pins;
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+ const unsigned num_pins;
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+};
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+
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+struct bcm6348_function {
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+ const char *name;
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+ const char * const *groups;
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+ const unsigned num_groups;
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+ unsigned int value;
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+};
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+
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+struct bcm6348_pinctrl {
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+ struct pinctrl_dev *pctldev;
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+ struct pinctrl_desc desc;
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+
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+ void __iomem *mode;
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+
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+ /* register access lock */
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+ spinlock_t lock;
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+
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+ struct gpio_chip gpio[2];
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+};
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+
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+#define BCM6348_PIN(a, b, group) \
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+ { \
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+ .number = a, \
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+ .name = b, \
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+ .drv_data = (void *)(group), \
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+ }
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+
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+static const struct pinctrl_pin_desc bcm6348_pins[] = {
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+ BCM6348_PIN(0, "gpio0", 4),
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+ BCM6348_PIN(1, "gpio1", 4),
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+ BCM6348_PIN(2, "gpio2", 4),
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+ BCM6348_PIN(3, "gpio3", 4),
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+ BCM6348_PIN(4, "gpio4", 4),
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+ BCM6348_PIN(5, "gpio5", 4),
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+ BCM6348_PIN(6, "gpio6", 4),
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+ BCM6348_PIN(7, "gpio7", 4),
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+ BCM6348_PIN(8, "gpio8", 3),
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+ BCM6348_PIN(9, "gpio9", 3),
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+ BCM6348_PIN(10, "gpio10", 3),
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+ BCM6348_PIN(11, "gpio11", 3),
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+ BCM6348_PIN(12, "gpio12", 3),
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+ BCM6348_PIN(13, "gpio13", 3),
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+ BCM6348_PIN(14, "gpio14", 3),
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+ BCM6348_PIN(15, "gpio15", 3),
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+ BCM6348_PIN(16, "gpio16", 2),
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+ BCM6348_PIN(17, "gpio17", 2),
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+ BCM6348_PIN(18, "gpio18", 2),
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+ BCM6348_PIN(19, "gpio19", 2),
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+ BCM6348_PIN(20, "gpio20", 2),
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+ BCM6348_PIN(21, "gpio21", 2),
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+ BCM6348_PIN(22, "gpio22", 1),
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+ BCM6348_PIN(23, "gpio23", 1),
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+ BCM6348_PIN(24, "gpio24", 1),
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+ BCM6348_PIN(25, "gpio25", 1),
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+ BCM6348_PIN(26, "gpio26", 1),
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+ BCM6348_PIN(27, "gpio27", 1),
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+ BCM6348_PIN(28, "gpio28", 1),
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+ BCM6348_PIN(29, "gpio29", 1),
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+ BCM6348_PIN(30, "gpio30", 1),
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+ BCM6348_PIN(31, "gpio31", 1),
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+ BCM6348_PIN(32, "gpio32", 0),
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+ BCM6348_PIN(33, "gpio33", 0),
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+ BCM6348_PIN(34, "gpio34", 0),
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+ BCM6348_PIN(35, "gpio35", 0),
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+ BCM6348_PIN(36, "gpio36", 0),
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+};
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+
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+enum bcm6348_muxes {
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+ BCM6348_MUX_GPIO = 0,
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+ BCM6348_MUX_EXT_EPHY,
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+ BCM6348_MUX_MII_SNOOP,
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+ BCM6348_MUX_LEGACY_LED,
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+ BCM6348_MUX_MII_PCCARD,
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+ BCM6348_MUX_PCI,
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+ BCM6348_MUX_SPI_MASTER_UART,
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+ BCM6348_MUX_EXT_MII,
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+ BCM6348_MUX_UTOPIA,
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+ BCM6348_MUX_DIAG,
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+};
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+
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+static unsigned group0_pins[] = {
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+ 32, 33, 34, 35, 36,
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+};
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+
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+static unsigned group1_pins[] = {
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+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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+};
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+
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+static unsigned group2_pins[] = {
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+ 16, 17, 18, 19, 20, 21,
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+};
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+
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+static unsigned group3_pins[] = {
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+ 8, 9, 10, 11, 12, 13, 14, 15,
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+};
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+
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+static unsigned group4_pins[] = {
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+ 0, 1, 2, 3, 4, 5, 6, 7,
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+};
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+
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+#define BCM6348_GROUP(n) \
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+ { \
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+ .name = #n, \
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+ .pins = n##_pins, \
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+ .num_pins = ARRAY_SIZE(n##_pins), \
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+ } \
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+
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+static struct bcm6348_pingroup bcm6348_groups[] = {
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+ BCM6348_GROUP(group0),
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+ BCM6348_GROUP(group1),
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+ BCM6348_GROUP(group2),
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+ BCM6348_GROUP(group3),
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+ BCM6348_GROUP(group4),
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+};
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+
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+static const char * const ext_mii_groups[] = {
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+ "group0",
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+ "group3",
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+};
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+
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+static const char * const ext_ephy_groups[] = {
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+ "group1",
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+ "group4"
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+};
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+
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+static const char * const mii_snoop_groups[] = {
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+ "group1",
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+ "group4",
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+};
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+
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+static const char * const legacy_led_groups[] = {
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+ "group4",
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+};
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+
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+static const char * const mii_pccard_groups[] = {
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+ "group1",
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+};
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+
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+static const char * const pci_groups[] = {
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+ "group2",
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+};
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+
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+static const char * const spi_master_uart_groups[] = {
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+ "group1",
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+};
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+
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+static const char * const utopia_groups[] = {
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+ "group0",
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+ "group1",
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+ "group3",
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+};
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+
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+static const char * const diag_groups[] = {
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+ "group0",
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+ "group1",
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+ "group2",
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+ "group4",
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+};
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+
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+#define BCM6348_FUN(n, f) \
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+ { \
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+ .name = #n, \
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+ .groups = n##_groups, \
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+ .num_groups = ARRAY_SIZE(n##_groups), \
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+ .value = BCM6348_MUX_##f, \
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+ }
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+
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+static const struct bcm6348_function bcm6348_funcs[] = {
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+ BCM6348_FUN(ext_mii, EXT_MII),
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+ BCM6348_FUN(ext_ephy, EXT_EPHY),
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+ BCM6348_FUN(mii_snoop, MII_SNOOP),
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+ BCM6348_FUN(legacy_led, LEGACY_LED),
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+ BCM6348_FUN(mii_pccard, MII_PCCARD),
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+ BCM6348_FUN(pci, PCI),
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+ BCM6348_FUN(spi_master_uart, SPI_MASTER_UART),
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+ BCM6348_FUN(utopia, UTOPIA),
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+ BCM6348_FUN(diag, DIAG),
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+};
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+
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+static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6348_groups);
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+}
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+
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+static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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+ unsigned group)
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+{
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+ return bcm6348_groups[group].name;
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+}
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+
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+static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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+ unsigned group, const unsigned **pins,
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+ unsigned *num_pins)
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+{
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+ *pins = bcm6348_groups[group].pins;
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+ *num_pins = bcm6348_groups[group].num_pins;
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+
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+ return 0;
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+}
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+
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+static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6348_funcs);
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+}
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+
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+static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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+ unsigned selector)
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+{
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+ return bcm6348_funcs[selector].name;
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+}
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+
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+static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,
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+ unsigned selector,
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+ const char * const **groups,
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+ unsigned * const num_groups)
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+{
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+ *groups = bcm6348_funcs[selector].groups;
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+ *num_groups = bcm6348_funcs[selector].num_groups;
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+
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+ return 0;
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+}
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+
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+static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)
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+{
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(&pctl->lock, flags);
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+
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+ reg = __raw_readl(pctl->mode);
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+ reg &= ~mask;
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+ reg |= val & mask;
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+ __raw_writel(reg, pctl->mode);
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+
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+ spin_unlock_irqrestore(&pctl->lock, flags);
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+}
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+
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+static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,
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+ unsigned selector, unsigned group)
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+{
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+ struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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+ const struct bcm6348_pingroup *grp = &bcm6348_groups[group];
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+ const struct bcm6348_function *f = &bcm6348_funcs[selector];
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+ u32 mask, val;
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+
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+ /*
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+ * pins n..(n+7) share the same group, so we only need to look at
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+ * the first pin.
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+ */
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+ mask = GROUP_MASK(grp->pins[0]);
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+ val = f->value << GROUP_SHIFT(grp->pins[0]);
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+
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+ bcm6348_rmw_mux(pctl, mask, val);
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+
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+ return 0;
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+}
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+
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+static int bcm6348_gpio_request_enable(struct pinctrl_dev *pctldev,
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+ struct pinctrl_gpio_range *range,
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+ unsigned offset)
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+{
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+ struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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+ struct pin_desc *desc;
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+ u32 mask;
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+
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+ /* don't reconfigure if already muxed */
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+ desc = pin_desc_get(pctldev, offset);
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+ if (desc->mux_usecount)
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+ return 0;
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+
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+ mask = GROUP_MASK(offset);
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+
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+ /* disable all functions using this pin */
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+ bcm6348_rmw_mux(pctl, mask, 0);
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+
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+ return 0;
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+}
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+
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+static struct pinctrl_ops bcm6348_pctl_ops = {
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+ .get_groups_count = bcm6348_pinctrl_get_group_count,
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+ .get_group_name = bcm6348_pinctrl_get_group_name,
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+ .get_group_pins = bcm6348_pinctrl_get_group_pins,
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+#ifdef CONFIG_OF
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+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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+ .dt_free_map = pinctrl_utils_free_map,
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+#endif
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+};
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+
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+static struct pinmux_ops bcm6348_pmx_ops = {
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+ .get_functions_count = bcm6348_pinctrl_get_func_count,
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+ .get_function_name = bcm6348_pinctrl_get_func_name,
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+ .get_function_groups = bcm6348_pinctrl_get_groups,
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+ .set_mux = bcm6348_pinctrl_set_mux,
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+ .gpio_request_enable = bcm6348_gpio_request_enable,
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+ .strict = true,
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+};
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+
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+static int bcm6348_pinctrl_probe(struct platform_device *pdev)
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+{
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+ struct bcm6348_pinctrl *pctl;
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+ struct resource *res;
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+ void __iomem *mode;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
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+ mode = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(mode))
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+ return PTR_ERR(mode);
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+
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+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
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+ if (!pctl)
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+ return -ENOMEM;
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+
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+ spin_lock_init(&pctl->lock);
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+
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+ pctl->mode = mode;
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+
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+ /* disable all muxes by default */
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+ __raw_writel(0, pctl->mode);
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+
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+ pctl->desc.name = dev_name(&pdev->dev);
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+ pctl->desc.owner = THIS_MODULE;
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+ pctl->desc.pctlops = &bcm6348_pctl_ops;
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+ pctl->desc.pmxops = &bcm6348_pmx_ops;
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+
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+ pctl->desc.npins = ARRAY_SIZE(bcm6348_pins);
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+ pctl->desc.pins = bcm6348_pins;
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+
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+ platform_set_drvdata(pdev, pctl);
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+
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+ pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
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+ pctl->gpio, BCM6348_NGPIO);
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+ if (IS_ERR(pctl->pctldev))
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+ return PTR_ERR(pctl->pctldev);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id bcm6348_pinctrl_match[] = {
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+ { .compatible = "brcm,bcm6348-pinctrl", },
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+ { },
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+};
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+
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+static struct platform_driver bcm6348_pinctrl_driver = {
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+ .probe = bcm6348_pinctrl_probe,
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+ .driver = {
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+ .name = "bcm6348-pinctrl",
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+ .of_match_table = bcm6348_pinctrl_match,
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+ },
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+};
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+
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+builtin_platform_driver(bcm6348_pinctrl_driver);
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