mirror of https://github.com/hak5/openwrt.git
64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Subject: net: phy: at803x: add support for AT8032
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Like AT8030, this PHY needs the GPIO reset workaround
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -62,8 +62,10 @@
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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+#define ATH8032_PHY_ID 0x004dd023
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#define ATH8035_PHY_ID 0x004dd072
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#define AT803X_PHY_ID_MASK 0xffffffef
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+#define AT8032_PHY_ID_MASK 0xffffffff
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MODULE_DESCRIPTION("Atheros 803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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@@ -308,7 +310,7 @@ static void at803x_link_change_notify(st
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struct at803x_priv *priv = phydev->priv;
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/*
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- * Conduct a hardware reset for AT8030 every time a link loss is
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+ * Conduct a hardware reset for AT8030/2 every time a link loss is
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* signalled. This is necessary to circumvent a hardware bug that
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* occurs when the cable is unplugged while TX packets are pending
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* in the FIFO. In such cases, the FIFO enters an error mode it
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@@ -414,6 +416,24 @@ static struct phy_driver at803x_driver[]
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.aneg_done = at803x_aneg_done,
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.ack_interrupt = &at803x_ack_interrupt,
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.config_intr = &at803x_config_intr,
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+}, {
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+ /* ATHEROS 8032 */
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+ .phy_id = ATH8032_PHY_ID,
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+ .name = "Atheros 8032 ethernet",
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+ .phy_id_mask = AT8032_PHY_ID_MASK,
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+ .probe = at803x_probe,
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+ .config_init = at803x_config_init,
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+ .link_change_notify = at803x_link_change_notify,
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+ .set_wol = at803x_set_wol,
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+ .get_wol = at803x_get_wol,
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+ .suspend = at803x_suspend,
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+ .resume = at803x_resume,
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+ .features = PHY_BASIC_FEATURES,
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+ .flags = PHY_HAS_INTERRUPT,
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+ .config_aneg = genphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = at803x_ack_interrupt,
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+ .config_intr = at803x_config_intr,
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} };
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module_phy_driver(at803x_driver);
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@@ -421,6 +441,7 @@ module_phy_driver(at803x_driver);
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static struct mdio_device_id __maybe_unused atheros_tbl[] = {
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{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
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{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
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+ { ATH8032_PHY_ID, AT8032_PHY_ID_MASK },
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{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
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{ }
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};
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